EP2002541A4 - Direct digital synthesizer with variable reference for improved spurious performance - Google Patents

Direct digital synthesizer with variable reference for improved spurious performance

Info

Publication number: EP2002541A4
Authority: EP; European Patent Office
Prior art keywords: direct digital; variable reference; digital synthesizer; spurious performance; improved spurious
Prior art date: 2006-03-08
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Withdrawn

Other versions

Inventor

Nicholas G Cafaro

Thomas L Gradishar

Robert E Stengel

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Motorola Solutions Inc

Original Assignee

Motorola Solutions Inc

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

2006-03-08

Filing date

2007-03-08

Publication date

2012-08-29

2007-03-08Application filed by Motorola Solutions IncfiledCriticalMotorola Solutions Inc

2008-12-17Publication of EP2002541A2publicationCriticalpatent/EP2002541A2/en

2012-08-29Publication of EP2002541A4publicationCriticalpatent/EP2002541A4/en

StatusWithdrawnlegal-statusCriticalCurrent

Classifications

- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/26—Time-delay networks
- H03H11/265—Time-delay networks with adjustable delay
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/26—Time-delay networks
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/1806—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop the frequency divider comprising a phase accumulator generating the frequency divided signal
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00058—Variable delay controlled by a digital setting
- H03K2005/00065—Variable delay controlled by a digital setting by current control, e.g. by parallel current control transistors

Landscapes

Physics & Mathematics (AREA)
Nonlinear Science (AREA)
Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Pulse Circuits (AREA)

EP07758145A2006-03-082007-03-08Direct digital synthesizer with variable reference for improved spurious performanceWithdrawnEP2002541A4 (en)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
US11/370,689US7315215B2 (en)	2006-03-08	2006-03-08	Direct digital synthesizer with variable reference for improved spurious performance
PCT/US2007/063565WO2007104010A2 (en)	2006-03-08	2007-03-08	Direct digital synthesizer with variable reference for improved spurious performance

Publications (2)

Publication Number	Publication Date
EP2002541A2 EP2002541A2 (en)	2008-12-17
EP2002541A4true EP2002541A4 (en)	2012-08-29

Family

ID=38475854

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
EP07758145AWithdrawnEP2002541A4 (en)	2006-03-08	2007-03-08	Direct digital synthesizer with variable reference for improved spurious performance

Country Status (5)

Country	Link
US (2)	US7315215B2 (en)
EP (1)	EP2002541A4 (en)
KR (1)	KR100970808B1 (en)
CN (1)	CN101454981A (en)
WO (1)	WO2007104010A2 (en)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US7315215B2 (en)*	2006-03-08	2008-01-01	Motorola,, Inc.	Direct digital synthesizer with variable reference for improved spurious performance
US8358993B2 (en)*	2006-07-25	2013-01-22	Analog Devices, Inc.	Image rejection calibration system
US20090079487A1 (en)*	2007-09-26	2009-03-26	Telefonaktiebolaget Lm Ericsson (Publ)	Time Delay Line with Low Sensitivity to Process Variations
US7724097B2 (en)*	2008-08-28	2010-05-25	Resonance Semiconductor Corporation	Direct digital synthesizer for reference frequency generation
US8238865B2 (en)*	2009-10-09	2012-08-07	Analog Devices, Inc.	Image calibration and correction for low-IF receivers
CN102111150B (en)*	2009-12-23	2012-10-31	中国科学院微电子研究所	Digital edge aligner for phase frequency detector
WO2011079471A1 (en)*	2009-12-31	2011-07-07	海能达通信股份有限公司	Method and system for optimizing fractional spurs
CN102404006A (en)*	2011-10-27	2012-04-04	天津大学	4G radio over fiber-orientated frequency synthesizing circuit
US9001868B2 (en)	2013-04-30	2015-04-07	Honeywell International Inc.	Systems and methods for enhancing GNSS numerically controlled oscillators
US9501087B1 (en)	2015-06-17	2016-11-22	Raytheon Company	Dynamically clocked DDS for spur optimization
WO2017105349A1 (en)*	2015-12-16	2017-06-22	Agency For Science, Technology And Research	Frequency synthesizers and methods for synthesizing a frequency
DE102016110344A1 (en)*	2016-06-03	2017-12-07	Infineon Technologies Ag	RF RECEIVER WITH BUILT-IN SELF-TEST FUNCTION
CN106933299B (en)*	2017-03-09	2019-07-19	黄山学院	Low-power DDS circuit with amplitude and phase error self-calibration
CN108736889B (en)*	2018-04-24	2022-04-01	西南电子技术研究所（中国电子科技集团公司第十研究所）	Low spurious/low phase noise frequency synthesizer
KR102749239B1 (en)*	2019-07-04	2024-12-31	에스케이하이닉스 주식회사	A delay locked loop
US11750201B2 (en)	2019-09-06	2023-09-05	SK Hynix Inc.	Delay line, a delay locked loop circuit and a semiconductor apparatus using the delay line and the delay locked loop circuit
US11206026B2 (en)	2019-09-06	2021-12-21	SK Hynix Inc.	Delay line, a delay locked loop circuit and a semiconductor apparatus using the delay line and the delay locked loop circuit
US11223362B2 (en)	2020-05-14	2022-01-11	Mediatek Inc.	Phase-locked loop circuit and digital-to-time convertor error cancelation method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US5329253A (en)*	1991-10-25	1994-07-12	Nec Corporation	Frequency synthesis using frequency controlled carrier modulated with PLL feedback signal
US6768356B1 (en)*	2000-09-07	2004-07-27	Iowa State University Research Foundation, Inc.	Apparatus for and method of implementing time-interleaved architecture
US6794913B1 (en)*	2003-05-29	2004-09-21	Motorola, Inc.	Delay locked loop with digital to phase converter compensation
US20050237093A1 (en)*	2004-04-22	2005-10-27	Wilhite Jeffrey B	Adjustable frequency delay-locked loop

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4409564A (en)	1981-03-20	1983-10-11	Wavetek	Pulse delay compensation for frequency synthesizer
GB9414729D0 (en)*	1994-07-21	1994-09-07	Mitel Corp	Digital phase locked loop
SE0301005D0 (en)*	2003-04-03	2003-04-03	Ericsson Telefon Ab L M	Method and system of jitter compensation
US7315215B2 (en)*	2006-03-08	2008-01-01	Motorola,, Inc.	Direct digital synthesizer with variable reference for improved spurious performance

2006
- 2006-03-08USUS11/370,689patent/US7315215B2/enactiveActive
2007
- 2007-03-08EPEP07758145Apatent/EP2002541A4/ennot_activeWithdrawn
- 2007-03-08CNCNA2007800081187Apatent/CN101454981A/enactivePending
- 2007-03-08WOPCT/US2007/063565patent/WO2007104010A2/enactiveApplication Filing
- 2007-03-08KRKR1020087021746Apatent/KR100970808B1/ennot_activeExpired - Fee Related
- 2007-09-26USUS11/861,860patent/US7570096B2/enactiveActive

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US5329253A (en)*	1991-10-25	1994-07-12	Nec Corporation	Frequency synthesis using frequency controlled carrier modulated with PLL feedback signal
US6768356B1 (en)*	2000-09-07	2004-07-27	Iowa State University Research Foundation, Inc.	Apparatus for and method of implementing time-interleaved architecture
US6794913B1 (en)*	2003-05-29	2004-09-21	Motorola, Inc.	Delay locked loop with digital to phase converter compensation
US20050237093A1 (en)*	2004-04-22	2005-10-27	Wilhite Jeffrey B	Adjustable frequency delay-locked loop

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references ofWO2007104010A2*

Also Published As

Publication number	Publication date
US7315215B2 (en)	2008-01-01
US7570096B2 (en)	2009-08-04
KR20080096816A (en)	2008-11-03
EP2002541A2 (en)	2008-12-17
WO2007104010A3 (en)	2008-11-27
CN101454981A (en)	2009-06-10
US20080258791A1 (en)	2008-10-23
US20070222492A1 (en)	2007-09-27
KR100970808B1 (en)	2010-07-16
WO2007104010A2 (en)	2007-09-13

Publication	Publication Date	Title
EP2002541A4 (en)	2012-08-29	Direct digital synthesizer with variable reference for improved spurious performance
GB2475663B (en)	2012-08-15	Direct digital synthesizer for reference frequency generation
GB2440157B (en)	2011-01-19	Variable phase mechanism
GB0609365D0 (en)	2006-06-21	Phase retrieval
IL194760A0 (en)	2009-08-03	Molded elements
GB2425366B (en)	2007-09-26	Controls for digital lighting
GB2464637B (en)	2012-05-02	Digital integrated transmitter based on four-path phase modulation
IL190589A0 (en)	2008-12-29	Level-restorer supply-regulated pll
AU310471S (en)	2006-10-10	Wheelbarrow with pivoting arcuate hopper
EP2026736A4 (en)	2011-05-25	Multi function wrapper
GB0905373D0 (en)	2009-05-13	Not published
GB0615146D0 (en)	2006-09-06	Digital pen
GB0620925D0 (en)	2006-11-29	Biodiesel synthesis
GB0618675D0 (en)	2006-11-01	Voltage-controlled oscillator
GB2455823B (en)	2013-01-16	Adapting cut-off frequency
GB0619037D0 (en)	2006-11-08	Eco-wheelie bin
GB0622945D0 (en)	2006-12-27	Fractional digital PLL
GB2451475B (en)	2012-01-11	Frequency synthesizer
GB0510976D0 (en)	2005-07-06	Phase shifting arrangement
GB0511161D0 (en)	2005-07-06	Phase difference calculator
GB0624967D0 (en)	2007-01-24	Not published
GB0619653D0 (en)	2006-11-15	Twin bin
GB0618028D0 (en)	2006-10-25	Digital brise soleil
GB2422575B (en)	2009-04-15	Files
GB0609234D0 (en)	2006-06-21	File

Legal Events

Date	Code	Title	Description
2008-11-14	PUAI	Public reference made under article 153(3) epc to a published international application that has entered the european phase	Free format text:ORIGINAL CODE: 0009012
2008-12-17	17P	Request for examination filed	Effective date:20081007
2008-12-17	AK	Designated contracting states	Kind code of ref document:A2 Designated state(s):AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC MT NL PL PT RO SE SI SK TR
2008-12-17	AX	Request for extension of the european patent	Extension state:AL BA HR MK RS
2009-01-07	R17D	Deferred search report published (corrected)	Effective date:20081127
2009-01-21	RIC1	Information provided on ipc code assigned before grant	Ipc:H03L 7/08 20060101AFI20081212BHEP
2011-04-06	RAP1	Party data changed (applicant data changed or rights of an application transferred)	Owner name:MOTOROLA SOLUTIONS, INC.
2012-08-08	DAX	Request for extension of the european patent (deleted)
2012-08-29	A4	Supplementary search report drawn up and despatched	Effective date:20120731
2012-08-29	RIC1	Information provided on ipc code assigned before grant	Ipc:H03L 7/08 20060101AFI20120725BHEP
2013-03-13	17Q	First examination report despatched	Effective date:20130215
2013-11-01	STAA	Information on the status of an ep patent application or granted ep patent	Free format text:STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN
2013-12-04	18D	Application deemed to be withdrawn	Effective date:20130626

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