EP1227381A1 - Field instrument with data bus communication - Google Patents

Abstract

The present invention includes a processcontrol instrument (100) having an improved data busprotocol for facilitating communications between masterand slave nodes. The process control instrument (100)includes a microprocessor (200) operating in accordancewith the SPI data bus protocol, first and secondperipheral devices (204,206), and a data bus (220)coupled to the microprocessor and the first and secondperipheral devices. The improved data bus protocol usedin the process control instruments of the presentinvention provides numerous advantages such as reducedprinted circuit board space requirements and greaterinterchangeability of peripheral and master nodecomponents.

Description

BACKGROUND OF THE INVENTION
• Tne present invention relates generally to thefield of process control instruments. Moreparticularly, the present invention relates to a newdata bus system and protocol for communication betweenmaster control nodes and peripheral devices in processcontrol field instrument operating in accordance withthe standard Motorola™ SPI protocol.
• Process control instruments such astransmitters and controllers are used to monitor and/orcontrol industrial processes. In some recent designs,these process control instruments include a number ofinternal devices or components such as a microprocessorwhich functions as a master node and a number ofperipheral electronic devices which act as slave nodes.The peripheral electronic devices include, for example,pressure sensors for measuring process pressures,temperature sensors for measuring process temperatures,valves for controlling a process, digital-to-analog andanalog-to-digital converters for converting datatransferred between analog and digital devices,communication links for transmitting and receivinginformation over a two-wire process control loop, memorydevices for storing instructions or monitored processresults, and displays for providing a graphicalrepresentation of some process related information.Typically, all of these devices are internal to theinstrument or in close proximity to the instrument. Theinstrument can include any combination of the abovementioned slave nodes (i.e., peripheral devices). Thevarious slave nodes in the process control instrument communicate on a data bus which connects each of theperipheral devices to the master node.
• Frequently, the master node in a processcontrol instrument is a Motorola or compatiblemicroprocessor or microcontroller. For example, theMotorola 68HC05 and 68HC11 microcontrollers are commonlyused as the master node in process control instruments.These and other microcontrollers are designed to operatein accordance with the standard Serial PeripheralInterface (SPI) bus communication protocol which isdefined by Motorola in the M68HC11 Reference Manualwhich is hereby incorporated by reference. While use ofmicroprocessors or microcontrollers which operate inaccordance with the SPI protocol is in manycircumstances advantageous, the SPI protocol itselfintroduces a number of disadvantageous data busrequirements and has a number of shortcomings. Forexample, in process control instruments, the size of thedevices can be critical. Therefore, smaller printedcircuit boards (PCB's) are preferred for inside theprocess control instrument. However, with the SPIprotocol, a separate chip select (CS) data bus line isrequired for each peripheral device which is to beconnected to the master node. In addition to requiringmore PCB space for the additional CS bus lines, thisrequirement of the standard SPI protocol also requiresadditional pins on the master node chip. Anotherdisadvantage of the SPI protocol relates to thedifficulties of adding or changing the master node orslave nodes. Typically, each device which communicateson the process control instrument data bus has apredetermined address. Adding, removing orinterchanging nodes requires that the bus and/oraddressing be customized to accommodate the change.
• As illustrated above, it is apparent that theSPI protocol provides a number of disadvantages,particularly in data buses within process controlinstruments. The present invention overcomes these andother disadvantages of the standard SPI communicationsprotocol.
SUMMARY OF THE INVENTION
• The present invention is a process controlinstrument having an improved data bus protocol forfacilitating communications between internal masternodes or microprocessors and internal slave nodes orperipheral devices. The process control instrumentincludes at least one microprocessor operating inaccordance with the standard SPI data bus protocol,first and second peripheral devices, and a data buscoupled to the microprocessor and the first and secondperipheral devices. The improved data bus protocol usedin the process control instruments of the presentinvention provides numerous advantages such as reducedprinted circuit board space requirements and greaterinterchangeability of peripheral and master nodecomponents.
• In some embodiments of the process controlinstrument of the present invention, the improved databus protocol has a single chip select (CS) data bus linewhich is coupled to the CS connections on each of themaster and slave nodes. In other embodiments, the CSlines are eliminated altogether. In other embodiments,the process control instrument has a data bus with a bi-directionalmaster-in-slave-out (MISO) line adapted tofacilitate serial communications both from theperipheral devices to the microprocessor, and betweenthe peripheral devices. In still other embodiments ofthe process control instrument of the present invention, the data bus physical interconnection and protocol areadapted such that the peripheral devices can bedynamically assigned addresses for communication on thedata bus.
BRIEF DESCRIPTION OF THE DRAWINGS
• Figure 1 is a diagrammatic view of a portionof a process control system having a process controlinstrument according to the present invention, a processpipeline, and a remote device for monitoring orcontrolling a process.
• Figure 2 is a block diagram of a preferredembodiment of the process control instrument of thepresent invention including master nodes operating inaccordance with the SPI protocol, peripheral deviceslave nodes, and a data bus coupling together the masterand slave nodes.
• Figure 3 is a timing diagram illustrating thedata bus protocol used in the process controlinstruments of the present invention.
• Figure 4 is a diagrammatic illustration of aninstruction byte structure used by the master and slavenodes of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
• The present invention includes an improvedinternal data bus communication protocol for processcontrol instruments based on the Motorola™ SerialPeripheral Interface (SPI). The invention may be usedfor communication between devices or components whichare connected on a data bus of the instrument.Typically, the data bus is internal to the instrument.The conventional or standard SPI protocol supports amaster node and plural slave nodes for synchronous bi-directionalserial communications. Standard SPIprotocol requires a separate chip select (CS) data bus line for each slave node. The data bus protocol used inprocess control instruments of the present inventionenhances the standard SPI protocol by allowing a singleCS line to control multiple slave nodes, by providing anaccess arbitration mechanism to enable multiple slavenodes to access the data bus on their own initiative,and by adding peer-to-peer and broadcast capabilities.
• Figure 1 is a diagrammatic illustration of aportion of a process control system having acontrolroom 90 coupled to aprocess control instrument 100controlling or monitoring a process.Control room 90 ismodeled as avoltage source 92 in series withresistance94. In the industrial process application illustrated,afluid 102 flows through apipeline 104.Processcontrol instrument 100, which communicates with otherprocess control instruments or with a master controlunit via two-wire process control loop orcircuit 106carrying loop current I_L, monitors or controls remotedevice 108 (such as a motor or switch) via aconnection107 in order to monitor or control the process. Forexample,remote device 108 can include a valve, whileprocess control instrument 100 includes a valvepositioner as a peripheral device. In the alternative,remote device 108 can include a pressure sensor, atemperature sensor or any of a wide variety of otherremote devices known in the art used in the processcontrol environment. Frequently, multipleprocesscontrol instruments 100 are coupled to two-wire controlloop 106 for controlling or monitoring various aspectsof the process.
• Figure 2 is a block diagram of process controlinstrument showing various devices connected on adatabus 100 in accordance with preferred embodiments of thepresent invention. As illustrated,process control instrument 100 includes first microprocessor 200 andsecond microprocessor 202. Whileprocess controlinstrument 100 is illustrated as having twomicroprocessors, it can in other embodiments have moreor less than two microprocessors. Microprocessors 200and 202 are preferably Motorola or compatiblemicroprocessors or controllers of the type available inthe commercial market which are designed or adapted foruse with the standard SPI protocol. Typically, one ofmicroprocessors 200 and 202 act as the system masternode. The other typically acts as a peripheral deviceor slave node.
• Process control instrument 100 also includesone or more of slave nodes orperipheral devices 204,206, 208, 210 and 212. The slave nodes ofprocesscontrol instrument 100 are typically peripheralintegrated chips or devices which perform a variety offunctions related to, or necessary for, controlling ormonitoring the process. For instance,peripheral device204 is a communications link or circuitry for receivingand/or transmitting information and instructions overtwo-wireprocess control loop 106. Further, while thedevices ofprocess control instrument 100 can receivepower from adedicated power supply 214, in someembodiments the nodes ofprocess control instrument 100receive power over two-wire loop 106 throughcommunication link 204.
• Peripheral device 206 can include anintegrated chip memory device for storing programminginstructions for use by the master or slave nodes, orfor storing information indicative of the processconditions.Peripheral device 208 can include ananalog-to-digital (A/D) converter for convertinginformation transferred between a device such as sensor 216 and other master or slave nodes.Peripheral device210 can include a digital-to-analog (D/A) converter forconverting digital information or instructions so thatthey can be used by an analog device such as a valvepositioner (controller) 218 which controls the positionof valve 108 (Figure 1) to control the process. Sensor216 may sense any system or process variable andpositioner 218 may be any type of remote device used tocontrol the process, for example.Peripheral device 212can be a display device, such as a CRT, LED or LCD, forproviding graphical or other visual representations ofprocess related information.
• Each of the slave nodes inprocess controlinstrument 100 preferably includes an interrupt out(INT) pin or connection for generating an interruptsignal, a CS pin or connection for receiving a CSsignal, a shift clock (SCK) pin or connection forreceiving a synchronous clock signal, a master-out-slave-in(MOSI) pin or connection for receiving seriallytransmitted data from the master node, a bi-directionalmaster-in-slave-out (MISO) pin or connection forserially transmitting and receiving data, and a slaveinterrupt input (SLINT) pin or connection for receivinginterrupt signals. The bi-directional MISO connectionon each slave node is preferably adapted for seriallytransmitting data from the slave node to a master nodeor to other slave nodes, and for receiving datatransmitted from the MISO connection of other slavenodes. In embodiments of the present invention in whichprocess control instrument 100 does not include a masternode or microprocessor, the MOSI connection on the slavenodes can be eliminated.
• The master node ofprocess control instrument100 preferably includes an interrupt SLINT input or connection for receiving interrupt signals, a CS outputcorresponding to the CS inputs of the slave nodes forgenerating CS signals, an SCK output corresponding tothe SCK input of the slave nodes for generating SCKsignals, a MOSI output for transmitting serial data tothe MOSI inputs of the slave nodes, and a MISO input forreceiving data transmitted from the MISO outputconnections of the slave node. Optionally,microprocessor 202 (or 200) may include an INT output sothat it may operate as a slave node. As shown in Figure2, microprocessor 200 is configured as the master node.Therefore, microprocessor 202 does not have CS, MOSI andSCK connections in some preferred embodiments andmicroprocessor 202 is configured in a monitor mode.
• Process control instrument 100 furtherincludesdata bus 220 coupled between the various masterand slave nodes for facilitating communication betweenthe nodes. As such,data bus 220 includes an INT linecoupled to the SLINT connections of each ofmicroprocessors 200 and 202 and to the INT connection oflowestpriority slave node 204. The INT and SLINTconnections of the remaining slave nodes are daisychained from the INT output connection of one slave nodeto the SLINT input connection of the next slave node.The last slave node (i.e.slave node 212 as illustrated)has its SLINT input always tied low or inactive and isthe highest priority slave node. The INT output of aslave node is active if that node is generating aninterrupt or if its SLINT input is active whichindicates that a higher priority slave node isgenerating an interrupt. This technique alleviates theneed for any additional circuits as interconnections forarbitrating interrupts from multiple slave devices.
• Data bus 220 also includes a single CS linecoupled to the CS output of master node microprocessor200 and to the CS inputs of each of the slave nodes.The CS signal on the CS data bus line is generated byone of the master nodes and indicates that the data busis active. It can be used as a delimiter betweenmessages or to indicate which data bus is active if themaster node is controlling multiple data buses.Alternatively, it can be permanently tied active or canbe eliminated.
• Data bus 220 further includes an SCK linecoupled to the SCK output of the master node and to theSCK input of each of the slave nodes for transmittingsynchronous clock signals between the master and slavenodes. Because of the addressing and other advantagesof the data bus protocol of the present inventiondiscussed below, a single CS data bus line can be used,or the CS line can be eliminated altogether. Thus, PCBspace can be reduced.
• Data bus 220 also includes a MOSI line coupledto the MOSI output connection of the mastermicroprocessor and to MOSI input connections of each ofthe slave nodes for carrying serial data from themicroprocessor to the slave nodes. Ifprocess controlinstrument 100 does not include a master node ormicroprocessor and requires only peer-to-peercommunications (i.e., communications between slavenodes), the MOSI line ofdata bus 220 is not required.
• Finally,data bus 220 includes a bi-directionalMISO line coupled to the MISO input/outputconnections of each of the slave nodes and to the MISOinputs of each of the microprocessors for carryingserial data from the slave nodes to the microprocessorsand/or for carrying serial data between slave nodes. Note that because the MISO connection on each of theslave nodes is bi-directional, the slave node MISOconnections are preferably tri-state devices. In otherwords, the MISO connections on the slave nodes are inthe high impedance state except when a single node hascontrol of the MISO data bus line.
• Initially, the slave node with highestinterrupt priority has control of the MISO data busline. The highest priority node that is generating aninterrupt and that has an inactive SLINT input hasinterrupt priority. In Figure 2,slave node 212 willinitially control the MISO data bus line if it isgenerating an interrupt at its INT output.Slave node210 will initially control the MISO data bus line if itis generating an interrupt at its INT output, and ifslave node 212 is not. In general, a slave nodeinitially controls the MISO data bus line if it isgenerating an interrupt, and if all previous nodes inthe interrupt daisy chain are not generating aninterrupt. Also, control of the MISO data bus line canchange as a result of the instruction transmitted on thebus. By making the MISO data bus line bi-directional inthe present invention, instead of uni-directional as isthe case with standard SPI protocol data busconfigurations, peer-to-peer communications between theperipheral devices is possible without increasing thenumber of data bus lines or physical connections. Theabove described arbitration method also aids infacilitating bi-directional communications.
• If the process control instrument includes amaster node, data bus control is typically performed bythe master node. If the process control instrument onlyincludes peripheral devices (i.e., slave or peer nodes),the data bus control function can be provided by one of the slave nodes or it can be shared by multiple slavenodes. For example, the slave node with interruptpriority at the beginning of a message can assume thedata bus control responsibilities for the message.
• Figure 3 is a timing diagram illustrating amessage format or protocol used in preferred embodimentsof the process control instruments of the presentinvention. With an interrupt signal (INT) originated byone of the slave nodes (and propagated through theinterrupt daisy chain and onto the INT data bus line)and with the CS line held active by a master node,messages on the MOSI or MISO data bus lines aretransmitted one bit per each cycle of the SCK signal.As can be seen in the timing diagram of Figure 3, thefirst byte of a message on either the MOSI or the MISOdata lines is the INSTRUCTION. The second byte isoptionally one or more extendable address bytes EXTADRindicative of which node the message is intended for.Potentially, multiple extended address bytes can followthe first extended address byte if needed. These bytesare followed by zero or more data bytes. If one or moreaddress byte extensions are used,bit 5 of theINSTRUCTION byte will be set tologic level 1. If theaddress is fully contained in the INSTRUCTION byte,bit5 will be set to 0 and DATA bytes will follow theINSTRUCTION byte. There is no byte count, because themessage length is inherent in the INSTRUCTION BYTE.
• The structure of the INSTRUCTION byte of theMOSI or MISO messages illustrated in Figure 3 is shownin greater detail in Figure 4.Bits 6 and 7 areindicative of the command, with a 00 representing abroadcast BRCST command, a 01 representing a statuscondition STCND command, a 10 representing a READcommand and a 11 representing a WRITE command. The READ command is a request for the contents of an object inanother node, and the WRITE command is a request tochange the contents of an object in another node. Thebroadcast command transmits the value of an object toall nodes and is initiated by the device containing theobject. The status command transmits the statuscondition of a node to all other nodes.
• The address extension AE bit (bit 5), if setto a logical 1 value, indicates one or more extendedaddress bytes EXTADR will follow the INSTRUCTION byte 'before any DATA bytes are transmitted in a message. Ifthe AE bit is set to a logical 1, indicating the nextbyte is an address,bit 7 of the extended address byteindicates whether yet another extended address bytefollows. Ifbit 7 of the extended address byte is setto a logical 1, then the next byte of the transmittedmessage will also be an extended address byte. Ifbit7 of the extended address byte is set to a logical 0,the next byte of the message will be a DATA byte. Inthis manner, address lengths of any number of bytes canbe used without modifying the data bus, the componentsor the programming. This feature of the presentinvention increases the ease in which nodes can be addedor interchanged. Bits 0-4 of the INSTRUCTION byte arethe node/object address. Theinstruction 00 hex (8zeros) is reserved and is defined as an interruptacknowledge or a no operation indicator.
• Various embodiments of the present inventioninclude one of three address assignment mechanisms forassigning addresses to the nodes for subsequentcommunication on the data bus. The three addressassignment mechanisms are referred to in thisapplication as static address assignment, master dynamicaddress assignment and automatic peer address assignment, respectively. Any of the address assignmentmethods can be used, and slave nodes using any of thethree methods can be mixed on the data bus. However, inall cases the nodes must either know in advance theaddress assignments, or each node must broadcast itsaddress at start-up. It may be desirable for each ofthe nodes in the process control instrument to transmitits respective address, whether static or dynamic innature, along with an identifier indicating what type ofnode it is, to all of the other nodes in the processcontrol instrument at start-up.
• In the static address assignment method, eachnode has an external hard-wired address. INSTRUCTIONbytes containing the address corresponding to aparticular node result in the node receiving thecorresponding message. A node can have multipleindependently addressable objects. If more than fivebits are required to address all of the objects andnodes, extended address bytes can be used as discussedabove. The address and extended address states can bedivided between the node addresses and object addressesas required.
• Both of the master dynamic and automatic peeraddress assignment mechanisms are dynamic in nature,which provides an advantage in that the process controlinstrument nodes can be upgraded and interchangedwithout physically reassigning addresses or changing thesystem software. In the master dynamic addressassignment method, at reset all slave nodes/objects onthe bus are initialized at address zero, and all slavenodes generate an interrupt. A master node ormicroprocessor will then assign a non-zero address toeach node/object in order from the highest prioritynode/object to the lowest priority node/object. Generally, the master node will generate the non-zeroaddresses and transmit the respective addresses over thedata bus to the assigned nodes. For example, theinitial interrupt acknowledge from the master node canhave the address, included in a data field of themessage, which is assigned to the node with the highestpriority. As each node/object is assigned an address,it removes its interrupt request. This must be donebefore any other operations are carried out on the databus. This feature provides easy interchangeability ofvarious modules of the field instrument such as theaddition or replacement of a sensor module.
• In the automatic peer address assignmentmethod, the slave node which initially has interruptauthority assigns itself the first address. The nodewith the highest interrupt priority which has assigneditself the first address then uses a broadcast BRCSTcommand in the message INSTRUCTION byte to notify all ofthe other nodes that the first address has beenassigned. The next node without an address, and withthe next highest interrupt priority, then assigns itselfthe second address. Subsequently, it broadcasts amessage which notifies all other nodes that the secondaddress has been assigned. In general, the node withthe highest interrupt priority and without an addressassigns itself the next sequential address, and thenhroadcasts to the other nodes the fact that the newaddress has been assigned. As stored inslave node 206or in other memory, a record of the last used addresscan be initialized to zero at start-up.
• In preferred embodiments of the processcontrol instrument of the present invention, any nodecan read a message from or write a message to any object(i.e. memory location, peripheral, etc.) of any node by issuing a READ or WRITE command message within theobjects address indicated in the INSTRUCTION byte andany extended address bytes. Also, any node can indicatethat a status condition exists by issuing a STCNDcommand, with the address field of the INSTRUCTION byteindicating the object with the status condition and,optionally, with a data byte of the message containingthe object value. Status conditions can include dataready, data overflow, data buffer empty, or hardware andsoftware faults. A node can also broadcast the value ofan object with a message having a BRCST command andobject address in the INSTRUCTION byte, followed by theobject value in a data byte of the message.
• A master node or microprocessor sends commandsto the slave nodes using the MOSI line of the data busSlave nodes send commands to both master and other slavenodes on the bi-directional MISO line of the data bus.Thus, slave nodes can receive commands and informationon both the MOSI and the MISO lines of the data bus.The MISO line of the data bus will be pulled low by anactive pull down by any one of the slave nodes. If aslave node needs to initiate communications on the databus, it generates an interrupt on its INT pin orconnection. If none of the slave nodes are generatingan interrupt, all of the MISO output connections of theslave nodes will be in the high impedance state,indicating no messages are being sent from the slavenodes.
• The master node can transmit on the data busunder at least two conditions. First, the master nodecan transmit messages on the data bus in response to aninterrupt signal from a slave node. Second, the masternode can transmit messages at its own discretion. Whena slave node generates an interrupt, the master node will issue a command on the MOSI line of the data bus inresponse. As the master node is transmitting theresponse message on the MOSI line of the data bus, thehighest priority interrupting slave node can transmitits message on the MISO line of the data bus. If themaster node's response message contains an interruptacknowledge, the interrupting node can continue totransmit its message on the MISO line of data bus. Ifthe master node's response message on the MOSI line ofthe data bus is a command other than an interruptacknowledge, the message from the slave node is aborteduntil the next message sequence.
• In embodiments of the present invention inwhich the process control instrument does not include amaster node, the MOSI data bus line can be eliminated ortied inactive (i.e., tied to a low logic level state),and all messages will treated as if they contain aninterrupt acknowledge. In this case, the SCK signalmust be generated by a device or node other than amaster node. Further, if required at all, the CS signalon the CS data bus line would also have to be generatedby another device if no master node is present.
• The present invention provides numerous otheradvantages over process control instruments havingmaster nodes operating in accordance with the standardSPI protocol and using a standard data busconfiguration. One advantageous feature of somepreferred embodiments of the present invention is thatslave nodes can receive messages on the MISO data busline from peer slave nodes. The physical layercommunications are transformed into a communicationsdata bus scheme capable of master and/or slave nodebroadcast type communications, master-to-slave typecommunications slave-to-master type communications, and peer-to-peer slave node communications. Using themodified data bus features and physical connections,master nodes using the standard SPI protocol can addressmultiple slave nodes with a single CS data bus line. Ifall nodes on the data bus use this modified protocol,the CS line can be considered always active andtherefore can be fully eliminated.
• The present invention also includes anarbitration technique which uses physical interconnectand/or instruction interpretation to determine which ofmultiple slave nodes has priority and thus control ofthe data bus. Further, the dynamic addressingtechniques used in the improved process controlinstrument of the present invention allow the nodes tobe easily interchanged or substituted and allows thesoftware to be more independent of the hardwareconfiguration. Also, the bi-directional MISO data busline of the present invention provides peer-to-peercommunications between slave nodes. In process controlinstruments which use peer-to-peer communicationsexclusively, the MOSI data bus line can be eliminatedall together. Other benefits of the enhanced SPIprotocol and data bus configuration of the presentinvention include reduced integrated chip pin counts andPCB interconnections which lead to a reduction in costand physical size, the ability to use existingmicroprocessors which operate on standard SPI protocoland the fact that microprocessor loading can be reducedvia the availability of broadcast and peer-to-peercommunications capabilities so that communicationbetween slave nodes does not have to be routed throughthe microprocessor.
• Although the present invention has beendescribed with reference to preferred embodiments, workers skilled in the art will recognize that changesmay be made in form and detail without departing fromthe spirit and scope of the invention. It will beunderstood that the present invention may be implementedin any type of process control instrument. Further,various functional blocks may be implemented using anyappropriate hardware, software, or firmware technique ortheir combination. Other minor design changes are alsopossible. For example, in embodiments in whichmicroprocessor 200 acts as the master node,communication by a second microprocessor (i.e.,microprocessor 202) can be implemented in several ways.The additional microprocessor can be treated as aperipheral device, in which case it would include a INToutput and-would be daisy chained with the other slavenodes. Then, the additional microprocessor wouldcommunicate over the bi-directional MISO line. In thealternative, tri-state drivers can be added to the MOSIoutput of each microprocessor and all microprocessorscan transmit over the MOSI line.

Claims (4)

1. A process control instrument (100), comprising:

   a first slave node (204, 206);

   a second slave node (206, 204); and

   a master node (200), wherein the master node is coupled to the first and second slave

   nodes by a data bus (220), wherein the master node comprises:

   an interrupt detection circuit for detecting a first interrupt generated by one of thefirst and second slave nodes on the data bus;

   an address generating circuit for generating a first address in response to the firstinterrupt generated by the one of the first and second slave nodes; and

   an address transmitting circuit for transmitting over the data bus the first addressto the one of the first and second slave nodes which generated the first interrupt

   and thereby assigning the first address to the one of the first and second slavenodes which generated the first interrupt.
2. The process control instrument of claim 1, wherein the master node (200) furthercomprises:

   an interrupt detection circuit for detecting a second interrupt generated by theother of the first and second slave nodes (204, 206) on the data bus;

   an address generating circuit for generating a second address in response to thesecond interrupt generated by the other of the first and second slave nodes; and

   an address transmitting circuit for transmitting over the data bus the secondaddress to the other of the first and second slave nodes which generated thesecond interrupt and thereby assigning the second address to the other of the firstand second slave nodes which generated the second interrupt.
3. The process control instrument of claim 1 or 2, wherein the data bus (220) includes asingle chip select line (CS) coupled to chip select connections on each of the masternode (200), the first slave node (204, 206) and the second slave node (206, 204).
4. The process control instrument of claim 1 or 2, wherein the data bus (220) includes a bi-directionalMaster-In-Slave-Out (MISO) line coupled to MISO connections on each ofthe master node (200), the first slave node (204, 206) and the second slave node (206,204), and wherein the MISO line is adapted to carry serial data both from the first andsecond slave nodes to the master node, and between the first and second slave nodes.

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