EP0933820B1 - Semiconductor element and semiconductor memory device using the same - Google Patents

Description

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductorelement suited for integration with a highdensity and a semiconductor memory device implemented byusing the same.

Heretofore, polycrystalline silicon transistorshave been used as elements for constituting astatic random access memory device (referred to as SRAMin abbreviation). One of the relevant prior arttechniques is described in T. Yamanaka et al: IEEEInternational Electron Device Meeting, pp. 477-480(1990). By making the most of polycrystalline silicontransistors, integration density of the integratedcircuit can be enhanced, the reason for which can beexplained by the fact that the polycrystalline silicontransistor can be formed in stack or lamination atop aconventional bulk MOSFET (Metal-Oxide SemiconductorField Effect Transistor) formed on a surface of asemiconductor substrate with an insulation film beinginterposed between the polycrystalline silicon transistorand the bulk MOSFET. In the SRAM, implementationof a memory cell for one bit requires four bulk MOSFETsand two polycrystalline silicon transistors. However,because the polycrystalline silicon transistors can bestacked atop the bulk MOSFETs, a single memory cell of the SRAM can be implemented with an area which substantiallycorresponds to that required for the bulkMOSFETs.

As another preceding technique related to theinvention, there may be mentioned a single-electronmemory described in K. Nakazato et al: ElectronicsLetters, Vol. 29, No. 4, pp. 384-385 (1993). It isreported that a memory could have been realized bycontrolling electron on a one-by-one basis. It ishowever noted that the operation temperature is as verylow as on the order of 30 mK.

As a further prior art technique related tothe invention, there may be mentioned one which isdirected to the study of RTN (Random Telegraph Noise) ofMOSFET, as is disclosed in F. Fang et al: 1990 Symposiumon VLSI Technology, pp. 37-38 (1990). More specifically,when a drain current of a MOSFET is measured for apredetermined time under the constant-voltage condition,there makes appearance such phenomenon that statetransition takes place at random between a high-currentstate and a low-current state. This phenomenon isreferred to as the RTN, a cause for which can beexplained by the capture or entrapping of a singleelectron in a level node existing at an interfacebetween silicon (Si) and silicon oxide (SiO₂) and therelease therefrom, whereby the drain current undergoesvariations. However, the RTN remains only as a subjectfor a fundamental study concerning the current noise in the MOSFET, and any attempt or approach for positivelymaking use of the RTN in practical applications has notbeen reported yet at all.

At present, the technology for processing asemiconductor integrated circuit with high fineness hasdeveloped up to such a level where any attempt forrealization of higher fineness will encounter difficulty.Even if it is possible technologically, therewill then arise a problem that intolerably high cost isinvolved due to the necessity for much sophisticatedtechnique. Under the circumstances, a great demandexists for a fundamentally novel method of enhancing theintegration density in the fabrication of semiconductorintegrated circuits instead of relying on a method ofimplementing the semiconductor elements constituting thesemiconductor integrated circuit simply by increasingthe fineness thereof.

On the other hand, the polycrystalline silicontransistor known heretofore is basically equivalent to avariable resistor element in the respect that resistancebetween a source and a drain of the polycrystallinesilicon transistor can be controlled by a gate voltage.Consequently, implementation of a memory cell of a SRAMrequires as many as six semiconductor elements inclusiveof the conventional MOSFETs formed in a siliconsubstrate.

By contrast, in the case of a DRAM (DynamicRandom Access Memory), information or data of one bit can be stored in a memory cell constituted by one MOSFETand one capacitor. For this reason, the DRAM enjoysreputation as a RAM device susceptible to implementationwith the highest integration density. However, becausethe DRAM is based on such a scheme that electric chargeis read out onto a data wire of which capacitance isnon-negligible, the memory cell thereof is required tohave capacitance on the order of several ten fF (femto-Farads),which thus provides a great obstacle to anattempt for further increasing fineness in implementationof the memory cells.

By the way, it is also known that a nonvolatilememory device such as a flash EEPROM (ElectricallyErasable and Programmable Read-Only Memory) can berealized by employing MOSFETs each having a floatinggate and a control gate. Further, as a semiconductorelement for such a nonvolatile memory device, there isknown MNOS (Metal Nitride Oxide Semiconductor) element.The MNOS is designed to store charge at interfacebetween a SiO₂-film and a Si₃N₄-film instead of thefloating gate of the flash EEPROM. Although the use ofthe MOSFET equipped with the floating gate or the MNOSelement is certainly advantageous in that one-bit datacan be held or stored by one transistor over an extendedtime span, a lot of time is required for the rewritingoperation because a current to this end has to flowthrough the insulation film, whereby the number of timesthe rewriting operation can be performed is limited to about 100 millions, which in turn gives rise to aproblem that limitation is imposed to the applicationswhich the nonvolatile memory device can find.

On the other hand, the one-electron memorydevice discussed in the Nakazato et al's articlementioned hereinbefore can operate only at a temperatureof cryogenic level, presenting thus a problem which isvery difficult to cope with in practice. Besides, acell of the single-electron memory is comprised of onecapacitor and two active elements, which means that anumber of the elements as required exceeds that of theconventional DRAM, to a further disadvantage.

As will be appreciated from the forgoing,there exists a great demand for a semiconductor elementwhich requires no capacitance elements, differing fromthat for the DRAM and which can exhibit stored functionby itself in order to implement a memory of higherintegration density than the conventional one withoutresorting to the technique for implementing the memorywith higher fineness.

The basic principle of a non-volatile memory device isdisclosed in the German Patent Applications DE 21 52 225 andDE 21 49 303. Both documents disclose that the hysteresiseffect is increasable by storing an increased number of carriers.

The patent application of Japan No. 59074680 and the USpatent application No. 5357134 relate to improvements of thecharge trap.

SUMMARY OF THE INVENTION

In the light of the state of the art describedabove, it is an object of the present invention toprovide an epoch-making semiconductor element whichallows a semiconductor memory device to be implementedwith a lesser number of semiconductor elements and asmaller area and which per se has data or information storing capability while requiring no cooling at a lowtemperature such as cryogenic level.

Another object of the present invention is toprovide a semiconductor memory device which can beimplemented by using the semiconductor elementsmentioned above.

A further object of the invention is toprovide a data processing apparatus which includes as astorage the semiconductor memory device mentioned above.

For achieving the above and other objectswhich will become apparent as description proceeds, itis taught according to a basic technical concept underlyingthe invention that capacitance between a gate anda channel of a semiconductor field-effect transistorelement is set so small that capture of a single carrier(electron or hole) by a trap level can definitely anddiscriminately detected as a change in the current ofthe semiconductor field-effect transistor element. Morespecifically, correspondences are established betweenchanges in a threshold value of the semiconductor field-effecttransistor element as brought about by capture ofa carrier in the trap and releasing therefrom anddigital values of logic "1" and "0", to thereby impartto the semiconductor field-effect transistor element afunction or capability for storing data or informationeven at a room temperature.

Thus, according to a first embodiment of thepresent invention in its most general sense thereof, there is provided a semiconductor element which includesa source region constituting a source of the semiconductorelement, a drain region constituting a drain ofthe semiconductor element, an effective channel regionprovided between the source region and the drain regionfor interconnection thereof, a gate electrode connectedto the channel region through a gate insulation filminterposed between the gate electrode and the channelregion, and a level node formed between the sourceregion and the drain region in the vicinity of a currentpath in the channel region for capturing at least onecarrier, wherein effective capacitance (which will beelucidated later on) between the gate electrode and theeffective channel region is set so small as to satisfy acondition given by the following inequality expression:1/Cgc > kT/q2where C_gc represents the effective capacitance,k representsBoltzmann's constant, T represents an operatingtemperature in degree Kelvin, andq represents charge ofan electron (refer to Figs. 1A - 1D).

According to another embodiment of the presentinvention, there is provided a semiconductor elementwhich includes a source region and a drain regionconnected to the source region through a channel regioninterposed therebetween, a gate electrode connected tothe channel region through a gate insulation film interposed between the gate electrode and the channelregion, at least one carrier confinement region formedin the vicinity of the channel region for confining acarrier, and a potential barrier existing between thecarrier confinement region and the channel region,wherein effective capacitance between the gate electrodeand the effective channel region is set so small as tosatisfy a condition given by the following inequalityexpression:1/Cgc > kT/q2where C_gc represents the effective capacitance,k representsBoltzmann's constant, T represents an operatingtemperature in degree Kelvin, andq represents charge ofan electron (refer to Figs. 10A, 10B).

According to yet another embodiment of the presentinvention, there is provided a semiconductor elementwhich includes a source region constituting a source ofthe semiconductor element, a drain region constituting adrain of the semiconductor element, the source regionbeing connected to the drain region through a channelregion interposed therebetween, a gate electrode connectedto the channel region through a gate insulationfilm interposed between the gate electrode and thechannel region, at least one carrier confinement regionformed in the vicinity of the channel region for confininga carrier, and a potential barrier existing between the carrier confinement region and the channel region,wherein a value of capacitance between the channelregion and the carrier confinement region is set greaterthan capacitance between the gate electrode and the carrierconfinement region, and wherein total capacitanceexisting around the carrier confinement region is so setas to satisfy a condition given by the followinginequality expression:q2/2Ctt > kTwhere C_tt represents the total capacitance,k representsBoltzmann's constant, T represents an operating temperaturein degree Kelvin, andq represents charge of anelectron (refer to Figs. 10A, 10B).

At this juncture, it is important to note thatwith the phrase "total capacitance (C_tt) means a totalsum of capacitances existing between the carrier confinementregion and all the other electrodes than thegate electrode.

In order to increase the number of times thesemiconductor memory element can be rewritten, it isrequired to suppress to a possible minimum degradationof a barrier (insulation film) existing between thechannel region and the carrier confinement region.

In view of the above, there is providedaccording to a further aspect of the invention asemiconductor element which includes a source region constituting a source of the semiconductor element, adrain region constituting a drain of the semiconductorelement, the source region being connected to the drainregion through a channel region interposed therebetween,a gate electrode connected to the channel region througha gate insulation film interposed between the gateelectrode and the channel region, at least one carrierconfinement region formed in the vicinity of the channelregion for confining a carrier, the confinement regionbeing surrounded by a potential barrier, storage ofinformation being effectuated by holding a carrier inthe carrier confinement region, and a thin film structurehaving a thickness not greater than 9 nm and formedof a semiconductor material in an insulation filmintervening between the channel region and the carrierconfinement region (refer to Figs. 17A, 17B).

For better understanding of the present invention,the underlying principle or concept thereof willhave to be elucidated in some detail.

In a typical mode for carrying out theinvention, a polycrystalline silicon element (see e.g.Figs. 1A - 1D) is imparted with such characteristic thatwhen potential difference between the gate and thesource thereof is increased and decreased repetitivelywithin a predetermined range with a drain-source voltagebeing held constant, conductance between the source andthe drain exhibits a hysteresis even at a roomtemperature (see Fig. 2).

More specifically, referring to Fig. 2 of theaccompanying drawings, when the gate-source voltage isswept vertically between a first voltage v_g0 (0 volt) anda second voltage V_g1 (50 volts), the drain current of thepolycrystalline silicon element exhibits hysteresischaracteristic. This phenomenon has not heretofore beenknown at all but discovered experimentally first by theinventors of the present application. The reason whysuch hysteresis characteristic can make appearance willbe explained below.

Fig. 4A shows a band profile in a channelregion of a semiconductor device shown in Figs. 1A - 1Din the state where the gate-source voltage V_gs is zerovolt. A drain current flows in the direction perpendicularto the plane of the drawing. For convenience ofdiscussion, it is assumed in the following descriptionthat the drain-source voltage is sufficiently low whencompared with the gate voltage, being however understoodthat the observation mentioned below applies equallyvalid even in the case where the drain-source voltage ishigh.

Now referring to Fig. 4A, there is formed in achannel (3) of polycrystalline silicon a potential wellof low energy between a gate oxide film (5) and a peripheralSiO₂-protection film (10). In this case, energylevel (11) of a conduction band in the channel region(3) which may be of p-type or of i-type (intrinsicsemiconductor type) or n-type with a low impurity concentration is sufficiently high when compared withenergy level of a conduction band in a n-type sourceregion of a high impurity concentration or Fermi level(12) in a degenerate n-type source region of a highimpurity concentration. As a consequence, there existno electrons within the channel (3). Thus, no draincurrent can flow.

Further, a trap level (7) exists in thevicinity of the channel (3), which can capture or trapcarriers such as electrons. As levels which partake informing the trap level, there are conceivable a levelextending to a grain or a level of group of grains(crystal grains in the channel regions of polycrystallinesilicon) themselves which are surrounded by a highbarrier, level internally of the grain, level at aSi-SiO₂ interface (i.e., interface between the channelregion (3) and the gate oxide film (5)), level insidethe gate oxide film (5) and others. However, it is ofno concern which of these levels forms the trap level.Parenthetically, even after the experiments conducted bythe inverters, it can not be ascertained at present bywhich of the aforementioned levels the carriers orelectrons are trapped in actuality. Of the levelsmentioned above, energy in the trap level (7) whichplays a role in realizing the hysteresis characteristicmentioned above is sufficiently higher than the Fermilevel (12) in the source region (1). Accordingly, noelectrons exist in the trap level (7). At this juncture, it should be added that although the traplevel is shown in Figs. 4A - 4C as existing within thegate oxide film, the trap level need not existinternally of the oxide film. It is only necessary thatthe trap level exists in the vicinity of the channel.

As the potential difference V_gs between thegate (4) and the source (1) is increased from zero voltto the low threshold voltage V_ℓ, potential in the channelregion (3) increases. Consequently, as comparedwith the initial energy level of the channel region (3)in the state where the potential difference V_gs is zero(refer to Fig. 4A), the potential of the channel region(3) for electrons becomes lower under the condition thatthe potential difference V_gs is higher than zero volt andlower than the low threshold voltage V_ℓ. When the gate-sourcepotential difference V_gs has attained the lowthreshold voltage V_ℓ, the Fermi level in the sourceregion (1) approaches to the energy level in the conductionband of the channel region (3) (with a differenceof about kT, wherek represents Boltzmann's constant andT represents operating temperature in Kelvin). Consequently,electrons are introduced into the channel region(3) from the source. Thus, a current flow takes placebetween the drain and the source.

When the gate voltage is further increased,the number of electrons within the channel region (3)increases correspondingly. However, when the potentialdifference V_gs has reached a capture voltage V_g1, energy of the trap level (7) approaches to the Fermi level(12), whereby at least one electron is entrapped orcaptured by the trap level (7) because of distributionof electrons under the influence of thermal energy ofthose electrons which are introduced from the sourceregion (1). At that time, since the level of the trap(7) is sufficiently lower than potentials of the gateoxide (5) and peripheral SiO₂-protection film (10), theelectron captured by the trap level (7) is inhibitedfrom migration to the gate oxide film (5) and theperipheral SiO₂-protection film due to thermal energy ofelectron. Besides, because a grain boundary of highenergy of the polycrystalline silicon channel region (3)exists in the vicinity of the trap level (7), for example,at the Si-SiO₂ interface, the electron captured bythe trap level (7) can not move from the trap level(refer to Fig. 4C). However, since the other electronscan move, the drain current continues to flow.

In this way, once a single electron is entrappedor captured by the trap level (7), the thresholdvoltage of the polycrystalline silicon semiconductorelement shown in Figs. 1A - 1D changes from the lowthreshold voltage V_ℓ to the high threshold voltage V_h,the reason for which will be explained below.

When the gate-source potential difference V_gsis lowered from the state shown in Fig. 4C within therange of V_h < V_gs < V_g1, the number of electrons withinthe channel region (3) is decreased. However, in general, a high energy region exists in the periphery ofthe trap level (7). Accordingly, the electron capturedby the trap level (7) remains as it is (refer toFig. 5A).

When the gate voltage is further lowered to avalue at which the potential difference V_gs attains thehigh threshold voltage V_h, the Fermi level (12) of thesource region (1) becomes different from the energylevel of the conduction band of the channel (3) byca. kT, as a result of which substantially all of theelectrons within the channel disappear (see Fig. 5B).Consequently, the drain current can flow no more.However, the threshold voltage V_h at which no draincurrent flow becomes higher than the low thresholdvoltage V_ℓ by a voltage corresponding to the charge ofelectron captured in the trap level (7).

Further, by lowering the gate-source potentialdifference V_gs to a value where the potential differenceV_gs becomes equal to zero, potential in the peripheralhigh-energy region of the trap level (7) becomes lowerin accompanying the lowering of the gate voltage, whichresults in that the electron captured by the trap level(7) is released to the region of low energy throughtunneling under the effect of the electric field (referto Fig. 5C).

Subsequently, the gate-source potential differenceV_gs is again increased for the vertical sweeping.By repeating this operation, hysteresis can be observed in the drain current-versus-gate voltage characteristicowing to trapping and release of the electron.

In this conjunction, the inventors havediscovered that the hysteresis characteristic mentionedabove appears only when the capacitance between the gateand the channel is small. Incidentally, the experimentconducted by the inventors shows that although a semiconductorelement having a gate length and a gate widtheach of 0.1 micron can exhibit the aforementionedhysteresis characteristic, a semiconductor element whosegate length and gate width are on the order of 1 (one)micron is incapable of exhibiting such hysteresischaracteristic.

Thus, it must be emphasized that smallness ofthe capacitance C_gc between the gate electrode and thechannel region is indispensable for the aforementionedhysteresis characteristic to make appearance, the reasonfor which may be explained as follows. There existsbetween an amount of charge Q_s stored in the trap leveland a change ΔV_t (= V_h - V_ℓ) in the threshold value orvoltage the following relation:ΔVt = Qs/Cgcwhere C_gc represents capacitance between the gate and aneffective channel. With the phrase "effective channel",it is intended to mean a region of the channel whichrestrictively regulates magnitude of a current flowing therethrough and which corresponds to a region ofhighest potential energy in the current path. Thus,this region may also be termed a bottle-neck region. Inorder to make use of the aforementioned hysteresischaracteristic as the memory function, it is necessarythat the state in which the threshold value is high (V_h)and the state where the threshold value is low (V_ℓ) candefinitely and discriminatively be detected as a changein the drain current. In other words, differencebetween the threshold values V_h and V_ℓ has to be clearlyor definitely sensed in terms of a difference or changeappearing in the drain current. The conditions to thisend can be determined in the manner described below. Ingeneral, the drain current I_d of a MOS transistor havinga threshold value V_t can be represented in the vicinityof the threshold value by the following expression:Id = A•exp[q(Vgs - Vt)/(kT)]where A represents a proportional constant,q representscharge of an electron, V_gs represents a gate-sourcevoltage of the MOS transistor, V_t represents thethreshold voltage,k represents Boltzmann's constant andT represents an operating temperature in degree Kelvin.Thus, when V_t = V_h, the drain current is given byIdh = A•exp[q(Vgs - Vh)/(kT)] while when V_t = V_ℓ, the drain current is given byIdℓ = A•exp[q(Vgs - Vℓ)/(kT)]Thus, ratio between the drain currents in the statewhere V_t = V_h and the state V_t = V_ℓ can be determined asfollows:Idℓ/Idh = exp[q(Vh - Vℓ)/(kT)]

Thus, it can be appreciated that in order tomake it possible to discriminate the two statesmentioned above from each other on the basis of thedrain currents as sensed, it is necessary that the draincurrent ratio I_dℓ/I_dh as given by the expression (5) isnot smaller than the basee (2.7) of natural logarithmat minimum, and for the practical purpose, the currentratio of concern should preferably be greater than "10"(ten) inclusive. On the condition that the draincurrent ratio is not smaller than the basee of naturallogarithm, the following expression holds true.ΔVt(= Vh - Vℓ) > kT/qThus, from the expression (1), the following conditionhas to be satisfied.Qs/Cgc > kT/q

In order that the capture of a single electroncan meet the current sense condition mentioned above, itis then required that the following condition besatisfied.q/Cgc > kT/q

From the above expression (8), it is apparentthat in order to enable operation at a room temperature,the gate-channel capacitance C_gc should not exceed 6 aF(wherea is an abbreviation of "atto-" meaning 10^-18).Incidentally, in the case of the semiconductor elementhaving the gate length on the order of 1 micron, thegate-channel capacitance C_gc will amount to about 1 fF(wheref is an abbreviation of "femto-" meaning 10^-15)and deviate considerably from the above-mentionedcondition. By contrast, in the case of a semiconductorelement fabricated by incarnating the teaching of theinvention, the gate-channel capacitance C_gc is asextremely small as on the order of 0.01 aF, and it hasthus been ascertained that a shift in the thresholdvalue which can be sensed is brought about by thecapture of only a single even electron at a roomtemperature.

Further, in the course of the experiment, theinventors have found that by holding the gate-sourcepotential difference V_gs between zero volt and thevoltage level V_g1, the immediately preceding threshold value can be held stably over one hour or more. Fig. 3of the accompanying drawing shows the result of thisexperiment. More specifically, Fig. 3 illustrateschanges in the drain current as measured under thecondition indicated bya in Fig. 2 while holding thegate voltage to be constant. As can be seen in thefigure, in the state of low threshold value, a highcurrent level can be held, while in the state of highthreshold value, a low current level can be held. Thus,by making use of the shift of the threshold value, it ispossible to hold information or data, i.e., to storeinformation or data, to say in another way. Further, bysensing the drain current in these states, it is possibleto read out the data. Namely, the state in whichthe drain current is smaller than a reference value 13may be read out as logic "1" data, while the state inwhich the drain current is greater than the referencevalue (13) may be read out as logic "0" (refer toFig. 3).

On the other hand, data write operation can beeffectuated by controlling the gate voltage. Now,description will be directed to the data write operation.It is assumed that in the initial state, the gatevoltage is at the low level V_g0. By sweeping the gatevoltage in the positive direction to the level V_g1 thethreshold voltage at is set the high level V_h. Withthis operation, logic "1" of digital data can be writtenin the semiconductor element according to the invention. Subsequently, the gate voltage is swept in the negativedirection to the zero volt level to thereby change thethreshold voltage to the low level V,. In this way,logic "0" of digital data can be written.

As will now be understood from the foregoingdescription, it is possible to write, hold and read thedata or information only with a single semiconductorelement. This means that a memory device can beimplemented with a significantly smaller number ofsemiconductor elements per unit area when compared withthe conventional memory device.

The semiconductor element according to theinvention in which data storage is realized by capturingor entrapping only a few electrons in a storage node(which may also be referred to as the carrier confinementregion or level node or carrier trap or carrierconfinement trap, quantum confinement region or the liketerms) can enjoy an advantage that no restriction isimposed on the number of times the data can be rewrittendue to deterioration of the insulation film as encounteredin a floating-gate MOSFET or restriction, ifimposed, is relatively gentle.

It is however noted that in the case of themode illustrated in Figs. 1A - 1D for carrying out theinvention, relative positional relationship (i.e.,relative distance) between the carrier trap levelserving for the carrier confinement and the effectivechannel region serving as the current path is rather1 difficult to fix, involving non-ignorable dispersions ofthe threshold value change characteristic among theelements as fabricated.

As one of the measures for coping with thedifficulty mentioned above, there is proposed anothermode for carrying out the invention such as one illustratedin Figs. 10A and 10B of the accompanying drawingsin which the carrier confinement region (24) surroundedby a potential barrier is provided independently in thevicinity of a channel region (21). With this structure,the dispersion mentioned above can be reduced.

From the stand point of performance stabilityof the semiconductor element, it is preferred thatdispersion of the voltage difference ΔV_t between thehigh threshold voltage V_h and the low threshold voltageV_ℓ among the semiconductor elements as fabricated shouldbe suppressed to a possible minimum.

Certainly, the condition given by the expression(1) can apply valid when the capacitance C_gt betweenthe gate region and the carrier confinement region aswell as the capacitance C between the carrier confinementregion and the channel region is sufficientlysmall. In the other cases than the above, the conditiongiven by the following expression applies valid:ΔVt = q/(1 + Cgt/C)Cgcwhere C_gc represents capacitance between the gate region (22) and the channel region (21), C_gt representscapacitance between the carrier confinement region (24)and the channel (21).

In conjunction with the mode shown in Figs. 1A- 1D for carrying out the invention, the inventors havefound that the term C representing the capacitancebetween the carrier confinement region and the channelregion in the expression (9) is most susceptible to thedispersion because the carrier confinement region is soimplemented as to assume the carrier trap level. Inorder that the potential difference ΔV_t mentioned abovescarcely undergoes variation notwithstanding ofvariation in the capacitance C between the carrierconfinement region and the channel region, thecapacitance C_gt between the gate electrode and thechannel region must be sufficiently smaller than thecapacitance C (i.e., C_gt « C).

Thus, according to another preferred mode forcarrying out the invention, it is proposed to set at asmall value the capacitance C_gt between the gate electrode(22) and the carrier confinement region (24) byinterposing a gate insulation film (23) of a greatthickness while setting at a large value the capacitanceC between the carrier confinement region (24) and thechannel region (21) by interposing therebetween aninsulation film (25) of a small thickness.

On the other hand, in conjunction with theholding of data in the carrier confinement region (24), it is necessary to ensure stability against thermalfluctuations. At this juncture, let's represent by C_ttthe total capacitance existing between the carrierconfinement region and all the other regions. Ingeneral, in the absolute temperature (T) system, energyfluctuation on the order of kT (wherek representsBoltzmann's constant and T represents temperature indegree Kelvin) will be unavoidable. Accordingly, inorder to hold the data stably, it is required thatchange of energy given by q²/2C_tt as brought about bycapturing a single electron is greater than the fluctuationmentioned above. To say in another way, thecondition given by the following expression will have tobe satisfied.q2/2Ctt > kT

This condition requires that the total capacitanceC_tt defined above has to be smaller than 3 aFinclusive in order to permit operation at a room temperature.

In still another mode for carrying out theinvention as illustrated in Figs. 17A and 17B of theaccompanying drawings, a thin semiconductor filmstructure (48) is formed interiorly of an insulationfilm (49, 50) which is interposed between the storageregion (47) and the channel region (46) with a view toreducing deterioration of the insulation film (49, 50).

Thus, in the semiconductor element implementedin accordance with the instant mode for carrying out theinvention, a potential barrier provided by the thin filmstructure (48) is formed interiorly of the insulationfilm (49, 50) so that the thin film structure (48) playseffectively a same role as the insulation film, whilemaking it possible to decrease the thickness of theinsulation film in practical applications.

As can be seen in Figs. 17A and 17B, thesemiconductor thin film (48) provided internally of theinsulation film (49, 50) has an energy level shifted bythe conduction band under the effect of the quantumconfinement effect in the direction thicknesswise of thesemiconductor thin film and serves essentially as apotential barrier between the storage region and acarrier supply region for the write/erase operations,the reason of which will be elucidated below.

Representing the film thickness of the semiconductorthin film by L, effective mass of the carrierin the thin film byn and Planck's constant byh, energyin the lowest energy state in quantum fluctuation of thecarrier due to the confinement effect in the thicknesswisedirection can appropriately be given by the followingexpression:h2/8mL2

In order that the energy shift due to the quantum confinement effect is made effective inconsideration of the thermal energy fluctuation, thecondition given by the following inequality expression(12) is required to be satisfied.h2/8mL2 > kT

In the light of the above expression (12), thethickness of the semiconductor thin film (48) formed ofsilicon (Si) will have to be smaller than 9 nm inclusivein order that the barrier is effective at a roomtemperature.

Thus, although there is a probability of thecarrier existing in the semiconductor thin film for ashort time upon moving of the carriers between thechannel region (46) and the carrier confinement region(47) via the insulation film (49, 50), the probabilityof the carriers staying in the semiconductor thin film(48) for a long time is extremely low. As a result ofthis, the semiconductor thin film (48) operates as atemporary passage for the carriers upon migrationthereof between the channel region (46) and the carrierconfinement region (47), which means that the semiconductorthin film (48) will eventually serve as thepotential barrier because of incapability of the carrierconfining operation.

With the structure described above, thesemiconductor element can exhibit the barrier effect with the insulation film of a smaller thickness whencompared with the semiconductor element in which theabove structure is not adopted. Thus, film fatigue ofthe insulation film (49, 50) can be suppressed. Forfurther mitigating the film fatigue, the semiconductorthin film (48) may be formed in a multi-layer structure.

The structure in which the semiconductor thinfilm is provided in the insulation film can enjoy afurther advantage that the height of the potentialbarrier between the carrier confinement region and thesource region can properly be set. Since the energyshift due to the quantum confinement is determined inaccordance with the size L of the carrier confinementregion, it is possible to adjust the height of thebarrier by adjusting the film thickness in addition tothe selection of the thin film material. In thisconnection, it should be noted that in the semiconductorelement of the structure known heretofore, the height ofthe barrier is determined only on the basis of thematerial constituting the insulation film.

The above other objects, features andattendant advantages of the present invention will moreclearly be understood by reading the following descriptionof the preferred embodiments thereof taken, only byway of example, in conjunction with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Figs. 1A to 1D are views for illustrating a structure of a memory element according to a firstembodiment of the invention, wherein Fig. 1A is a topplan view, Fig. 1B is microphotographic view of achannel portion of the same Fig. 1C is a schematicperspective view illustrating an overall structure ofthe memory element, and Fig. 1D is a sectional view ofthe same taken along a line C-C' in Fig. 1C;

Fig. 2 is a view showing graphically measuredvalues representing a gate-source voltage dependency ofa drain current of the memory element according to thefirst embodiment of the invention;

Fig. 3 is a view showing experimentallyobtained results for illustrating holding of data by thesemiconductor element according to the first embodimentafter writing of logic "1" and "0";

Figs. 4A to 4C are views for illustratingchanges of a band profile in the vicinity of a channelregion of the semiconductor element according to thefirst embodiment of the invention when gate voltage isincreased;

Figs. 5A to 5C are views for illustratingchanges of a band profile in the vicinity of a channelregion of the semiconductor element according to thefirst embodiment of the invention when gate voltage islowered;

Fig. 6 is a schematic circuit diagram showinga structure of a memory IC device according to theinvention in which the memory elements each having the structure shown in Fig. 1 are employed;

Fig. 7 shows a hysteresis characteristicexpected to be exhibited by the memory device shown inFig. 6;

Fig. 8 is an exploded perspective view showingschematically a structure of a semiconductor memorydevice according to the first embodiment of the inventionin which a memory cell array is formed as stackedon peripheral circuits formed in a Si-substrate surface;

Figs. 9A and 9B are sectional views forillustrating fabrication steps of a semiconductor memorydevice according to the first embodiment of theinvention;

Figs. 10A and 10B are sectional views showinga structure of a semiconductor memory element accordingto a second embodiment of the invention;

Figs. 11A and 11B are enlarged views showingexaggeratedly a channel region, a carrier confinementregion and a gate electrode of the memory elementaccording to the second embodiment of the invention,wherein Fig. 11A is a perspective view and Fig. 11B is asectional view;

Fig. 12 is a view for illustrating graphicallya gate-source voltage dependency of a drain current inthe semiconductor memory element according to the secondembodiment of the invention;

Figs. 13A to 13C are schematic diagrams forillustrating exaggeratedly changes in potential distribution in the vicinity of a channel region andcarrier confinement region of a semiconductor memoryelement when a gate voltage is increased;

Figs. 14A to 14C are schematic diagrams forillustrating exaggeratedly changes in potentialdistribution in the vicinity of a channel region andcarrier confinement region of a semiconductor memoryelement when a gate voltage is lowered;

Figs. 15A and 15B are sectional views showinga structure of a semiconductor memory element accordingto a third embodiment of the invention;

Figs. 16A to 16C are views showing a structureof a semiconductor memory element according to a fourthembodiment of the invention, wherein Fig. 16A is asectional view, Fig. 16B shows a section taken along aline a-a' in Fig. 16A and Fig. 16C is a top plan view;

Figs. 17A and 17B are views for illustrating asemiconductor memory element according to a fifthembodiment of the present invention wherein Fig. 17A isa sectional view of the same and Fig. 17B shows apotential distribution profile in the memory element;

Fig. 18 is a view showing a symbol representinga semiconductor memory element according to theinvention;

Figs. 18A, 18B and 18C are views for illustratinga memory cell according to a sixth embodiment ofthe invention, wherein Fig. 18A shows a circuit configurationof the memory cell, Fig. 18B shows voltages applied to a word wire and a data wire of the memorycell upon read and write operations, respectively, andFig. 18C is a view for graphically illustratingdependency of a drain current on a gate-source voltageof a semiconductor element employed in the memory cell;

Fig. 19 is a circuit diagram showing circuitconfiguration of a read circuit for the memory cellaccording to the sixth embodiment of the invention;

Fig. 20 is a signal waveform diagram forillustrating timings at which various signals areapplied upon read operation;

Figs. 21A and 21B are diagrams showing acircuit configuration of a 4-bit memory cell arrayaccording to the sixth embodiment and a layout thereof,respectively;

Figs. 22A to 22C are views showing a memorycell set according to a seventh embodiment of theinvention, wherein Fig. 22A shows a circuit configurationof the cell set, Fig. 22B shows voltages applied toa memory element thereof upon write and read operations,and Fig. 22C graphically illustrates characteristic ofthe memory element;

Fig. 23 is a circuit diagram showing astructure of a semiconductor memory device according tothe seventh embodiment of the invention;

Figs. 24A to 24E are circuit diagrams showingvarious configurations of the memory cell according tothe invention;

Figs. 25A to 25C are views for illustrating amemory cell according to an eighth embodiment of theinvention, wherein Fig. 25A shows a circuit configurationof the memory cell, Fig. 25B shows voltages appliedto a word wire and a data wire of the memory cell uponread and write operations, respectively, and Fig. 25C isa view for graphically illustrating dependency of adrain current on a gate-source voltage of a semiconductorelement employed in the memory cell;

Fig. 26 is a circuit diagram showing circuitconfiguration of a read circuit for the memory cellaccording to the eighth embodiment of the invention;

Figs. 27A and 27B are circuit diagrams showingversions of the memory cell circuit according to theeighth embodiment, respectively;

Figs. 28A and 28B are a circuit diagramshowing a configuration of a four-bit memory cell and acorresponding mask layout of the same, respectively;

Figs. 29A to 29C are views for illustrating amemory cell according to a ninth embodiment of theinvention, wherein Fig. 29A shows a circuit configurationof the memory cell, Fig. 29B shows voltages appliedto a word wire and a data wire of the memory cell uponread and write operations, respectively, and Fig. 29C isa view for graphically illustrating dependency of adrain current on a gate-source voltage of a semiconductorelement employed in the memory cell;

Fig. 30 is a circuit diagram showing a read/write circuit according to the ninth embodiment ofthe invention;

Figs. 31A, 31B and 31C are views for illustratinga memory cell according to a tenth embodiment ofthe invention, wherein Fig. 31A shows a circuit configurationof the memory cell, Fig. 31B shows voltagesapplied to a word wire and a data wire of the memorycell upon read and write operations, respectively, andFig. 31C is a view for graphically illustratingdependency of a drain current on a gate-source voltageof a semiconductor element employed in the memory cell;

Fig. 32 is a circuit diagram showing a readcircuit according to the tenth embodiment of theinvention;

Fig. 33 is a view showing a version of amemory cell according to the tenth embodiment; and

Fig. 34 is a block diagram showing a structureof a data processing apparatus in which a memory deviceaccording to the invention be employed as a main memory.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Now, the present invention will be describedin detail in conjunction with the preferred or exemplaryembodiments thereof by reference to the drawings.

Embodiment 1

Description which follows is directed to afield effect semiconductor memory element (FET memoryelement) according to an exemplary embodiment of the present invention. Figs. 1A to 1D are views forillustrating a structure of a semiconductor memoryelement according to a first embodiment of the invention,wherein Fig. 1C is a schematic perspective viewillustrating an overall structure of the memory element,Fig. 1D is a sectional view of the same taken along theline C-C' in Fig. 1C, Fig. 1B is an enlarged microphotographicview showing a channel portion of the same, andFig. 1A is a top plan view thereof. Referring to thefigures, a source 1 and a drain 2 are each constitutedby a region formed of n-type polycrystalline silicon andhaving a high impurity concentration while a channelportion 3 is constituted by a region formed of a non-dopedpolycrystalline silicon region. Each of thesource 1, the drain 2 and the channel 3 is realized inthe form of a thin and fine wire of polycrystallinesilicon. In the case of a memory device manufacturedactually by the inventors of the present application,the channel 3 is 0.1 µm in width and 10 nm, preferably3.4 nm in thickness. Connected to the ends of thesource 1 and the drain 2 are contacts 1A and 2A of polycrystallinesilicon, respectively, each of which has athickness greater than that of the source 1 and thedrain 2, wherein the source 1 and the drain 2 areconnected to metallic wiring conductors via the polycrystallinesilicon contacts 1A and 2A, respectively.In the case of a typical example of the memory element,each of the polycrystalline silicon contacts 1A and 2A should preferably be implemented with a thickness of0.1 µm which is ten times as large as that of thechannel 3, because, if otherwise, polycrystallinesilicon itself becomes insusceptible to etching uponforming contact holes directly in thin polycrystallinesilicon. A gate electrode 4 is provided in such orientationas to intersect the channel region 3 through aninterposed gate insulation film 5. In the case of theinstant embodiment, the film thickness of the gateelectrode 4 is 0.1 µm. The structure mentioned abovecan best be seen from Fig. 1C.

Parenthetically, the polycrystalline siliconfilm constituting the channel region 3 is whollyenclosed by a SiO₂-protection film 10 in the case of theinstant embodiment (see Fig. 1D). Because the dielectricconstant of silicon oxide (SiO₂) is about one thirdof that of silicon, capacitances of the channel region 3and the gate electrode 4 can be reduced by enclosingthem with the SiO₂-protection film 10 as mentionedabove. This is one of the reasons why the hysteresischaracteristic elucidated hereinbefore can be realizedat a room temperature.

In the case of the memory element according tothe instant embodiment, the channel of polycrystallinesilicon is formed by depositing amorphous silicon (a-Si)in a thickness of 10 nm on a SiO₂-substrate and crystallizingby heat treatment at a temperature of 750°C. Inthis conjunction, it has been found that the thickness of amorphous silicon (a-Si) should preferably be in theorder of 3.5 nm. A structure of a channel portion isshown in Fig. 1B. In the course of the heat treatment,silicon crystal grains in amorphous silicon growprogressively. However, when the size of the grainreaches the film thickness, any further growth in thedirection perpendicular to the plane of the film isprevented. At the same time, the rate of the graingrowth in the direction parallel to the film becomesretarded. As a consequence, the grain size in thelateral direction (i.e., in the direction parallel tothe film surface) is substantially equal to the filmthickness. For these reasons, the field-effectsemiconductor memory element according to the instantembodiment of the invention features that the grain sizeof polycrystalline silicon forming the channel region isextremely small.

The small grain size mentioned above contributesto realization of small capacitance between thegate electrode and the channel region, the reason forwhich will be elucidated below. In the field effectelement now under consideration, it is only a fewcurrent paths 6 having lowest resistance in the channelregion 3 that a current can actually flow within a low-currentrange close to a threshold level (see Fig. 1A).To say in more concrete, the current flow takes placedue to migration or transfer of electrons from one toanother crystals grain. In the case of the instant embodiment, the current path is extremely fine or thinbecause of a very small grain size as mentioned above.Consequently, the region in which electrons exists isremarkably small when compared with whole the channelregion. For this reason, the capacitance C_gc which iseffective between the gate electrode and the effectivechannel portion (in the sense defined hereinbefore) issignificantly small.

In the case of a semiconductor memory elementactually fabricated according to the instant embodiment,the gate-channel capacitance C_gc mentioned above was setat an extremely small value, e.g. 0.02 aF (atto-Farad),with a view to observing the effect of change in thethreshold value to a possible maximum extent. As aresult of this, the range of voltages required foroperation expanded to several ten volts. Of course, bysetting the gate-channel capacitance C_gc at a greatervalue, e.g. 0.2 aF, the operation voltage range can beset to a range of several volts usually employed in theconventional integrated circuit. To this end, thethickness of the gate insulation film 5 may be decreasedand/or the length or width of the gate electrode may beincreased, which can be realized without any appreciabletechnical difficulty.

In the case of the instant embodiment of theinvention, the channel is formed of polycrystallinesilicon. At this juncture, it should however bementioned that the hysteresis characteristic can be realized even in a conventional bulk MOSFET formed in acrystal silicon substrate if the gate-channel capacitancementioned above can be made so small that theconditions mentioned previously can be satisfied. Inthat case, the bulk MOSFET can be made use of as amemory element. In this conjunction, it is howevernoted that in the case of a bulk MOSFET, the effects ofthe grain mentioned above are absent. Besides, thelower side of the bulk MOSFET is covered with a Si-filmhaving a high dielectric constant. Consequently, it isnecessary to decrease the size of the bulk MOSFET elementwhen compared with the element having the channelformed of polycrystalline silicon. This in turn meansthat difficulty will be aggravated in manufacturing thebulk MOSFET memory element. However, because the bulkMOSFET has a greater mobility of carriers, it can handlea large current and is suited for a high-speed operation,to an advantage. As a further version, thehysteresis characteristic mentioned previously can berealized by using a MOSFET of SOI (Silicon-On-Insulator)structure as well. The SOI structure can be implementedby growing monocrystalline silicon on an insulation filmand by forming a MOSFET therein. Because the gate-channelcapacitance of the SOI MOSFET can be madesmaller than that of the bulk MOSFET, the hysteresischaracteristic can be realized with a greater size whencompared With the bulk MOSFET.

The foregoing description has been made on the assumption that the channel for migration of electronsis of n-type. It should however be mentioned thatsimilar operation can be accomplished by using holes.Further, other semiconductor material than silicon canbe employed in forming the channel region.

Additionally, it has been assumed in theforegoing description that the gate electrode 4 islocated beneath the channel region 3. However, similaroperation can be effectuated equally with such structurein which the gate electrode lies above the channelregion. Besides, gate electrodes may be provided aboveand beneath the channel, respectively, for realizingsimilar operation and effects as those mentioned previously.Furthermore, the gate electrode may be disposedat a side laterally of the channel region. Moreover,gate electrodes may be provided at both sides of thechannel, respectively.

Now, referring to Fig. 6, description will bemade of an integrated memory circuit which is comprisedof the semiconductor elements of the structure describedabove. Fig. 6 shows a structure of a memory IC devicein which polycrystalline silicon memory elements eachhaving the structure shown in Fig. 1 are employed. Inthis conjunction, it is assumed that each of thesemiconductor elements or the polycrystalline siliconmemory elements has such hysteresis characteristic asillustrated in Fig. 7. More specifically, it ispresumed that when a voltage V_w is applied between the gate and the source, the memory element takes on logic"1" state (state of high threshold value represented byV_h) while upon application of a voltage of -V_w betweenthe gate and the source, the memory element assumeslogic "0" state (low threshold state V_ℓ). On the otherhand, application of a voltage in a range of -V_w/2 toV_w/2 between the gate and the source or between the gateand the drain, the threshold voltage undergoes nochange. The characteristic illustrated in Fig. 7 iscomparable to that shown in Fig. 2 except that thethreshold value is lowered as a whole and can berealized by introducing a donor impurity in the channelregion of the memory element upon manufacturing thereof.

Referring to Fig. 6, each of semiconductormemory elements MP1 to MP4 is constituted by a semiconductorelement according to the invention which has thestructure shown in Fig. 1 and the hysteresis characteristicillustrated in Fig. 7. Each of the semiconductormemory elements has a gate terminal connected to a wordwire, a drain terminal connected to a data wire and asource terminal connected to the ground potential.

Operation for writing digital data in theintegrated memory circuit is performed through cooperationof a word wire driver circuit and a data wiredriver circuit shown in Fig. 6 in a manner describedbelow. For writing logic "1" in the memory element MP1,the potential on the word wire 1 is set to a voltagelevel of V_w/2 with the potential of the data wire 1 being set to -V_w/2, while the other word wires and datawires are set to zero volt. As a result of this, avoltage of V_w is applied between the gate and the drainof the memory element MP1, which thus takes on the logic"1" state (high threshold state). At this time point,all the other memory elements than the memory elementMP1 are applied with a voltage not higher than V_w/2.Accordingly, no change takes place in the thresholdvoltage in these other memory elements. On the otherhand, for writing logic "0" in the memory element MP1,the potential on the word wire 1 is set to -V_w/2 withthe potential on the data wire 1 being set to V_w/2.Thus, the voltage of -V_w is applied between the gate andthe drain of the memory element MP1, whereby the memoryelement MP1 is set to logic "0" state (low thresholdstate V_ℓ). At this time point, all the other memoryelements than the memory element MP1 are applied with avoltage which is not higher than -V_w/2. Accordingly, nochange can take place in the threshold value in theseother memory elements.

On the other hand, reading of information ordata is carried out in a manner described below (seeFig. 6). In the data wire driver circuit, the data wireis connected to a voltage source via a load element. Onthe other hand, the other end of the data wire is connectedto a sense amplifier. Now, operations involvedin reading out data from the memory element MP1 will beconsidered. To this end, the potential of the word wire 1 as selected is set to the level of zero volt while thepotential on the other word wire 2 not selected is setto the voltage level of -V_w/2. When the memory elementMP1 is in the logic "1" state, this means that thememory element MP1 is in the off-state (i.e., nonconductingstate) with the data wire remaining in thelogically high state. Even when the memory element MP2is in the logical "0" state, no current can flow throughthe memory element MP1 because the word wire not selectis at the potential level of -V_w/2. When the memoryelement MP1 is in the logic "0" state, a current flowsfrom the data wire 1 to the grounded wire via the memoryelement MP1, resulting in lowering of the potential atthe data wire 1. This potential drop is amplified bythe sense amplifier, whereupon the data read-outoperation comes to an end. The memory device can beimplemented in this manner.

In the memory device now under consideration,peripheral circuits thereof such as a decoder, the senseamplifier, an output circuit and the like are implementedby using the conventional bulk MOSFET formed in asurface of a Si-substrate in such an arrangement asillustrated in Fig. 8, and a memory cell array includingthe memory elements MP1 to MP4 each of the structureillustrated in Fig. 1 are fabricated on the peripheralcircuits with an interposition of an insulation film.This is because polycrystalline silicon for the memoryelements MP1 to MP4 can be fabricated on the bulk MOSFETs. By virtue of this structure, the space or areaotherwise required for the peripheral circuits can bespared, whereby the memory device can be implementedwith about twice as high an integration density whencompared with that of the conventional dynamic RAM.Parenthetically, it should be added that a wiring layerwhich exists in actuality between the bulk MOSFETs andthe polycrystalline silicon transistor layer is omittedfrom illustration in Fig. 8.

As will be appreciated from the foregoingdescription, with the structure of the memory deviceaccording to the instant embodiment of the invention,there can be realized a integrated memory circuit with ahigh integration density because of capability ofstoring single-bit information by the single memoryelement. Besides, the integration density can furtherbe increased by stacking the memory cell array on theperipheral circuit layer in a laminated or stackedstructure. Additionally, there is no necessity forreading out a quantity of electric charge, as requiredin the case of the conventional dynamic RAM, but thesignal can be generated on the data wire in a staticmanner, so to say. Owing to this feature, fine structurizationcan further be enhanced without involvingdegradation in the signal-to-noise ratio (S/N ratio).Moreover, information as stored can be retained over anextended time period, which means that refreshing operationas required in the case of the dynamic RAM can be rendered unnecessary. Consequently, power consumptioncan be suppressed to a possible minimum. Further, theperipheral circuits can be implemented in much simplifiedconfiguration. Owing to the features mentionedabove, there can be realized according to the teachingsof the invention incarnated in the instant embodiment asemiconductor memory device with an integration densitywhich is at least twice as high as that of the conventionaldynamic RAM while the cost per bit can be reducedat least to a half of that required in the conventionaldynamic RAM. Of course, electric power required forholding or retention of information (data) can significantlybe reduced.

In the foregoing description, it has beenassumed that the low threshold voltage V_ℓ is of negativepolarity with the high threshold level V_h being positive,as illustrated in Fig. 7. However, even whenthese threshold voltages V_ℓ and V_h for the memory elementare set at higher levels, respectively, similar operationcan be ensured simply by setting correspondinglyhigher the gate control signal level.

Next, by reference to Figs. 9A and 9B,description will turn to a process for fabricating ormanufacturing the memory element and the memory deviceaccording to the instant embodiment of the invention.At first, an n-channel MOS 15 and a p-channel MOS 16(i.e., a CMOS (Complementary Metal-Oxide Semiconductordevice) are fabricated on a surface of a p-type Si-substrate 14, which is then followed by formation of aninsulation film over the CMOS device as well as formationof metal wires 17 (refer to Fig. 9A). Subsequently,an inter-layer insulation film 18 is depositedand the surface thereof is flattened for reducingroughness. Next, a polycrystalline silicon region whichis to serve as a gate electrode 4 of the memory elementis formed on the flat surface of the insulation layer18. To this end, the polycrystalline silicon region isdoped with n-type impurity at a high concentration sothat it exhibits a low resistance. Next, a SiO₂-filmwhich is to serve as a gate insulation film 5 isdeposited in thickness on the order of 50 nm over theinsulation layer 18 having the gate electrodes through achemical vapor deposition method (i.e., CVD method inabbreviation), which is then followed by deposition ofan amorphous silicon layer. After patterning of theamorphous silicon layer, source regions 1 and drainregions 2 are doped with n-type impurity such as As, Por the like through ion implantation and annealed at atemperature of about 750°C, whereby channels 3 of polycrystallinesilicon are formed. Finally, a protectionor passivation film 10 of SiO₂ is formed. Thus, therecan be fabricated a memory device of high integrationdensity according to the invention (refer to Fig. 9B).At this juncture, it should be added that an electricallyconducting layer may be provided on the top surfaceof the memory device for the purpose of shielding the memory device against noise to thereby enhance thereliability thereof.

Embodiment 2

Figs. 10A and 10B are sectional views showinga memory element according to a second embodiment of theinvention. An SOI (Silicon-On-Insulator)-substrate isemployed as the substrate, wherein Fig. 10B shows asection taken along as line a-a' in Fig. 10A. A sourceregion 19 and a drain region 20 are each constituted byan n-type silicon region of high impurity concentrationand low resistance, wherein a channel 21 of siliconextending between the source and drain regions 19 and 20is formed in a fine or thin wire. A thin film 25 ofSiO₂ is formed over the channel 21. Further, a storagenode 24 for confining carriers with silicon grains isformed on the channel region 21. A gate electrode 22 isprovided above the channel region 21 with a gate insulationfilm 23 being interposed therebetween.

With the structure of the memory elementaccording to the instant embodiment, the capacitance C_gcbetween the channel region 21 and the gate electrode 22can be reduced because of a very small wire width of thechannel 21. Writing and erasing operations can beeffected by changing potential level. More specifically,the writing can be carried out by injecting electronsfrom the channel region into the storage node 24by clearing a potential barrier provided by the insulation film 25, while for erasing the stored information,electrons are drawn out from the storage node 24. Thus,in the memory element according to the instant embodiment,writing and erasure of or data information to andfrom the storage node 24 are performed by transferringthe electrons with the channel. It should however bementioned that these operations can be realized throughelectron transferring with other region than the channelregion. The same holds true in the embodiments of theinvention which will be described below. Further,although silicon is employed for forming the source, thedrain and the channel with SiO₂ being used for formingthe insulation films in the memory element according tothe instant embodiment, it should be understood that thesource and the drain may be formed of other semiconductormaterial or metal and that the insulation filmmay also be formed with other compositions so long asthe capacitance C_gc satisfying the requisite conditionsmentioned previously can be realized.

Additionally, it is important to note thatalthough the storage node 24 is provided above thechannel 21 in the memory element according to theinstant embodiment, the storage node 24 may be providedbeneath the channel region or at a location laterally ofthe channel region. Besides, although it has beendescribed that the SOI substrate is employed with monocrystallinesilicon being used for forming the source,the drain and the channel, it should be understood that they may be formed by using polycrystalline silicon asin the case of the first embodiment. In that case,difference from the first embodiment can be seen in thatthe storage node 24 is provided independently. Itshould further be added that the material for the insulationfilm interposed between the channel region andthe storage node need not be same as the material of theinsulation film interposed between the gate and thestorage node.

Although it is presumed that the carriers areelectrons in the memory element and the memory deviceaccording to the instant embodiment, holes may equallybe employed as the carriers substantially to the sameeffect. This holds true in the embodiments describedbelow as well.

According to the teachings of the inventionincarnated in the instant embodiment, the storage node24 is formed by using crystal grains of a small size,wherein the storage node 24 of Si-grains is surroundedor enclosed by the gate insulation film 23 and theinsulation film 25 of SiO₂ to thereby reduce surroundingparasitic capacitance. Because of the small size of thegrains constituting the storage node 24, the surroundingor total capacitance C_tt therefor may be determined interms of intrinsic capacitance. In the case of aspherical body having a radiusr and enclosed by amaterial having a dielectric constantε, the intrinsiccapacitance thereof is given by 4πεr. By way of example, for the storage node formed by silicon crystalgrains having a grain size of 10 nm, the surrounding ortotal capacitance C_tt of the storage node is about 1 aF.

Figs. 11A and 11B show schematically andexaggeratedly a channel region, a carrier confinementnode and a gate electrode in a perspective view and asectional view, respectively.

Referring to Fig. 12, when a gate-sourcevoltage (i.e., voltage applied between the gate and thesource) is swept between a first voltage V_g0 (zero volt)and a second voltage V_g1 (5 volts) in the vertical directionas viewed in Fig. 12, the drain current exhibits ahysteresis characteristic. In this conjunction, relevantpotential distributions on and along a plane b-b'in Fig. 11B are illustrated in Figs. 13A to 13C andFigs. 14A to 14C. The reason why the hysteresis characteristicsuch as illustrated in Fig. 12 makes appearancewill be elucidated below.

In the semiconductor memory element shown inFig. 10, potential distribution making appearance in thechannel region 21 when the potential difference V_gsbetween the gate and the source is zero volt is schematicallyshown in Fig. 13A. This corresponds to the state25 shown in Fig. 12. Parenthetically, it is assumedthat the drain current flows in the direction perpendicularto the plane of the drawing Fig. 13A. Thedescription which follows will be made on the assumptionthat the drain-source voltage is sufficiently low as compared with the gate voltage, being however understoodthat the following description applies valid as it is,even when the voltage between the drain and the sourceis high.

Now referring to Fig. 13A, in the channelregion 21 surrounded by a potential barrier 25 formedbetween the channel region 21 and the storage node 24and the peripheral SiO₂-film 23, there prevails a low-energypotential. Thus, the storage node 24 (carrierconfinement region) formed of Si-grains and surroundedby the insulation films 23 and 25 can capture or trapthe carriers or electrons. On the other hand, noelectrons exist in the channel region 21 because energylevel of the conduction band in the channel region 21 ofP-type or N-type having low impurity concentration ori-type (intrinsic semiconductor type) is sufficientlyhigher than the energy level of the conduction band inthe N-type source 19 of a high impurity concentration orFermi level in the N-type degenerate source region 19having a high impurity concentration. Consequently, nodrain current can flow.

Incidentally, energy in the carrier confinementregion or the storage node 24 is sufficientlyhigher than the Fermi level in the source region 19.Thus, no electron exists in this region 24 either.

As the potential difference V_gs between thegate electrode 22 and the source 19 is increased fromzero volt to the low threshold voltage V_ℓ, potential in the channel region 21 increases. As a consequence,potential in the channel region 21 for electrons becomeslower, as can be seen in Fig. 13B, hereby electrons areintroduced into the channel region 21 from the source19. Thus, a current flow takes place between the sourceand the drain.

When the gate voltage is further increased,the number of electrons existing in the channel region21 increases correspondingly. However, when the gate-sourcevoltage V_gs reaches a writing voltage V_g1, energyin the storage node 24 becomes low, being accompaniedwith a corresponding increase of the potential gradientbetween the channel 21 and the storage node 24. As aconsequence of this, at least one electron will beentrapped in the storage node 24 by clearing the potentialbarrier 25 due to thermal energy distribution ofelectron and/or tunneling phenomenon (tunnel effect).This corresponds to transition from the state 27 to thestate 28, as illustrated in Fig. 12.

Thus, there takes place a Coulomb blockadeowing to one electron trapped in the storage node 24 aswell as potential increase, whereby injection of anotherelectron in the storage node 24 is prevented, as isillustrated in Fig. 14A.

In this way, every time one electron isentrapped in the storage node 24, the threshold voltageof the semiconductor memory element shown in Fig. 10changes from the low threshold V_ℓ to the high threshold voltage V_hs, the reason for which will be explainedbelow.

When the gate-source voltage V_gs is loweredwithin the range of V_h (high threshold voltage) < V_gs <V_ℓ (low threshold voltage), starting from the stateillustrated in Fig. 14A, the number of electrons in thechannel region 21 decreases. However, electron capturedor trapped in the storage node 24 remains as it is,because of existence of the potential barrier 25 betweenthe storage node 24 and the channel 21.

When the voltage of the gate electrode 22 islowered to a level where the potential difference V_gs isequal to the high threshold voltage Vh, the Fermi levelin the source 19 becomes different from the energy levelof the conduction band in the channel 21 by a magnitudeon the order of kT, as a result of which substantiallyall of the electrons in the channel region make disappearance,(refer to Fig. 14B). This corresponds to thestate 29 shown in Fig. 12. At this juncture, it shouldhowever be mentioned that the threshold value V_h atwhich the drain current can no more flow becomes higherthan the low threshold voltage V_ℓ by an amount of thecharge of the electrons captured in the storage node 24.

As the gate-source voltage V_gs is furtherlowered to a level where it becomes equal to zero volt,the potential gradient between the storage node 24 andthe channel region 21 becomes steeper correspondingly,as a result of which the electron captured in the storage node 24 is released owing to the tunnelingeffect brought about by thermal energy distribution ofelectrons and the field effect (refer to Fig. 14C).Potential profile in the state where electrons aredispelled is equivalent to the initial potential profileillustrated in Fig. 13A. This means that the semiconductormemory element resumes the state 25 shown inFig. 12.

Subsequently, when the gate-source voltage V_gsis again increased for effecting repeatedly the sweep inthe vertical direction, hysteresis phenomenon whichaccompanies the capture/release of electron can beobserved.

In the structure of the memory element nowunder consideration, the condition given by the expression(8) has to be satisfied in order to detect thepresence/absence of a single electron in terms of acurrent.

Next, description will turn to a method offabricating the memory element or memory device accordingto the instant embodiment of the invention. AS isshown in Figs. 10A and 10B, the source region 19, thedrain region 20 and the channel region 21 are formed inthe SOI substrate by resorting to a photoetchingprocess. The channel region is realized in the form ofa fine or thin wire. The source and drain regions aredoped with n-type impurity at a high concentration. Bycontrast, the channel region is doped with n-type or i-type or p-type impurity at a low impurity concentration.Subsequently, the SiO₂-film 25 is deposited through aCVD (chemical vapor deposition) process, which is thenfollowed by formation of a crystal silicon grain or thestorage node 24 through a CVD process.

In order to form the silicon crystal grain 24(which is to serve as the storage node 24) having a verysmall radiusr, a nucleus formed initially in the CVDdeposition process is made use of for forming thecrystal silicon grain 24. To this end, formation of thecrystal silicon grain 24 by the CVD method should becarried out at a low temperature and completed within ashort time.

Embodiment 3

Fig. 15A and 15B show in sections a memoryelement according to a third embodiment of the presentinvention, respectively, in which Fig. 15B is a sectionalview taken along a line a-a' in Fig. 15A. Thememory element or memory device according to the instantembodiment differs from the second embodiment in thatthe former is implemented in such a structure in which achannel region 33 and a carrier confinement region orstorage node 34 are sandwiched between a pair of gateelectrodes 31 and 32. Thus, in the memory element ormemory device according to the instant embodiment,writing and erasing operations can be performed not onlyfrom the first gate electrode 31 but also through the medium of the second gate electrode 32.

In the case of memory element or memory deviceaccording to the second embodiment of the invention, itis expected that potential profiles in the carrierconfinement region and in the vicinity of the channelregion inclusive thereof may undergo variation under theinfluence of change in the external potential. Bycontrast, the memory element or memory device accordingto the instant embodiment is less susceptible to theinfluence of such external potential change owing to theshielding effect of the gate electrodes provided at bothsides, to an additional advantage.

Embodiment 4

Figs. 16A to 16C show a memory elementaccording to a fourth embodiment of the invention,wherein Fig. 16A is a sectional view, Fig. 16B shows asection taken along a line a-a' in Fig. 16A and Fig. 16Cis a top plan view. Referring to the figures, formedover a channel region 39 of a bulk MOSFET in which asource 35 and a drain 36 are formed in a siliconsemiconductor crystal substrate is an insulation film 40on which a plurality of silicon crystal grains 41 areformed. Further, an insulation film 42 is formed overthe insulation film 40 and the grains 41. Additionally,a second gate electrode 38 is deposited on the insulationfilm 42. This gate electrode 38 is of such a shapethat a gap exists in the direction interconnecting the source 35 and the drain 36. A first gate electrode 37is provided above the second gate electrode 38 with aninsulation film 43 being interposed therebetween. Thesource 35 and the drain 36 are each constituted by aregion formed of an n-type bulk silicon having a highimpurity concentration, wherein a p-type region 44intervenes between the source region 35 and the drain36.

By applying a voltage of positive or pluspolarity to the first gate electrode 37, electrons areinduced in a surface portion of the p-type region 44,whereby a channel 39 is formed. In that case, thepotential of the second gate electrode 38 is set lowerthan the first gate electrode 37 so that the second gateelectrode 38 also operates as an electrostatic shieldelectrode. As a result of this, the channel region 45is formed only in a region located in opposition to thefine gap of the second gate electrode 38, whereby theeffective capacitance C_gc between the first gate electrode37 and the channel region 39 can be made smaller.Writing and erasing operations can be realized bychanging the potential of the first gate electrode 37 orthe second gate electrode 38 or the substrate 37 in asubstantially same manner as described hereinbefore inconjunction with the third embodiment.

Embodiment 5

Fig. 17A shows a cross section of a memory element according to a fifth embodiment of the presentinvention. The direction in which the current flowsextend perpendicularly to the plane of the drawing. Thechannel region and the carrier confinement region (storagenode) as well as regions located in the vicinity areshown exaggeratedly. The source and the drain areimplemented in same configurations as those of thememory element according to the second embodiment of theinvention. The instant embodiment differs from thesecond embodiment in that a thin film 48 of silicon isformed in SiO₂-insulation films 49 and 50 between achannel region 46 of silicon and a storage node (carrierconfinement node) 47 formed by a silicon crystal grain.

Carriers within a channel 46 can reach thestorage node (carrier confinement region) 47 via theSi-thin film 48. Fig. 17B shows a potential profile inthe memory element of the structure mentioned above.Referring to Fig. 17B, an energy shift 52 takes place inthe Si-thin film 48 due to the quantum confinementeffect in the direction thicknesswise. The thin Si-film48 plays a role as a barrier for the migration ofelectron from the Si-channel region 46 to the carrierconfinement region (storage node) 47. As a result ofthis, for achieving the same barrier effect, the sum offilm thicknesses of the SiO₂-films 49 and 50 existingbetween the channel and the carrier confinement regionmay be reduced as compared with the film thickness ofthe SiO₂-film located between the channel region and the carrier confinement region of the memory element inwhich the structure according to the instant embodimentis adopted (e.g. refer to Figs. 10A and 10B). Accordingly,fatigue of the insulation film can be mitigated,whereby the number of the times the memory is rewrittencan be increased.

It should further be mentioned that thepotential barrier realized by making use of the quantumconfinement effect described above is effective forprotecting the insulation film against fatigue even inthe case where a greater number of carriers are to behandled by the carrier confinement region.

Embodiment 6

A structure of a memory read circuit for asemiconductor memory device according to the inventionwill be described by reference to Figs. 18A to 18C andFig. 19. In the description which follows, the semiconductormemory element according to the inventionwhich may be one of the elements described hereinbeforeby reference to Figs. 1A - 1D, Fig. 6, Figs. 10A, 10B,Figs. 15A, 15B, Figs. 16A - 16C and Figs. 17A, 17B,respectively, is identified by representing the carriertrapping node (carrier confinement region) by a solidcircle as shown in Fig. 18 for the purpose of discriminationfrom the conventional field effect transistor.On Figs. 18A to 18C, Fig. 18A shows a circuit configurationof a single-bit memory cell, Fig. 18B shows voltages applied to a word wire W and a data wire D uponread and write operations, respectively, and Fig. 18Cgraphically illustrates a dependency of a drain currenton a gate voltage (gate-source voltage) in a semiconductorelement MM7 employed for realizing the memorycell. The circuit configuration per se is identicalwith that described hereinbefore in conjunction with thefirst embodiment by reference to Fig. 6.

Fig. 19 shows a circuit configuration forreading data or information stored in a memory cell MM1.Needless to say, a large number of memory cells similarto the memory cell MM1 are disposed in an array in thememory device which the invention concerns, althoughillustration thereof is omitted. The memory cell MM1serving for storing information differs from theconventional MOSFET known heretofore in that the valueof a current which can be handled by the memory cell issmaller as compared with that of the MOSFET. This isbecause the gate-channel capacitance is set small in thecase of the memory cell according to the invention. Astructure for reading such a small current value stablyat a high speed will be described below. The memorycell constituted by the semiconductor memory element MM1is connected to a data wire D which in turn is connectedto an input transistor M9 constituting a part of adifferential amplifier via a data wire selecting switchM5. Connected to another data wire Dn provided in pair with the data wire D are dummy cells constituted bysemiconductor memory elements MM5 and MM6, respectively.The data wire Dn is connected to a gate terminal of aninput transistor constituting the other part of thedifferential amplifier via a data wire selecting switchM6.

Now, description will be directed to operationfor reading data from the memory cell MM1. Fig. 20shows timing of signals involved in the read operation.It is assumed that logic "0" is written in the memorycell MM1 which is thus in the state where the thresholdvoltage is low. Each of the dummy cells MM5 and MM6 isalways written with logic "0" previously. Upon readoperation, a signal S2 is set to a low level to therebyprecharge both the data wires D and Dn to a sourcevoltage V_r. At the same time, signals S3 and S4 are setto a high level to thereby allow the data wires D and Dnto be connected to the input transistors M9 and M10 ofthe differential amplifier, respectively. Further, atthe same timing, signals S5 and S6 are set to the highlevel to thereby activate the differential amplifier sothat the outputs OUT and OUT_n are equalized to eachother. By changing potentials of the word wire W1 andWD from the low level to the high level, the memory cellMM1 and the dummy cells MM5 and MM6 are selected. Then,the memory cell MM1 assumes the on-state (conductingstate), which results in that the potential of the datawire D becomes low. At the same time, the dummy cells MM5 and MM6 are set to the on-state, whereby the potentialof the data wire Dn becomes low. However, becausethe dummy cells MM5 and MM6 are connected in series, thecurrent driving capability thereof is poor as comparedwith that of the memory cell MM1. Consequently, thepotential of the data wire Dn changes more gently thanthat of the data wire D. When data of the data wires Dand Dn are fixed, a signal S6 is set to the low level,whereby the differential amplifier can assume the stateready for operation. The potential difference betweenthe data wires D and Dn is amplified by the differentialamplifier, the output OUT of which thus assumes the highlevel while the other output OUTn becomes low. At thistime point, operation for reading logic "0" from thememory cell MM1 is completed.

When the memory cell MM1 is in the state oflogic "1" (i.e., in the state where the threshold valueis high with only a small current flowing), the datawire D remains in the precharged state, as a result ofwhich the potential of the data wire Dn lowers morespeedily than that of the data wire D. The resultantdifference is then amplified by the differentialamplifier, whereupon the read operation comes to an end.

For reading information from the memory cellconstituted by a semiconductor memory element MM2, thesemiconductor memory elements MM3 and MM4 then serve asthe dummy cells. It is sufficient to provide a singledummy cell for each of the data wires. Thus, the area requirement can be suppressed to a minimum.

With the circuit arrangement described above,information read operation can be effectuated even whenonly a small potential difference makes appearancebetween the data wires D and Dn. This means that thequantity of charge to be discharged from the data wire Dvia the memory cell MM1 may be small. By virtue ofthese features, high-speed operation can be realized.

In the case of the exemplary embodimentdescribed above, the series connection of the dummycells MM5 and MM6 is provided as the means for makingthe dummy cell current substantially equal to a half ofthe memory cell current. However, the referencepotential can be generated by reducing the channel widthto a half or lowering the applied gate voltage insteadof resorting to the provision of the serial dummy-cellconnection.

Figs. 21A and 21B show a circuit configurationof memory cells in a semiconductor memory device and alayout thereof, respectively. More specifically,Fig. 21A is a circuit diagram showing four memory cellsarrayed adjacent to one another, while Fig. 21B shows amask layout corresponding to the circuit configurationshown in Fig. 21A. The two memory cells MM91 and MM92connected to a word wire W91 share one and the same gateelectrode in common, whereby the wiring required, ifotherwise, can correspondingly be spared. On the otherhand, for the other memory cells MM93 and MM91 which are connected to a same data wire D91, diffused layersthereof are directly connected to each other forallowing a single contact (CT) to be shared by both thememory cells MM93 and MM91, whereby the wiring area asrequired is correspondingly reduced.

Embodiment 7

Another embodiment of the semiconductor memorydevice according to the invention will be described byreference to Figs. 22A to 22C and Fig. 23. With thestructure of this embodiment, the read operation can becarried out at a higher speed than the semiconductormemory device according to the sixth embodiment.

Of these drawings, Fig. 22A shows a circuitdiagram of a cell set comprised of an assembly of pluralmemory cells MM51, MM52 and MM53 which are connected tothe same sub-data wire D, Fig. 22B shows voltagesapplied to the memory element MM51 upon write and readoperations, Fig. 22C graphically illustrates characteristicof the memory element MM51, and Fig. 23 shows astructure of a semiconductor memory device implementedby using the cell sets each of a structure shown in Fig.22A. The instant embodiment differs from the sixthembodiment primarily in that the data wire is hierachizedinto a main data wire MD 51 and a sub-data wireD (see Fig. 23) in order to carry out read operation ata higher speed. As can be seen in Fig. 22A, the sourceterminals of the memory cells MM51, MM52 and MM53 are connected to the sub-data wire D, which in turn isconnected to a preamplifier comprised of transistors M53and M52 and generally denoted by PA51. The preamplifierPA51 has an output terminal connected to a main datawire MD 51 (see Fig. 23). Connected to the main datawire MD 51 are a plurality of cell sets each of thestructure mentioned above via the respective preamplifiers.The main data wire MD 51 is connected to one ofthe input terminals of a main amplifier MA51 constitutedby a differential amplifier. A column of dummy cells isconstituted by cell sets disposed in an array. Thedummy cell (e.g. MM54) is connected to another main datawire MD 52 via a preamplifier PA52. The main data wireMD 52 in turn is connected to the other input terminalof the main amplifier MA51. The preamplifier PA52 forthe dummy cell set is so designed that the currentdriving capability thereof approximately corresponds toa half of that of the preamplifier PA51. This can berealized, for example, by diminishing the channel widthof the transistor to the half.

Next, description will turn to operation forreading information from a memory cell MM51. Informationof logic "0" is written in the dummy cell MM54previously. It is first assumed that information oflogic "0" is stored in the memory cell MM51. At first,high-level potential V_r is applied to a gate terminalS52 of the transistor M51 to thereby set the sourceterminal S51 to the ground potential level, whereby the sub-data wire D is set to the ground potential level.Further, for the selection of cell set, high-levelpotential is applied to the gate terminal S53 to therebyset the transistor M52 of the preamplifier PA51 to theconducting state (on-state). At the same time, the maindata wires MD 51 and the MD 52 are precharged to thehigh potential level V_r. When the potential of the wordwire W changes from a low level to a high level V_r, thememory cell MM51 becomes conductive, whereby the sub-datawire D is charged from a source terminal P (= V_r)via the memory cell MM51. Consequently, the transistorM53 is turned on, which results in that the main datawire MD 51 is discharged through the memory cells MM52and MM53 with the potential of the main data wire MD 51being lowered. Through similar operation, the dummycell MM54 connected to the same word wire assumes theon-state. In response, the preamplifier PA52 operatesto cause the main data wire MD 52 to be discharged.Thus, the potential of the main data wire MD 52 islowered. However, because the current driving capabilityof the preamplifier PA52 is poor as compared withthat of the preamplifier PA51, the potential of the maindata wire MD 52 is lowered at a slower rate than that ofthe main data wire MD 51. Thus, there makes appearancebetween the main data wires MD 51 and MD 52 a potentialdifference, which is detected by the main amplifierMA51, whereby corresponding output information isderived from the main amplifier MA51. Operation for reading out logic "1" is carried out in the similarmanner.

In the case of the instant embodiment, it issufficient for the memory cell MM51 only to drive thesub-data wire D. The sub-data wire features that theparasitic capacitance is small, because the number ofthe cells connected to the sub-data wire is as small asin a range of 8 to 32 and because the length of thesub-data wire is short. Thus, the sub-data wire can bedriven by the memory cell or memory element MM51 at ahigh speed. Equally, high-speed operation of the maindata wire MD 51 can be achieved because it can be drivenat a high speed by the preamplifier PA51.

According to the teaching of the inventionincarnated in the instant embodiment, the preamplifiersPA52 and PA51 are so implemented that they differ inrespect to the current driving capability for thepurpose of generating a reference voltage for thedifferential amplifier PA51. When compared with thesixth embodiment in which the current is reduced to ahalf by the memory cell per se, the instant embodimentaccording to which the current level is changed in thepreamplifier constituted by the transistors of higherrating is advantages in that it is less susceptible tothe influence of the dispersions mentioned hereinbefore.

Parenthetically, the main amplifier MA51 canbe implemented by using an appropriate one of variouscircuits known in the art such as differential amplifier employed in the device of the sixth embodiment, acurrent-mirror type differential amplifier circuit andthe like.

In the case of the sixth and seventh embodimentsdescribed above, it has been assumed that thememory cell is constituted by a single transistor. Itshould however be mentioned at this juncture that thememory cell may be implemented in other configurationssuch as exemplified by those shown in Figs. 24A to 24E.More specifically, Fig. 24A shows a memory cell in whicha back gate is provided in opposition to the gate electrodewith the channel being interposed between the backgate and the gate electrode. This structure of thememory cell provides an advantage that when a pluralityof memory cells are connected to a same back gate terminal,information or data contained in these memory cellscan simultaneously be set to logic "0" by applying avoltage of minus polarity to the back gate. Of course,by applying a voltage of plus or positive polarity tothe back gate, it is equally possible to write simultaneouslylogic "1" in these memory cells.

In this junction, the back gate terminal maybe realized by making use of the semiconductor substrateitself, a potential well or the like.

Fig. 24B shows a memory cell in which theterminal wire P extends in parallel with the word wireso that control of the memory device can be performed ona row-by-row basis independently. On the other hand, Fig. 24C shows a memory cell in which the terminal wireP extends in parallel with the data wire. Further, Fig.24D shows a memory cell in which the gate of the memoryelement MM73 is connected to the data wire. In thiscase, the terminal P can be spared, which contributes toreduction of the area as involved in implementing thesemiconductor memory device. Finally, Figs. 24E shows amemory cell in which the gate of the memory element MM74is connected to the word wire and which thus can ensurean advantage similar to that of the memory cell shown inFig. 24D.

Embodiment 8

Figs. 25A to 25C and Fig. 26 show a semiconductormemory device according to an eighth embodimentof the invention. As can be seen in Fig. 25A, thememory cell of the memory device according to theinstant embodiment is constituted by a circuit includinga memory element MM21 according to the invention and aswitching FET (field-effect transistor) M25 which areconnected in series. More specifically, the word wireis connected to the gate of the switching FET M25 sothat the voltage applied to the memory element MM21 fromthe data wire D can be interrupted by the switching FETM25. Thus, necessity for applying a voltage to non-selectedmemory cells which shares the word wire or thedata wire with the selected memory cell can be obviated.This in turn means that the device according to the instant embodiment is excellent over the sixth andseventh embodiments in respect to the data holdcharacteristic, to an advantage.

Writing operation for the memory cell accordingto the instant embodiment is performed in a mannerdescribed below. First, operation involved in writinglogic "0" will be considered. Applied to the word wireto be selected is a voltage of (V_cc + V_t) while thepotential level of zero volt is applied to the data wireto be selected. As a result, the switching FET M25 isturned on, whereby a node N21 assumes approximately theground potential level. Since the source terminal P isat a voltage level of V_cc/2, a voltage of -V_cc/2 isapplied across the gate and the source of the memoryelement MM21, whereby information of logic "0" iswritten in the memory cell (refer to Fig. 25C). Next,operation for writing logic "1" is considered. Also inthis case, the voltage of (V_cc + V_t) is applied to theword wire while applying the voltage V_cc to the datawire. Thus, the voltage V_cc/2 is applied between thegate and the source of the memory element MM21, wherebylogic "1" is written in the memory cell (refer toFig. 25C).

The operation for reading data or informationfrom the memory cell according to the instant embodimentcan be carried out by the means of the similar to thoseadopted in the sixth and seventh embodiments. However,in connection with the instant embodiment, the invention teaches an arrangement which allows the read/writeoperation to be performed at a lower source voltage.Referring to Fig. 26, for reading out information fromthe memory cell comprised of the memory element M25 andthe switching FET MM21, the potential level of the wordwire W21 is changed to the source voltage level V_cc fromthe ground potential level, and at the same time thepotential of the word wire WD22 of the dummy cellcomprised of a switching FET M27 and memory elementsMM25 and MM26 is changed from low level to high level.Succeeding operation is the same as that of the sixthembodiment except that after the output is fixed,rewriting is performed for the memory cell by a writingdriver connected to the output of the sense amplifier.By way of example, when logic "1" is to be written inthe memory element MM21, the voltage V_cc is applied tothe data wire D. In that case, a voltage substantiallyequal to V_cc is applied across the gate and the source ofthe memory element MM21, whereby logic "1" can bewritten in the memory element MM21. On the other hand,when logic "0" is to be written, the data wire is set tothe ground potential level. Thus, the voltage of -V_cc/2is applied between the gate and the source of the memoryelement MM21, whereby logic "0" is written in the memorycell.

In the memory device according to the instantembodiment, every time the data read operation isperformed, rewriting operation is carried out in succession. By virtue of this arrangement, inversion of theinformation or data held by the memory element MM21 fromlogic "0" to logic "1" will present no problem so longas such inversion takes place only after the potentialdifference of such a magnitude which enables the readoperation has occurred between the data wire D and thedummy data wire Dn. Thus, the read voltage V_r and thewrite voltage V_cc/2 can be set at values or levels whichare relatively close to each other. This in turn meansthat the write voltage can be set at a low level. Byway of concrete example, the read voltage V_r may be setat 3 volts with the write voltage V_cc/2 being set at4 volts. By contrast, in order to ensure positivelyprevention of the information or data inversion fromoccurrence in the read operation as described hereinbeforein conjunction with the seventh embodiment (seeFig. 22C), the write voltage V_p has to be set at aboutthree times as high as the read voltage V_r. Thisnecessitates application of a high voltage for the writeoperation.

Figs. 27A and 27B are circuit diagrams showingversions of the memory cell circuit according to theinstant embodiment, respectively. The memory cell shownin Fig. 27A differs from the one shown in Fig. 25A inthat a source terminal P is connected to the gate of thememory element MM81. On the other hand, in the memorycell shown in Fig. 27B, the gate of the memory elementMM82 is controlled by a control signal C supplied externally of the memory cell.

Figs. 28A and 28B show a circuit configurationand a layout of a semiconductor memory device includinga number of memory cells each of the structure shown inFig. 27A which corresponds to four bits. In thesefigures, the memory cells MM101 to 104 are each constitutedby the polycrystalline silicon memory elementdescribed hereinbefore in conjunction with the firstembodiment. As can be seen from Fig. 28B, the wordwires for the adjacent memory cells are constituted byone and the same electrode, while a contact is shared incommon by the two adjacent memory cells and connected tothe data wire. It will thus be understood that the arearequired for implementation of the memory cell cansignificantly be decreased.

Embodiment 9

Figs. 29A to 29C show a memory cell circuitand a read circuit according to a ninth embodiment ofthe invention. More specifically, Fig. 29A shows acircuit diagram of a memory cell according to theinstant embodiment, Fig. 29B shows voltages as appliedupon read and write operations performed for the memorycell, and Fig. 29C graphically illustrates characteristicsof memory elements MM31 and MM32 employed in thememory cell. A feature of the memory cell according tothe instant embodiment of the invention resides in thatcomplementary information or data are written in the memory elements MM31 and MM32. More specifically, forwriting logic "1", a voltage of V_cc is applied to theword wire W while a voltage of V_e (of negative polarity)is applied to the data wire D, as a result of which aswitching FET M33 is turned on, whereby the potential ofthe data wire D is applied to a node N31 which thusassumes the potential level V_e. Since the voltage V_e isapplied between the gate and the source of the memoryelement MM32, the latter is set to a low thresholdstate. In contrast, a voltage of (V_cc - V_e) is appliedbetween the gate and the source of the memory elementMM31, which thus assumes a high threshold state. Forwriting logic "0" in the memory cell, the data wire D isset to the write voltage level V_p. As a result of this,the memory element MM31 assumes the low threshold statewith the memory element MM32 in the high thresholdstate. In succession to the write operation, thepotential level of the data wire is set to V_cc/2, whichresults in application of voltage of about V_cc/2 betweenthe gates and the sources of the memory elements MM31and MM32, respectively. In the logic "1" state, thedata wire D tends to discharge, while in the state oflogic "0", the data wire D is charged. This trend orstate is detected by the differential amplifier forreading the data or information, as can be seen inFig. 30.

In the memory cell according to the instantembodiment of the invention, the potential level of the data wire lowers or rises in dependence on whether theinformation or data of the memory cell to be read out islogic "1" or "0". Accordingly, it is possible to applydirectly the reference voltage (V_cc/2) to one of inputterminals of the differential amplifier. For thisreason, no dummy cell is required, to an advantage. Inthis conjunction, it should be recalled that in the caseof the circuit configurations according to the embodimentsdescribed hereinbefore, the dummy cells have to beprovided because it is indefinite whether the potentiallevel of the data wire is maintained or lowered independence on whether the memory cell data is logic "1"or "0".

Embodiment 10

Description will now turn to a memory cellcircuit according to a further embodiment of theinvention by reference to Figs. 31A to 31C, in whichFig. 31A shows a memory cell circuit for a single bitaccording to the instant embodiment of the invention,Fig. 31B shows voltages for read and write operations,respectively, and Fig. 31C graphically illustratescharacteristics of the memory elements MM41 and MM42.In the memory cell according to the instant embodiment,such arrangement is adopted that a pair of memory cellseach of the structure shown in Fig. 27A can be selectedby means of one and the same word wire. To this end,memory elements MM41 and MM42 are adapted to store information or data which are complementary to eachother. Namely, when the memory element MM41 is set to alow threshold state, the memory element MM42 is set to ahigh threshold state, and vice versa. Consequently,when the word wire is set to a high potential levelafter the write operation, there makes appearancebetween the data wires D and Dn a potential differencereflecting a difference in the current driving capabilitybetween the memory elements MM41 and MM42. Thus,by connecting the data wires D and Dn to a pair of inputterminals of a differential amplifier, it is possible toread information or data stored in the memory cell.

In the memory cell or memory device accordingto the instant embodiment of the invention, stableoperation can be ensured without need for provision ofthe dummy cell as well as need for generation of thereference potential level for the differential amplifier.Thus, the circuit design can be simplified.Parenthetically, similar advantage can be assured byusing a memory cell circuit shown in Fig. 33.

In the foregoing description of the exemplaryembodiments, it has been assumed that an n-channel gateinsulated field effect transistor is employed as theswitching element. It goes, however, without sayingthat it may be replaced by other type of switchingelement. By way of example, a p-channel field effecttransistor may be employed. In that case, the polarityof the voltage applied to the gate electrode must of course be inverted.

Besides, in the foregoing description, it hasbeen assumed that the semiconductor memory element is ofn-channel type. It is however obvious that the memoryelement as well as the memory device can be implementedby using p-channel memory element (i.e., element capableof operating with holes).

Embodiment 11

The semiconductor memory devices or simply thememories described hereinbefore in conjunction with thesixth to tenth embodiments feature that information ordata can be held without being volatilized. Thus, thetime taken for data write operation is extremely shortwhen compared with the conventional non-volatile memory,and no limitation is imposed to the number of times therewriting operation is performed. Further, because thewriting operation is completed by injecting only a fewelectrons, the writing operation of a very high speedcan be achieved. The reason why no limitation isimposed on the number of times for the writing operationcan be explained by the fact that the writing isrealized by the move of a few electrons.

The memory devices according to the inventioncan very profitably be employed as a main memory of amicroprocessor in a data processing system such as shownin Fig. 34. Since the memory device according to theinstant embodiment is nonvolatile, information stored once in the memory device can be held even after asource power supply is interrupted. Owing to thisfeature, the external storage implemented in the form ofa hard disk or floppy disk can be realized by a memorychip fabricated according to the teachings of theinvention. Besides, because of nonvolatileness of themain memory, a computer incorporating this type of mainmemory can instantaneously be restored to the stateprevailing immediately before interruption of the powersupply.

Additionally, by using the semiconductormemory device described in conjunction with the sixth totenth embodiments as a cache memory in a microprocessor,not only the cache memory can be made nonvolatile butalso power consumption of the microprocessor can bedecreased significantly.

As is apparent from the foregoing description,there is provided according to the invention the semiconductormemory devices which can be implemented with asmall number of memory elements which per se have informationor data storing capability while mitigating therequirement imposed on the area for implementation withoutneed for cooling at a cryogenic level of temperature.Thus, by using the semiconductor memory deviceaccording to the invention, there can be realized anonvolatile memory device susceptible to high speedrewrite operation.

Claims (6)

1. A semiconductor element, comprising

   a source region (19) and a drain region (20) interconnectedthrough a channel region (21);

   a gate electrode (22) connected to said channel region(21) through a gate insulation film (23);

   at least one carrier confinement region (24) formed inthe vicinity of said channel region (21); and

   a potential barrier (25) between said carrier confinementregion (24) and said channel region (21);

   characterised in that
      the capacitance between said channel region (21) andsaid carrier confinement region (24) is greater than thecapacitance between said gate electrode (22) and said carrierconfinement region (24); and
      the total capacitance (C_tt) existing around said carrierconfinement region (24) is so set as to satisfy the followingcondition:q2/2Ctt > kTwhere
      k is the Boltzmann constant,
      T is the operating temperature in degree Kelvin, and
      q is the charge of an electron.
2. A semiconductor element according to claim 1, wherein aneffective capacitance (Cgc) between said gate electrode andsaid effective channel region is set as to satisfy a conditiongiven by the following inequality expression:1/Cgc > kT/q2wherein
      C_gc represents said effective capacitance,
      k represents Boltzmann's constant,
      T represents an operating temperature in degree Kelvin,and
      q represents charge of an electron.
3. A semiconductor element according to claim 1 or 2,wherein said effective channel region (21) is provided on aninsulation film (25).
4. A semiconductor element according to any of claims 1 to3, wherein said gate electrode includes a first gate electrode(31) and a second gate electrode (32); and
      said effective channel region (33) and said carrier confinementregion (34) being disposed between said first gate electrode (31) and said second gate electrode (32).
5. A semiconductor element according to any of claims 1 to4, wherein said gate electrode includes a first gate electrode(37) and a second gate electrode (38); and
      said second gate electrode (38) is disposed between saidfirst gate electrode (37) and said effective channel region(39).
6. A semiconductor element according to any of claims 1 to5, wherein an island of crystal thin film is used for formingsaid carrier confinement region.

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