Movatterモバイル変換


[0]ホーム

URL:


EP0893827B1 - Electronic device and method for forming a membrane for an electronic device - Google Patents

Electronic device and method for forming a membrane for an electronic device
Download PDF

Info

Publication number
EP0893827B1
EP0893827B1EP97401796AEP97401796AEP0893827B1EP 0893827 B1EP0893827 B1EP 0893827B1EP 97401796 AEP97401796 AEP 97401796AEP 97401796 AEP97401796 AEP 97401796AEP 0893827 B1EP0893827 B1EP 0893827B1
Authority
EP
European Patent Office
Prior art keywords
layer
membrane
semiconductor substrate
substrate
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP97401796A
Other languages
German (de)
French (fr)
Other versions
EP0893827A1 (en
Inventor
Jean-Paul Guillemet
Myriam Combes
Stephen Astie
Emmanuel Scheid
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Freescale Semiconducteurs France SAS
Original Assignee
Motorola Semiconducteurs SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Semiconducteurs SAfiledCriticalMotorola Semiconducteurs SA
Priority to DE69728976TpriorityCriticalpatent/DE69728976T2/en
Priority to EP97401796Aprioritypatent/EP0893827B1/en
Priority to US09/120,755prioritypatent/US6022754A/en
Priority to KR1019980029781Aprioritypatent/KR100578259B1/en
Priority to CN98116373Aprioritypatent/CN1213081A/en
Priority to JP22525298Aprioritypatent/JP4271751B2/en
Publication of EP0893827A1publicationCriticalpatent/EP0893827A1/en
Application grantedgrantedCritical
Publication of EP0893827B1publicationCriticalpatent/EP0893827B1/en
Anticipated expirationlegal-statusCritical
Expired - Lifetimelegal-statusCriticalCurrent

Links

Images

Classifications

Definitions

Landscapes

Description

Field of the Invention
This invention relates in general to electronic devices and a method forforming electronic devices. More particularly, this invention relates to lowpower electronic devices and a method for their manufacture.
Background of the Invention
A chemical sensor is a device which monitors the concentration of agiven chemical species in a liquid or a gas. Chemical sensor devices comprise asensitive layer, which is sensitive to a particular chemical which is to bedetected by the sensor device, and a heater integrated on a semiconductorsubstrate such as a silicon substrate. The heater increases the temperatureof the sensitive layer to increase the sensitivity of the sensor device and istypically required to heat the sensitive layer to temperatures in the range of25ºC to 600ºC during operation of the sensor device. At these temperatures,there is significant loss of thermal energy through the silicon substrate andtherefore such devices suffer from high power consumption.
The high power consumption is a particular problem when the sensordevice is required to be powered by a battery. For example, some applicationsmay require battery back-up operation. For such battery poweredapplications, the power consumption should be around 60mw at 400ºC in DCmode.
In order to reduce the power consumption in semiconductor chemicalsensors, it has been proposed, see for example French Patent Application no.FR-A-2615287, to micromachine the backside of the bulk silicon substrate toform a thin membrane under the active region of the sensor device (i.e. underthe heater and sensitive layer). The thin membrane is formed by depositing asolution of Boron Oxide (B2O3) by spin-on onto the silicon substrate and by thendiffusing the boron dopant into the substrate. Although this technique reducesthe thermal losses to the bulk silicon substrate, since the membranecomprises a silicon layer doped with P+ type material, which material has a high thermal conductivity (35Wm-1K-1), the thermal losses during use of thesensor, and hence power consumption, are still too high for low power operation,such as battery back-up operation. For example, at 400ºC, the powerconsumption for such a sensor can be as high as 200mW in DC mode.
Another technique for reducing thermal loss is described in US PatentNo. 5,545,300. This patent describes using a composite membrane comprisinga glass film formed over a silicon nitride film. The reduction in the powerconsumption with the described technique is limited due to the high thermalconductivity of the silicon nitride film (23Wm-1K-1) used in the compositemembrane. The power consumption of the device disclosed in this patent isclose to 110mW at 400ºC in DC mode, which is still too high for batteryoperation.
Since two different steps (deposition of silicon nitride film followed bydeposition of silicon oxide film) are required to realise the membrane, thistechnique also suffers from the cost disadvantage mentioned above of havingseveral fabrication steps. A further disadvantage of the process described inthis patent is that as the silicon nitride layer is deposited on top of the siliconsubstrate, such a process step can create dislocations on the silicon surfacewhich is not compatible with integrated circuit (IC) technology. In other words,with such a process, it would not be possible to integrate the control chip on thesame substrate as the sensor device.
An article entitled 'Reduction of heat loss of silicon membranes by theuse of trench-etching techniques' by J. Werno, R. Kersjes, W. Mokwa and H.Vogt, and published on pages 578-581 of Sensors and Actuators A, 41-42(1994), describes a solution to improve the thermal insulation of single crystalsilicon membranes by means of oxide-filled trenches. The power consumptionof this technique is 230mW at 400°C in DC mode, which is too high for batteryoperation. In addition, the described trench-etching technique employs threesuccessive process steps (SIMOX/epitaxy/oxide-filled trenches) and is thus anexpensive technique to use with respect to the manufacturing costs.
There is therefore a need to provide an improved electronic device whichcan be operated at low power and a method of forming such an electronicdevice.
Summary of the Invention
In accordance with a first aspect of the present invention there isprovided an electronic device as recited in claim 1 of the accompanying claims.
In accordance with a second aspect of the present invention there isprovided a method of forming an electronic device as recited in claim 5 of theaccompanying claims.
Brief Description of the Drawings
An electronic device and a method for forming an electronic device inaccordance with the present invention will now be described, by way of exampleonly, with reference to the accompanying drawings in which:
  • FIGs. 1-9 show simplified schematic cross-sectional diagrams of aportion of an electronic device in accordance with the present invention duringvarious stages of fabrication; and
  • FIG. 10 shows a graph of power consumption as a function oftemperature for different types of membranes.
  • Detailed Description of the Preferred Embodiment
    In the following description, the invention will be described in relation to achemical sensor device. It will however be appreciated that the presentinvention may apply to any other electronic devices, such as thermal sensors,calorimetric sensors, pressure sensors, microphones, inkjet sensors,micropumps, and microsystems, which use a membrane to support the activeregion of the electronic device over a cavity in the bulk substrate.
    A method for forming a chemical sensor device in accordance with apreferred embodiment of the present invention will now be described withreference to FIGs. 1-9 of the drawings which are simplified schematic cross-sectionaldiagrams of a portion of the chemical sensor device during variousstages of fabrication. Although in the following description the semiconductorsubstrate, layers and regions will be described as having certain conductivitytypes and being comprised of certain material, this is for illustrative purposes only. It is not intended that the invention be limited to the specific conductivitytypes nor the specific materials referred to herein.
    Referring firstly to FIG. 1, asemiconductor substrate 2, preferably asilicon <100> substrate, is provided. Thesemiconductor substrate 2 has afirstsurface 4 and asecond surface 6, which is opposite thefirst surface 4. Adielectric layer 8 of an oxy-nitride material is formed oversemiconductorsubstrate 2 on thefirst surface 4, see FIG. 2. Thedielectric layer 8 has athickness 10 in therange 30 nanometres to 3 micrometers.
    In the preferred embodiment, thedielectric layer 8 is formed of a siliconoxy-nitride material having a composition SiOxNy. The composition (i.e. thevalues of x and y) is selected so that thedielectric layer 8 has good mechanicalproperties and low thermal conductivity in the range 1-30 Wm-1K-1. (preferably5 Wm-1K-1). Adielectric layer 8 having good mechanical properties ensures highmanufacturing yield of the device (up to 100%).
    The mechanical properties of thedielectric layer 8 depend upon theYoung's Modulus of the silicon oxy-nitride material, which forms thedielectriclayer 8, and the thermal expansion of the silicon oxy-nitride material. Thecomposition of the silicon oxy-nitride material is selected so that the thermalexpansion of the material is substantially equal to that of the substratematerial. In the preferred embodiment which has a silicon substrate, thecomposition is chosen so that the thermal expansion of the silicon oxy-nitridematerial is substantially equal to the thermal expansion of silicon (that is, 2.5X 10-6/ºC). This ensures that thedielectric layer 8 has a low residual stresslevel.
    The composition of the silicon oxy-nitride material is also selected sothat the Young's Modulus is close to that of the substrate material. Sincesilicon has a Young's Modulus of 170 GPa, the silicon oxy-nitride material isarranged to have a Young's Modulus in the range 100-180 GPa.
    Thedielectric layer 8 can be formed by Plasma Enhanced ChemicalVapour Deposition (PECVD) or Chemical Vapour Deposition (CVD). PECVDis preferred because it is easier to control the composition of the oxy-nitridematerial by adjusting the pressure and power of the plasma and hence the oxy-nitridedielectric layer 8 can be optimised both for low thermal conductivity andfor low stress.
    In the preferred embodiment, a mixture of silane, ammonia, nitrous oxideand nitrogen in a 0.17:0.14:0.14.0.55 ratio respectively is used in a PECVDprocess to provide adielectric layer 8 having a composition SiOxNy, where x =0.89, and y = 0.74. The PECVD process is carried out in a CVD 5000 chambersupplied by Applied Materials Inc., which chamber is heated to a temperatureof 400ºC. The plasma pressure is 600 Pa (4.5 Torr) and the plasma power is 325 W.
    Referring now also to FIG. 3, asilicon oxide layer 12 is formed on thesecond surface 6 of thesemiconductor substrate 2. Thesilicon oxide layer 12can be formed by thermal oxidation of the silicon substrate or by PECVD or byCVD. Thermal oxidation is preferred because during the oxidation of the siliconsubstrate, thedielectric layer 8 is annealed at the same time.
    A conductive layer is formed over thedielectric layer 8. The conductivelayer is then patterned and etched to leave aportion 14 of the conductive layerwhich forms aheater 14 of the chemical sensor device, see FIG. 4. Theconductive layer comprises a polysilicon layer or a metal layer having goodconductivity: the resistivity is in therange 10-6 ohm.cm to 10-3 ohm.cm. Thethickness 16 of theconductive layer 14 is between 30 nanometres and 3micrometres.
    In FIG. 5, amasking layer 18 is formed over thesilicon oxide layer 12 onthe backside of thesemiconductor substrate 2. Thethickness 20 of themasking layer 18 is between 30 nanometres and 3 micrometres. In thepreferred embodiment, a silicon nitride masking layer is PECVD deposited onthesilicon oxide layer 12 using the same equipment used for PECVD depositionof thedielectric layer 8. Thesilicon oxide layer 12 is required since the siliconnitride masking layer 18 has poor adherence to thesilicon substrate 2. Themasking layer 18 is used as a backside bard mask during backsidemicromachining of thebulk silicon substrate 2. Alternatively, a silicon oxy-nitridelayer could be used as themasking layer 18 due to the very low etchrate of silicon oxy-nitride in potassium hydroxide solution, which solution is usedto etch thesemiconductor substrate 2.
    A first insulatinglayer 22 is then deposited over thedielectric layer 8and theportion 14 of the conductive layer. In the preferred embodiment, thefirst insulatinglayer 22 comprises a silicon dioxide layer, which is deposited onthedielectric layer 8 by PECVD or a Low Pressure Chemical Vapour Deposition LPCVD. The first insulatinglayer 22 is patterned and etched toformcontact openings 24 extending to the conductive layer (FIG. 6).
    In FIG. 7, themasking layer 18 is patterned and then themasking layer18 and thesilicon oxide layer 12 are etched to form anopening 26 extending tothesecond surface 6 of thesemiconductor substrate 2. Theopening 26 definesthe area for etching thesemiconductor substrate 2.
    Asensitive layer 30 is then formed on a portion of the first insulatinglayer 22 so that it overlies the heater 14 (FIG. 8). Thesensitive layer 30 isformed by first depositing (by sputtering, evaporating, CVD or spin-on) a layerof material which is sensitive to the chemical species to be sensed by thesensor device over the whole of the device and then using patterning to removeportions of the layer to leave thesensitive layer 30. In the preferredembodiment, the sensitive material is a metal oxide and a standard lift-offtechnique is used. Polymeric sensing materials may also be used.
    Electrical contact is then made to theheater 14 and thesensitive layer30. Metallisation, such as chromium/titanium/platinum metallisation, isformed over the wafer by evaporation. The metallisation is then patterned bylift-off or etching to leave heater metal conductors 28 (FIG. 8) and sensitivelayer metal conductors (not shown).
    In order to improve thermal isolation of the active region of the chemicalsensor device, which region includes thesensitive layer 30 and theheater 14,thesemiconductor substrate 2 is etched or bulk-micromachined through theopening 26 to form acavity 32 which extends from thesecond surface 6 to thefirst surface 4 of thesemiconductor substrate 2 as shown in FIG. 9. Thesingledielectric layer 8 of oxy-nitride material forms the membrane of the chemicalsensor device in accordance with the present invention, which membraneextends at least across thecavity 32 and supports the active region of thechemical sensor device.
    The bulk-micromachining process is an anisotropic etch process. In thepreferred embodiment, a wet etch solution comprising potassium hydroxide(KOH) is used to remove the bulk of thesilicon substrate 2. Since oxy-nitridematerial has a very low etch rate in KOH (0.04 micrometres per hour), thedielectric layer 8 acts as an etch stop layer. Table 1 below gives data on theKOH mechanical yield and etch rate at 90ºC for different kinds of membranes.
    Membrane MaterialKOH Yield (%)KOH Etch Rate (µm/h)
    Oxide200.25
    Oxy-Nitride1000.04
    Nitride/Oxide950.02
    TrenchesN/A0.25
    P+ Silicon10015
    This very low etch rate means that the thickness of thedielectricmembrane 8 can be accurately controlled, and hence the same powerconsumption of the sensor device can be controlled, over a wafer, wafer towafer and lot to lot. As can be seen from the etch rates given in Table 1, this isnot the case with a P+ silicon layer which forms the membrane in the abovedescribed French Patent Application No. FR-A-2615287.
    Table 1 also shows the mechanical yield for membranes of differenttypes of material. An oxy-nitride membrane deposited by PECVD inaccordance with the present invention, as can be seen from Table 1, has goodmechanical properties.
    In the preferred embodiment described above, a portion of the siliconsubstrate is removed by backside micromachining using a wet etch process.Other techniques for removing the silicon substrate so as to leave a membraneover a cavity may also be used. For example, the silicon substrate may besurface micromachined using a wet etch process (on first surface 4), or thesilicon substrate may be backside or surface micromachined using a dry etchprocess, such as plasma etching, or a direct wafer bonding technique may beused. For the later technique, two wafers are bonded together and then onewafer is micromachined to provide the membrane.
    The oxy-nitride membrane 8 of the present invention provides low heatconduction after bulk substrate removal and also acts as an insulating layerbetween the heater and the substrate. The effectiveness of the thermal isolation provided by the membrane is determined by the thermal conductivityof the PECVD oxy-nitride membrane, which mainly depends on thecomposition of the membrane.
    FIG. 10 shows a graph of the power consumption as a function oftemperature for different types of membrane. As shown bycurve 40, the oxy-nitridemembrane in accordance with the present invention meets the lowpower requirements for battery operation across a wide temperature range.
    In summary, the present invention provides a device having amembrane to support the active region of the device comprising a singledielectric layer of oxy-nitride material having low thermal conductivity (i.e. lowpower consumption), low stress level, very low etch rate in KOH and which onlyrequires a single process step. The invention therefore provides a membranewhich can support low power operation, such as battery back-up, and which issimple and not expensive to manufacture.

    Claims (11)

    1. An electronic device comprising:
      a semiconductor substrate (2) formed of a semiconductor material andhaving a cavity (32) extending into the substrate;
      a membrane (8) formed over the semiconductor substrate so as to extendacross the cavity in the semiconductor substrate; and
      an active region (14, 22, 30) supported by the membrane (8) andpositioned adjacent the cavity (32),
      the electronic device beingcharacterized in that the membrane (8)comprises a single dielectric layer (8) formed of a silicon oxy-nitride materialhaving a composition SiOxNy, wherein x, and y are selected such that the siliconoxy-nitride material has a Young's Modulus substantially the same as theYoung's Modulus of the substrate semiconductor material, a thermal expansionsubstantially the same as the substrate semiconductor material and a thermalconductivity in the range 1-30 Wm-1K-1.
    2. An electronic device according to claim 1 wherein the oxy-nitride materialhas a composition SiOxNy, where x = 0.89, and y = 0.74.
    3. An electronic device according to any preceding claim wherein theelectronic device comprises a semiconductor sensor device and the active regioncomprises:
      a conductive layer (14) formed over the membrane;
      an insulating layer (22) formed over the conductive layer; and
      a sensitive layer (30) formed over the insulating layer.
    4. An electronic device according to any preceding claim wherein thesemiconductor substrate has a first surface (4) and a second surface (6) andwherein the cavity (32) extends through the substrate between the secondsurface (6) and the first surface (4).
    5. A method for forming a membrane for supporting an active region (14, 22,30) of an electronic device, the method comprising the steps of:
      providing a semiconductor substrate (2) formed of a semiconductormaterial;
      forming a membrane (8) over the semiconductor substrate;
      forming the active region of the electronic device over the single dielectriclayer (8); and
      removing a portion of the semiconductor substrate so as to provide acavity (32) in the substrate, the single dielectric layer (8) extending across thecavity (32), the method beingcharacterized in thatthe membrane (8) comprises asingle dielectric layer of a silicon oxy-nitride material having a compositionSiOxNy, wherein x, and y are selected such that the silicon oxy-nitride materialhas a Young's Modulus substantially the same as the Young's Modulus of thesubstrate semiconductor material, a thermal expansion substantially the same asthe substrate semiconductor material and a thermal conductivity in the range 1-30Wm-1K-1.
    6. A method according to claim 5 wherein the semiconductor substrate has afirst surface (4) and a second surface (6), wherein the step of forming themembrane (8) comprises forming the membrane over the first surface of thesemiconductor substrate and wherein the step of removing a portion of thesemiconductor substrate comprises the steps of:
      forming a masking layer (18) over the second surface (6) of thesemiconductor substrate after forming the membrane;
      removing a portion of the masking layer so as to provide an opening (26)extending through the masking layer to the second surface; and
      etching the semiconductor substrate through the opening so as to providethe cavity (32) extending between the second surface and the membrane.
    7. A method according to claim 6 wherein the etching step comprises wetetching the semiconductor substrate with a solution comprising potassiumhydroxide.
    8. A method according to claim 6 or 7 wherein the semiconductor substratecomprises a silicon substrate and the masking layer comprises a silicon oxidelayer over the second surface and a silicon nitride layer over the silicon oxidelayer.
    9. A method according to claim 5, 6, 7, or 8 wherein the forming a membranestep comprises depositing a single dielectric layer of a silicon oxy-nitride materialson the semiconductor substrate.
    10. A method according to claim 5, 6, 7, 8, or 9 wherein the oxy-nitridematerial has a composition SiOxNy, where x = 0.89, and y = 0.74.
    11. A method according to claim 5, 6, 7, 8, 9 or 10 wherein the electronicdevice is a semiconductor sensor device, and the method further comprises thesteps of:
      forming a conductive layer (14) on a portion of the single dielectric layer(8);
      forming a first insulating layer (22) over the single dielectric layer (8) andthe conductive layer (14);
      removing portions of the first insulating layer (22) to form contact openings(24) extending to the conductive layer (14);
      forming a sensitive layer (30) over a portion of the first insulating layer (22)such that the sensitive layer extends over the conductive layer but not over thecontact openings (24); and
      forming electrical contacts to the conductive layer and the sensitive layer.
    EP97401796A1997-07-251997-07-25Electronic device and method for forming a membrane for an electronic deviceExpired - LifetimeEP0893827B1 (en)

    Priority Applications (6)

    Application NumberPriority DateFiling DateTitle
    DE69728976TDE69728976T2 (en)1997-07-251997-07-25 Electronic device and method for making a membrane therefor
    EP97401796AEP0893827B1 (en)1997-07-251997-07-25Electronic device and method for forming a membrane for an electronic device
    US09/120,755US6022754A (en)1997-07-251998-07-22Electronic device and method for forming a membrane for an electronic device
    KR1019980029781AKR100578259B1 (en)1997-07-251998-07-24 Electronic device and film formation method for electronic device
    CN98116373ACN1213081A (en)1997-07-251998-07-24Electronic device and method for forming membrane for electronic device
    JP22525298AJP4271751B2 (en)1997-07-251998-07-24 Electronic device and method for forming a membrane for an electronic device

    Applications Claiming Priority (2)

    Application NumberPriority DateFiling DateTitle
    EP97401796AEP0893827B1 (en)1997-07-251997-07-25Electronic device and method for forming a membrane for an electronic device
    US09/120,755US6022754A (en)1997-07-251998-07-22Electronic device and method for forming a membrane for an electronic device

    Publications (2)

    Publication NumberPublication Date
    EP0893827A1 EP0893827A1 (en)1999-01-27
    EP0893827B1true EP0893827B1 (en)2004-05-06

    Family

    ID=26147864

    Family Applications (1)

    Application NumberTitlePriority DateFiling Date
    EP97401796AExpired - LifetimeEP0893827B1 (en)1997-07-251997-07-25Electronic device and method for forming a membrane for an electronic device

    Country Status (4)

    CountryLink
    US (1)US6022754A (en)
    EP (1)EP0893827B1 (en)
    JP (1)JP4271751B2 (en)
    CN (1)CN1213081A (en)

    Families Citing this family (13)

    * Cited by examiner, † Cited by third party
    Publication numberPriority datePublication dateAssigneeTitle
    DE19817311B4 (en)*1998-04-182007-03-22Robert Bosch Gmbh Manufacturing method for micromechanical component
    US6387724B1 (en)*1999-02-262002-05-14Dynamics Research CorporationMethod of fabricating silicon-on-insulator sensor having silicon oxide sensing surface
    JP4513161B2 (en)*2000-03-312010-07-28東亞合成株式会社 Gas sensor manufacturing method and gas sensor
    US6468897B1 (en)*2001-05-232002-10-22Macronix International Co., Ltd.Method of forming damascene structure
    EP2092833B1 (en)2006-12-142012-10-17ITO EN, Ltd.Process for producing tea drink
    CN102354659B (en)*2011-11-022016-05-11上海华虹宏力半导体制造有限公司Mask nucleation removing method and selective epitaxial growth method
    US9354197B2 (en)*2013-04-252016-05-31Wisenstech Ltd.Micromachined oxygen sensor and method of making the same
    KR101616959B1 (en)*2013-07-022016-04-29전자부품연구원Fet ion detector and system by using the same
    KR102142885B1 (en)*2013-10-142020-08-10한국전자통신연구원Method for manufacturing array-type antenna-coupled detector
    CN103606565B (en)*2013-11-272016-05-11苏州科技学院The manufacturing process of pressure sensor sensing element
    US11513091B2 (en)*2016-05-272022-11-29Carrier CorporationGas detection device and method of manufacturing the same
    FR3079616B1 (en)2018-03-302021-02-12Soitec Silicon On Insulator MICRO-SENSOR FOR DETECTING CHEMICAL SPECIES AND ASSOCIATED MANUFACTURING PROCESS
    CN110797255B (en)*2019-10-142022-10-28长江存储科技有限责任公司 Thin film stack structure, three-dimensional memory and preparation method thereof

    Family Cites Families (4)

    * Cited by examiner, † Cited by third party
    Publication numberPriority datePublication dateAssigneeTitle
    US4706493A (en)*1985-12-131987-11-17General Motors CorporationSemiconductor gas sensor having thermally isolated site
    FR2615287B1 (en)*1987-05-121989-10-06Suisse Electronique Microtech MICRO SENSOR WITH INTEGRATED TECHNOLOGY FOR DETECTING THE PRESENCE OF CERTAIN GASES
    JP2582343B2 (en)*1993-12-041997-02-19エルジー電子株式会社 Low power consumption thin film gas sensor and method of manufacturing the same
    US5635628A (en)*1995-05-191997-06-03Siemens AktiengesellschaftMethod for detecting methane in a gas mixture

    Also Published As

    Publication numberPublication date
    US6022754A (en)2000-02-08
    JP4271751B2 (en)2009-06-03
    CN1213081A (en)1999-04-07
    JPH11166866A (en)1999-06-22
    EP0893827A1 (en)1999-01-27

    Similar Documents

    PublicationPublication DateTitle
    EP1417151B1 (en)Method for the fabrication of suspended porous silicon microstructures and application in gas sensors
    EP0893827B1 (en)Electronic device and method for forming a membrane for an electronic device
    US5286671A (en)Fusion bonding technique for use in fabricating semiconductor devices
    US7183637B2 (en)Microelectronic mechanical system and methods
    EP0822578B1 (en)Method of fabricating integrated semiconductor devices comprising a chemoresistive gas microsensor
    EP0340022A1 (en)Mechanical sensor for high temperature environments
    US6619133B1 (en)Semiconductor pressure sensor and its manufacturing method
    US7514285B2 (en)Isolation scheme for reducing film stress in a MEMS device
    US6689669B2 (en)High temperature sensors utilizing doping controlled, dielectrically isolated beta silicon carbide (SiC) sensing elements on a specifically selected high temperature force collecting membrane
    JP3418548B2 (en) Circuit board and method of manufacturing the same
    JP2003501657A (en) Low power consumption sensor
    US7989894B2 (en)Fusion bonding process and structure for fabricating silicon-on-insulation (SOI) semiconductor devices
    EP0341964B1 (en)Silicon micro sensor and manufacturing method therefor
    KR20080098990A (en) Pressure sensor manufacturing method and structure
    KR100578259B1 (en) Electronic device and film formation method for electronic device
    JP4032476B2 (en) Manufacturing method of micro device
    US5948361A (en)Chemical sensor and method of making same
    JPH11126910A (en) Method of manufacturing semiconductor substrate for pressure sensor
    US20190237358A1 (en)Methods of fabricating silicon-on-insulator (soi) semiconductor devices using blanket fusion bonding
    WO2003090281A2 (en)Single crystal silicon membranes for microelectromechanical applications
    EP1193752A1 (en)Method to form a localized silicon-on-insulator structure
    EP1846321A1 (en)Method of fabricating a silicon-on-insulator structure
    WO2006132161A1 (en)Integrated device
    JPH10107296A (en)Semiconductor device and fabrication thereof
    JP2004090102A (en) Method of forming semiconductor thin film on insulating substrate

    Legal Events

    DateCodeTitleDescription
    PUAIPublic reference made under article 153(3) epc to a published international application that has entered the european phase

    Free format text:ORIGINAL CODE: 0009012

    AKDesignated contracting states

    Kind code of ref document:A1

    Designated state(s):DE FR GB

    AKXDesignation fees paid

    Free format text:DE FR GB

    17PRequest for examination filed

    Effective date:19991117

    17QFirst examination report despatched

    Effective date:20010914

    GRAPDespatch of communication of intention to grant a patent

    Free format text:ORIGINAL CODE: EPIDOSNIGR1

    GRASGrant fee paid

    Free format text:ORIGINAL CODE: EPIDOSNIGR3

    GRAA(expected) grant

    Free format text:ORIGINAL CODE: 0009210

    AKDesignated contracting states

    Kind code of ref document:B1

    Designated state(s):DE FR GB

    REGReference to a national code

    Ref country code:GB

    Ref legal event code:FG4D

    REFCorresponds to:

    Ref document number:69728976

    Country of ref document:DE

    Date of ref document:20040609

    Kind code of ref document:P

    ETFr: translation filed
    PLBENo opposition filed within time limit

    Free format text:ORIGINAL CODE: 0009261

    STAAInformation on the status of an ep patent application or granted ep patent

    Free format text:STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

    26NNo opposition filed

    Effective date:20050208

    PGFPAnnual fee paid to national office [announced via postgrant information from national office to epo]

    Ref country code:GB

    Payment date:20060614

    Year of fee payment:10

    PGFPAnnual fee paid to national office [announced via postgrant information from national office to epo]

    Ref country code:FR

    Payment date:20060705

    Year of fee payment:10

    REGReference to a national code

    Ref country code:GB

    Ref legal event code:732E

    PGFPAnnual fee paid to national office [announced via postgrant information from national office to epo]

    Ref country code:DE

    Payment date:20060731

    Year of fee payment:10

    REGReference to a national code

    Ref country code:FR

    Ref legal event code:TP

    GBPCGb: european patent ceased through non-payment of renewal fee

    Effective date:20070725

    PG25Lapsed in a contracting state [announced via postgrant information from national office to epo]

    Ref country code:DE

    Free format text:LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

    Effective date:20080201

    PG25Lapsed in a contracting state [announced via postgrant information from national office to epo]

    Ref country code:GB

    Free format text:LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

    Effective date:20070725

    REGReference to a national code

    Ref country code:FR

    Ref legal event code:ST

    Effective date:20080331

    PG25Lapsed in a contracting state [announced via postgrant information from national office to epo]

    Ref country code:FR

    Free format text:LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

    Effective date:20070731


    [8]ページ先頭

    ©2009-2025 Movatter.jp