EP0520838B1 - SCSI interface employing bus extender and auxiliary bus - Google Patents

Description

Field of the Invention

The invention relates to computer systems, and moreparticularly to input/output interfaces of the type used toconnect peripheral devices to a digital computer.

Background of the Invention

Generally-recognized Small Computer System Interface("SCSI") standards of the American National Standards Institute(ANSI X3.131-1986) specify the electrical, mechanical andlogical characteristics of an input/output (I/O) bus interfacefor coupling physically small computers with each other andwith peripheral devices, for example, disk drives, tape drives,printers, compact disk read-only memories ("CD-ROM's"), andscanners.

Essentially, the SCSI standards specify an I/O bus,commonly called a "SCSI bus." The bus does not require aseparate bus controller; instead, a SCSI bus protocol specifiedby the standards is implemented distributively within centralprocessing units ("CPU's") or, often, host adapters ofcomputers on the bus, and by controllers of peripheral deviceson the bus.

The SCSI bus protocol facilitates information transferbetween devices connected to the bus. The bus protocolincludes an addressing scheme for identifying the devices, andspecifies connection-control signals for arbitrating forcontrol of the SCSI bus and establishing a communication linkwith the intended recipient or target of an informationtransfer on the bus. Where the host computer is the initiatorand a peripheral device on the SCSI bus is the target, thislatter process is known in the standards as SELECTION. Incertain situations, an information transfer may be interrupted,and, at a later time, the target can reselect the host computer to continue the transfer. This process is called RESELECTION.

Since, generally speaking, any peripheral devices having acontroller complying with the SCSI standards can be connectedto a SCSI bus, the standards have lead to a proliferation ofthe types and sources of commercially-available peripheraldevices. Moreover, computer systems complying with thestandards can be configured and reconfigured with ease by,e.g., end users, to meet specific computing needs andincorporate evolving peripheral device technologies.

The SCSI standards are available from the AmericanNational Standards Institute, Inc., New York, New York, USA,and are incorporated herein by reference.

While conventionally-implemented SCSI bus interfaces aresuitable for their intended purposes, they generally arelimited to supporting no more than seven peripheral devices.Heretofore, this limit on the number of peripheral devices hasnot presented a significant drawback. As systems employingSCSI buses have expanded and become more powerful, however, theneed for more storage capacity and the ability to connect tomore peripheral devices has grown. For instance, the need formore storage is often particularly acute in multi-user computersystems.

A known approach to increasing the number of SCSIperipheral devices connectable to a SCSI bus employs multipleSCSI ports on the computer, each connected to a separate SCSIbus. Unfortunately, as computers have shrunk in physical size,the space on the computer housing available for such ports hasbecome increasingly limited. Indeed, many computermanufacturers have reduced the number of ports provided on thehousing, and do not provide multiple SCSI ports in theirstandard computer configurations. In addition, this approachoften requires additional host adapters to control theinformation transfer in accordance with the standards.

Another known approach is disclosed in JP-A-63310052 which describes asmall computer system interface (SCSI), peripheral controllers and a connection controller connected to the SCSI bus. Responsive to identificationinformation from a host controller, the connection controller transfers certaindata from peripheral controllers (connected to an expanded SCSI bus) to theSCSI bus. Proper identifications are generated for peripheral equipmentcontrollers and for the requested data transfer.

Alternatively, "juke box" arrangements are known, in which a controllersupports a plurality of peripheral devices. Unfortunately, such controllers arededicated units for supporting specific types of peripheral devices, and can notbe used with other types of devices. For example, a known type of juke boxsupports only tape drives.

Accordingly, it would be desirable to provide an improved, general-purposeinterface that can support a greater number of peripheral devices whilemaintaining reliable connectivity with a host computer. Desirably, also, theimproved interface should operate in accordance with SCSI standards.

According to the present invention there is provided a bus extender asspecified inclaim 1.

Preferred features of the bus extender ofclaim 1 are specified inclaims 2to 7.

According to another aspect of this invention there is provided a methodof operating a bus extender as specified inclaim 8.

A preferred feature of the method ofclaim 8 is specified in claim 9.

The invention resides in a bus interface that employs abus extender for connecting an auxiliary bus to a single porton a main bus in such a way as to interconnect one or more hostcomputers on the main bus to one or more peripheral devices onthe auxiliary bus. Since the interface can comply with SCSIstandards, any of a variety of types of commercially-availableperipheral devices having controllers complying with thosestandards can be supported on the auxiliary bus.

The bus extender employs a transceiver coupled to the mainSCSI bus, another coupled to the auxiliary bus, and signaltransfer and logic circuitry passing signals between andcontrolling the operation of the transceivers. The circuitryalso performs all address translation necessary for inter-buscommunication.

In particular, the transfer and logic circuitry (i)receives first connection-control signals from one of thebuses, which signals have fields of data designating theextender as the addressee and designating the source of thesignals; (ii) identifies the ultimate target for the inter-buscommunication based on data contained in the first connection-controlsignals, or, depending on the direction of thecommunication, stored in a latch within the extender itself;(iii) generates second connection-control signals includingfields of data designating the extender as the source of the communication and the ultimate target; and (iv) provides theselatter signals to the appropriate transceiver for transmissionover the other bus.

A preferred embodiment of the bus extender takes advantageof dual-tier, hierarchal addressing used in the SCSI standardsto direct messages to the designated devices on the other bus.In the addressing scheme employed in the invention, each deviceconnected to either the main or auxiliary bus is identified bya unique identification code ("ID"). In addition, each deviceID is associated with an auxiliary identification or address-descriptor,which in the SCSI standards is referred to as a LUNor logical unit number.

For purposes of communication, the bus extender has an IDon both the main and auxiliary buses. Whenever connection-controlsignals on the main or auxiliary buses carry theextender's respective ID as a destination ID, the extenderresponds and attempts to establish the communication linknecessary to transfer information to the ultimate recipient onthe other bus.

In order to pass messages received over the main bus froma host computer, i.e., during SELECTION, the extender firstconverts the LUN field data of the connection-control signalsreceived over the main bus to the ID of the target on theauxiliary bus, and supplies the extender's own auxiliary-bus IDas the initiator ID in the auxiliary-bus connection-controlsignals. Then, the extender attempts to establish acommunication link with the target device via connection-controlsignals on the auxiliary bus using the target IDgenerated by the extender.

Analogously, in order to-continue an earlier, discontinuedtransfer of messages from a peripheral device on the auxiliarybus to a host computer that initiated the earlier transfer,i.e., RESELECTION, the extender converts the device's IDcontained in auxiliary-bus connection-control signals into LUNfield data, supplies the extender's own main-bus ID as the target attempting RESELECT, and uses the ID of the initiator ofthe earlier SELECTION, which the extender has stored (e.g., ina suitable latch) for such purposes.

Once the communication link has been established betweenthe initiator and target for communication in either direction,the extender transfers message data signals (e.g., COMMAND,STATUS, DATA-IN, and DATA-OUT) directly and withoutmodification between the main and auxiliary buses. Thus, as ageneral rule, the extender intervenes only during theestablishment of the communication link and not during theactual transfer of information. This limited role for theextender permits the extender to be economically designed andproduced using, e.g., application specific integratedcircuitry, and without the need for a microcomputer within theextender.

Moreover, the interface of the invention provides computersystem designers with improved flexibility in the type as wellas the number of peripheral devices connectable to a hostcomputer. For instance, devices having differentialtransceivers can be attached to the main bus, and deviceshaving single-ended transceivers can be attached to theauxiliary bus, or vice versa, and these diverse devices cancommunicate by providing the extender with the appropriate typeof transceivers.

The bus extender connects up to seven SCSI peripherals tothe main bus. Since SCSI standards permit as many as sevendevices in addition to a host computer to be inter-connected bya main bus, and since the invention permits each of the sevendevices to be a bus extender, the invention can be practiced toconnect as many as 49 peripheral devices to the host computer,a significant increase over the seven peripheral devicesgenerally connectable to a host computer under the standards.

The invention can be practiced also in conjunction withvarious types of bus interfaces other than SCSI interfaces,provided such other interfaces use a parallel bus architecture and connection-control signals providing both address-ID andaddress-descriptor fields, which are sent, e.g., over paralleldata lines of the bus.

Brief Description of the Drawings

For a fuller understanding of the nature and objects ofthe invention, reference should be made to the followingdetailed description, taken in conjunction with theaccompanying drawings, in which:

FIGURE 1 is a block diagram of a computer system having aSCSI interface including main and auxiliary buses and a busextender in accordance with the present invention;

FIGURE 2 is a block diagram of a computer system having aSCSI interface including a main bus connected to a plurality ofauxiliary buses by means of bus extenders in accordance with analternative practice of the invention;

FIGURE 3 is a block diagram of the bus extender of FIGURE1;

FIGURE 4 is a flow chart depicting operation of the busextender of FIGURE 3 during information transfer from the hostcomputer on the main bus to one of the peripheral devices onthe auxiliary bus; and

FIGURES 5 and 6 are diagrammatic representations of themodification of connection-control signals by the extender ofFIGURE 1 during SELECTION and RESELECTION, respectively;

FIGURES 7 and 8 are signal sequence diagrams depictingillustrative operations of the computer system of FIGURE 1during SELECTION and RESELECTION, respectively.

Detailed Description of an Illustrative Embodiment

FIGURE 1 shows acomputer system 10 in accordance with anillustrative embodiment of the invention as including first andsecond host computers 14, 16 interconnected by aSCSI interface20 with first and second sets of respectively six and sevenSCSI-conformingperipheral devices 22, 24. TheSCSI interface 20 includes amain bus 26 to which the first andsecond hostcomputers 14, 16 and the peripheral devices 22 (called the"main-bus peripheral devices") are connected, anauxiliary bus28 to which peripheral devices 24 (called the "auxiliary-busperipheral devices") are connected, and abus extender 30 forinterconnecting the main andauxiliary buses 26, 28. Eachhostcomputer 14, 16 is connected to themain bus 26 via aconventional SCSI port 14A, or, if necessary, aconventionalhost adapter 16A incorporating such a port.

Theinterface 20 is responsible for transferring digitalsignals including message signals from thehost computers 14,16 to the auxiliary-busperipheral devices 24, or in theopposite direction, that is, from the auxiliary-busperipheraldevices 24 to thehost computers 14, 16.

Eachcomputer 14, 16 and each main-busperipheral device22 has a unique address on themain bus 26 specified by anaddress-identification code ("ID"), designated in the drawingsas ID_0 through ID_7. Analogously, each of the auxiliary-busperipheral devices 24 has a unique address on theauxiliary bus28 specified as ID_0 through ID_6.

Thebus extender 30 occupies a unique address on each ofthe main andauxiliary buses 26, 28. For example, thebusextender 30 has a main bus ID_0 and an auxiliary bus ID_7. Thespecific assignment of address ID's can be varied by thoseskilled in the art, although priority during signal contentionon the buses as discussed below should be taken intoconsideration during ID assignment.

The particular configuration of thecomputer system 10 ofFIGURE 1 is for illustrative purposes only. Any combination ofcomputers and main-bus peripheral devices can be used inconjunction with the invention, as long as at least onecomputer is connected to themain bus 26. For instance, asingle computer and seven peripheral devices could be connectedto the main bus. Theauxiliary bus 28 can support onlyperipheral devices.

FIGURE 2 illustrates acomputer system 40 having yet adifferent configuration. (For convenience, the same referencenumbers will be used for analogous features in the drawings.)Themain bus 26 incomputer system 40 connects asingle hostcomputer 14 to sevenbus extenders 30A-30G, which connect tosevenauxiliary buses 28A-28G. Eachauxiliary bus 28 supportsseven auxiliary-busperipheral devices 24. With thisconfiguration, as many as 49 peripheral devices can beconnected to a single SCSI port of thehost computer 14.

Of significance, the peripheral devices connectable to thehost computer through the practice of the invention can becommercially available units. The peripheral devices need notbe specifically adapted or modified in terms of either hardwareor software for use in conjunction with the invention so longas they conform to the SCSI standards.

FIGURE 3 shows a block diagram of thebus extender 30. asincluding main-bus and auxiliary-bus transceivers 42, 44,transfer circuits 46, 48 for selectively passing signalsbetween the main-bus transceiver 42 and the auxiliary-bustransceiver 44, a storage device such aslatch 49 for storinginitiator ID's, and controllogic 50 for controlling theoperation of the other components of theextender 30. Theextender 30 also has a main-bus ID-input arrangement 52, suchas a group of switches, which permits a user to manually enter,and then store, a main-bus ID identifying theextender 30. Inaddition, theextender 30 has aclock 30A for providing timingsignals, and apower supply 30B.

Eachtransceiver 42, 44 has areceiver 56 for receivingsignals from the respective originatingbuses 26, 28, and adriver 58 for sending or asserting signals on therespectivetarget buses 28, 26. Thetransceivers 42, 44 can be eitherboth differential or both single-ended transceivers, or one canbe differential and the other single-ended, and, in any event,should conform with the type of signal lines on thebus 26, 28to which eachtransceiver 42, 44 is connected.

Eachtransfer circuit 46, 48 modifies certain signals,i.e., connection-control signals, received by thetransceivers44, 48, and passes other signals, i.e., message data signals,without modification. Eachtransfer circuit 46, 48 has ademultiplexer 62 ("DEMUX") for receiving the received signalsat a data input thereof from therespective transceiver 42, 44and, in response to a control signal at a control inputthereof, for passing the message data signals ontodirect datalines 64 connected to a first output of theDEMUX 62 andpassing the connection-control signals 65A, 65B to aconverter66 connected to a second output of theDEMUX 62. Thedirectdata lines 64 of thetransfer circuit 46, 48 directly couplethe message data signal passed by theDEMUX 62 to a multiplexer68 ("MUX") at a first data input thereof.

Theconverter 66 translates the ID and LUN field data ofthe connection-control signals 65A, 65B into appropriate ID andLUN field data for use on thedestination bus 28, 26, inconformance with the address specifications of, e.g., the SCSIstandards. Theconverter 66 then passes the generated ID andLUN field data to the connection-control signal generator 72,which forms connection-control signals 65C, 65D suitable foruse on thebus 28, 26 that is to receive the communication.The operation of theconverters 66 andsignal generators 72 ofthetransfer circuits 46, 48 will be described more fullybelow.

The connection-control signals 65C, 65D generated by thesignal generator 72 of thetransfer circuit 46, 48 are appliedto theMUX 68 at a second data input thereof. Responsive to acontrol signal 74B, 76B at a control input thereof, theMUX 68passes either the message data signals received over thedirectdata lines 64, the connection-control signals 65C, 65D, orsignals 74C, 76C generated by the control logic 50 (asdescribed hereinafter), to thedriver 58 of thetarget bus 28,26.

Thecontrol logic 50 includes first and secondcontrol logic modules 74, 76, which (i) monitor, over detectlines 78,signals received by thetransceivers 42, 44, and, in responsethereto, (ii) control the direction of thetransceivers 42, 44(i.e., control whether the transceivers are driving orreceiving signals) usingtransceiver control lines 82, (iii)control the operation of the DEMUX's 62 and the MUX's 68 byapplying thereto appropriate control signals 74A, 74B, and 76A,76B, and (iv) assertsignals 74C, 76C to third data inputs ofMUX's 68 to be sent over the target buses.

Thecontrol logic 50 controls the signals in accordancewith FIGURES 4-8, and is preferably implemented economicallythrough the use of application-specific integrated circuitry(ASIC), although thecontroller logic 50 can also constitute aprogrammable logic array or be made from discrete devices. Thetransfer circuits 46, 48 and thelatch 49 can also beimplemented using ASIC.

FIGURES 4 and 5 provide an overview of the operation oftheextender 30 during SELECTION-related phases, i.e., duringthe establishment of a communication link from thehostcomputer 14 to aperipheral device 24 on theauxiliary bus 28in accordance with the SCSI standards and the principles of theinvention.

In block 90, theextender 30 monitors the signals on themain bus 26 in order to detect those containing data indicatingthat theextender 30 is the designated recipient. In otherwords, theextender 30 checks the target fields of firstconnection-control signals being sent over themain bus 26 forthe extender's main-bus ID.

When such signals having the extender's main-bus ID areidentified, theextender 30 establishes a communication link,in block 92, with the initiator whose ID is also specified inthose signals. The initiator in this example ishost computer14.

Then, inblock 94, theextender 30 arbitrates for controlof theauxiliary bus 28, and also, in block 96, generates connection-control signals for theauxiliary bus 28 thatspecify theextender 30 as the initiator on that bus, andspecify the ultimate target on theauxiliary bus 28 as thetarget of the ensuing message.

More specifically, as depicted in FIGURE 5, first andsecond main-bus connection control signals 122, 124 arereceived from themain bus 26 by theextender 30, which usesthe data in these signals to generate auxiliary-bus first andsecond connection control signals 126, 128 to be sent over theauxiliary bus 28. The main-bus first connection-control signal122 has an initiator ID field providing the ID of thehostcomputer 14 that originated the communication, and a target IDfield that provides the extender's ID so as to identify theextender as the intended recipient on themain bus 26 of thecommunication. The main-bus second connection-control signals124 correspond, e.g., to IDENTIFY signals under the SCSIstandards, and include a LUN field, which, for purposes of theinvention, specifies the ultimate targetperipheral device 24on theauxiliary bus 28. (The IDENTIFY signals also cancontain other fields.) Thus, thehost computer 14 isresponsible for identifying both theextender 30 and theultimate recipient of the communication in the main-busconnection-control signals.

Theconverter 66 of thetransfer circuit 46 of theextender 30 translates the LUN field data of the received main-bussecond connection-control signal 124 into the auxiliary-busID of the ultimate target on theauxiliary bus 28 forincorporation into an auxiliary-bus first connection-controlsignal 126. Theconverter 66 ofcircuit 46 also initializesthe LUN field data to a predetermined value of, e.g., zero, forincorporation into an auxiliary-bus second connection-controlsignal 128.

Thesignal generator 72 of thetransfer circuit 46 formsthe auxiliary-bus first connection-control signal 126 byincorporating the ultimate target ID generated by theconverter 66 in that signal's target ID field, and the extender'sauxiliary-bus ID in that signal's initiator ID field. Thesignal generator 72 ofcircuit 46 also forms an auxiliary-bussecond connection-control signal 128 by incorporating theinitialized LUN value into that signal's LUN field, and thedata from the other fields of the main-bus second connection-controlsignal 124 into the other fields of the auxiliary-bussecond connection-control signal 128.

In addition, theextender 30 assures that the parity bitprovided by the SCSI standards is correct for the generatedIDENTIFY message. Specifically, theextender 30 modifies theparity bit 132 received from themain bus 26 based on whetherthe change in the value of the LUN field changed the parity forthe LUN field, i.e., from even to odd, or odd to even, andprovides the modifiedparity bit 134 to theauxiliary bus 28.Accordingly, theextender 30 changes the parity of the IDENTIFYmessage based solely on the LUN field data.

Moreover, theextender 30 stores the initiator ID field ofthe main-bus first connection-control signal 122 inlatch 49for use in case theperipheral device 24 elects to RESELECT thehost computer 14 at a later time following a discontinuation ofthe original communication. Latch 50A stores the ID so that itcan be accessed using the ID's of the targets seekingRESELECTION. This will be described more fully below.

With reference again to FIGURE 4, in block 106, theextender 30 sends the auxiliary-bus first connection-controlsignal on theauxiliary bus 28 to establish a communicationlink with the ultimate target. Once the link is established,theextender 30 sends auxiliary-bus second connection-controlsignal inblock 108, and the message data follows, pursuant toblock 110.

During RESELECTION following a discontinued communication,i.e., for transferring information from aperipheral device 24on theauxiliary bus 28 to thehost computer 14 that initiatedthe earlier communication, theextender 30 operates in an analogous way to that just described. However, as shown inFIGURE 6, there are some differences, as will be explained inthe following discussion.

During RESELECTION, theextender 30 receives an auxiliary-busfirst connection-control signal 126 from theauxiliary bus28, which signal has an initiator ID field providing theextender's auxiliary bus ID, and a target ID field providingthe auxiliary-bus ID of the peripheral device seeking toreestablish the communication. Theextender 30 also receivesan auxiliary-bus second connection-control signal 128 that hasan initialized LUN field (e.g., having a zero value).

Theconverter 66 oftransfer circuit 48 of theextender 30translates the LUN field data of the received auxiliary-bussecond connection-control signal 128 into a LUN valuecorresponding to the contents of the target ID field of theauxiliary-bus second connection-control signal 128, i.e., tothe auxiliary-bus ID of the peripheral device seekingRESELECTION.

Thesignal generator 72 of thetransfer circuit 46 formsthe main-bus first connection-control signal 122 by fetchingthe ID of the original initiator of the previously discontinuedcommunication fromlatch 49, and incorporating the fetched IDas that signal's initiator ID field, and incorporating theextender's auxiliary-bus ID in that signal's target ID field.Thesignal generator 72 ofcircuit 48 also forms a main-bussecond connection-control signal 124 by incorporating the LUNvalue generated byconverter 66 ofcircuit 48 into thatsignal's LUN field, and the data from the other fields of theauxiliary-bus second connection-control signal 128 into theother fields of main-bus second connection-control signal 124.

In addition, theextender 30 again assures that theparitybit 132 is correct for the generated IDENTIFY message.Specifically, theextender 30 modifies the parity bit receivedfrom theauxiliary bus 28 based on whether the change in thevalue of the LUN field changed the parity for the LUN field. Accordingly, as with respect to SELECTION, theextender 30changes the parity of the IDENTIFY message during RESELECTIONbased solely on the LUN field data, and provides the modifiedparity bit 134 to themain bus 26.

FIGURES 7 and 8 will form the basis of the following moredetailed discussion of the operation of thebus extender 30.These figures show signal sequence diagrams of SELECT withATTENTION and RESELECTION after DISCONNECT, respectively, andemploy positive logic (i.e., signals are asserted when theirvalues are DIGITAL high) to denote the state and timing ofdigital signals. The various lines comprising the buses aredenominated along the left margin of the drawings, with themain-bus lines shown in the top half (designated 7A, 8A) of thedrawings , and the auxiliary bus signals in the bottom half(designated 7B, 8B) of the drawings. Various phases of thesignaling process are listed along the top of the drawings.

With reference to FIGURE 7, during an initial period oftime, which is denoted as "free" at the top of the drawing,none of the lines are asserted, i.e., thebus 26 is quiet andavailable for communication.

To transfer messages, thehost computer 14 attempts togain control of themain bus 26 during what is called theARBITRATION phase by asserting the BUSY line ("bsy") at "a" inpart 7A of the drawing, and asserting the host computer's ownID on the data lines ("dbn") at "b." (In SCSI buses, thereare, e.g., eight data lines, one corresponding to each of theID's (i.e., ID_0-ID_7) that can be assigned to devices on thebus. Thus, for example, to assert ID_6, the sixth data line isdriven HIGH.)

If at the time thehost computer 14 is attempting tocontrol themain bus 26, any other device or devices arelikewise attempting to do so, the bus is deemed to be incontention. In that case, according to the SCSI standards, thecontending device with the highest ID is given priority. Thus,for example, if theextender 30 were also attempting to control themain bus 26, thecontrol logic 50 would assert BUSY and theextender's ID, i.e., ID_0, on the data lines. Since, thecomputer's ID_6 is higher than the extender's ID_0, theextender 30 would fall off themain bus 26, and thehostcomputer 14 would gain control of themain bus 26 by assertingthe SELECT line ("sel"). If there are no contenders for thebus, then thehost computer 14 simply can assert "sel," asshown at "c." This finishes the main-bus ARBITRATION phase.

Now, thehost computer 14 attempts to establish acommunication link with a target on themain bus 26 within whatis called the SELECTION phase by sending a first connectioncontrol signal over the data lines ("dbn") as shown at "d,"which signal gives both the host computer's own ID as theinitiator and the target's ID on themain bus 26.Consequently, two of the data lines are asserted -- the twocorresponding to the host computer and the target. Inaddition, the correct parity for the asserted data bits, i.e.,in this case, a HIGH value, is maintained on the data parityline ("dbp"). In other words, dbp is asserted at "e.".Moreover, another signal line, the I/O control line ("i/o"), isdeasserted to indicate SELECTION. (Assertion of the i/o lineindicates RESELECTION.) Afterwards, the initiator alsodeasserts BUSY at "f."

In order to illustrate the invention, we will assume thatthe target ID asserted during SELECT is that of thebusextender 30, e.g., ID_0, which means that thehost computer 14is attempting to communicate with one of the auxiliary-busperipheral devices 24. Accordingly, during SELECT, thecontrollogic 50 of theextender 30 identifies the target as ID_0, andverifies that SELECT is asserted and that BUSY is deasserted.In addition, thecontrol logic 50 verifies that the parity iscorrect, and that there are two, and only two, bits asserted onthe dbn lines.

Once theextender 30 has confirmed that it is the target,the extender accepts SELECTION by asserting BUSY on themain bus 26, as shown at point "g" in FIGURE 5. In response to theacceptance, thehost computer 14 deasserts SELECT at "h."

Another signal that plays a part during SELECTION isATTENTION ("atn"). With the start of SELECTION, the atn lineis either asserted or left deasserted. If asserted, as shownat point "i" in the drawing, the initiator is "selecting withattention," which informs the target that the initiator has amessage for transfer out, in which case the target goes into amessage-out phase after SELECTION and readies itself to receivea message, i.e., enables the receiver of the target'stransceiver. On the other hand, if SELECTION is notaccompanied by ATTENTION being asserted, i.e., the atn line isLOW, the target knows the initiator is inviting the target tocontrol flow of information. Therefore, the target will gointo, e.g., a message-in phase, in which the target will send amessage, and, accordingly, will enable its own driver.

For purposes of this discussion, the SELECTION is withATTENTION, and the status of the ATTENTION and MESSAGE lines isdetermined by thecontrol logic 50 of theextender 30.Therefore, theextender 30 prepares for a message-out phase, asis shown in the drawings. In the message-out phase, thebusextender 30 leaves the data lines deasserted since it isexpecting data from thehost computer 14 to be sent over thoselines. Furthermore, thecontrol logic 50 enables thereceiver56 of the main-bus transceiver 42 and thedriver 58 of theauxiliary-bus transceiver 44.

At this point in the discussion, we turn to two otherlines, called REQUEST ("req") and ACKNOWLEDGE ("ack"), whichcarry handshake signals. Thecontrol logic 50 of theextender30 will assert "req" at point "j" in FIGURE 5 to request that amessage from thehost computer 14 be sent over the data lines.Thehost computer 14 as the initiator responds to the REQUESTby sending data on the data lines at "k," setting the correctdata parity for the data being sent at "l", and asserting "ack"at "m."

In order for thebus extender 30 to pass the message datato the ultimate target on theauxiliary bus 28, the extenderhas to identify that device. Thehost computer 14 sends anidentification of the ultimate target in an IDENTIFY message,which, pursuant to the SCSI standards, usually begins themessage data transmission.

The IDENTIFY message according to the SCSI standards has alogical unit number ("LUN") field that can serve as an address-descriptor.While conventionally the LUN field is used forother purposes, the invention uses that field to designate theperipheral device which is the ultimate target on theauxiliarybus 28 to which thehost computer 14 is sending the messages.

In order to pass the message on to the designated ultimatetarget, however, theextender 30 has to generate appropriateconnection-control signals for theauxiliary bus 28. It will beremembered that a first connection-control signal generallycontains the ID of a device on the SCSI bus that is initiatingthe information transfer, and the ID of the target on that bus.Accordingly, the main-bus connection-control signals receivedby thebus extender 30 typically has to be translated to thosewhich the ultimate target will recognize, i.e., to connection-controlsignals having auxiliary bus ID's for the initiator andtarget on theauxiliary bus 28. (Furthermore, SCSI-conformingperipheral devices typically expect the value of the LUN fieldto be zero.)

Consequently, theconverter 66 is charged with recoveringthe data from the LUN field of the main-bus second connection-controlsignal, i.e., the IDENTIFY message, and translatingthat data into the auxiliary-bus ID of the ultimate target.Since, according to the standards, the LUN field is three-bitswide, and the ID is an eight-bit number with a single bit HIGH,the translating process is essentially a 3-bit to 8-bit("3b/8b") decoding resulting in a bit mask containing eightbits. The various bit masks for each LUN value are given inthe table below:

The resulting ID can then be used as part of the firstconnection-control signal on theauxiliary bus 28. The otherpart of that signal is the initiator ID, which is provided bythesignal generator 72 and is the preferably factory-setauxiliary-bus ID of theextender 30, which is shown in FIGURE1 as ID_7.

Since, preferably, message data is transferred withoutsignificant delay in theextender 30 from one bus to theother, theextender 30 performs certain steps with respect totheauxiliary bus 28 at the same time as theextender 30 isresponding to themain bus 26. Thus, while holding the reqline asserted on themain bus 26, theextender 30 undertakesARBITRATION and SELECTION on the auxiliary bus so as to reachthe message-out phase as soon as possible.

Accordingly, theextender 30 initiates auxiliary-busARBITRATION as soon as it detects a main-bus SELECT signalwith the extender designated as the target. For this, theextender 30 asserts BUSY on theauxiliary bus 28 at point "n,"and its own ID, which is shown in FIGURE 1 as ID_7, on thedata lines dbn at "p."

Since that ID has the highest value, if contention forthebus 28 occurs, theextender 30 will always have thehighest priority. Thus, if anyperipheral device 24 on theauxiliary bus 28 is attempting RESELECTION at the same time as theextender 30 is attempting to gain control of theauxiliarybus 28 for SELECTION, the extender will prevail. This givesthehost computers 14, 16 preference on theauxiliary bus 28during contention, which is desirable to permit greaterutilization of the peripherals by promoting parallel oroverlapping operation of the peripheral devices.

After gaining control of theauxiliary bus 28, theextender 30 then asserts an auxiliary-bus first connection-controlsignal, which theextender 30 generates using datafrom the main-bus IDENTIFY signal, as described above. Thetarget with that ID responds by asserting BUSY on theauxiliary bus 28 at "q."

Because theextender 30 asserts the atn line at point "r"on theauxiliary bus 28 whenever that line is asserted on themain bus 26, the target prepares to enter a message out phase,which starts with an IDENTIFY message fromextender 30. Afterthe IDENTIFY, theextender 30 asserts the ack line on theauxiliary bus 28 at "s," which tells the target that messagedata (in contra-distinction to connection-control signals) canbe received.

For message data transfer, the main andauxiliary buses26, 28 are connected directly via theDEMUX 62 andMUX 68. Theskew time and delays through these components along themessage data path are preferably as short as possible.

During message transfer, theextender 30 no longerintervenes in the information transfer. Instead, theextender30 simply monitors the transfer for IDENTIFY signals, whichwill require translation by theextender 30, as describedabove, and monitors the i/o line to detect any change intransfer direction that would require the extender to changethe direction of itstransceivers 42, 44. In addition, theextender 30 monitors the BUSY and SELECT lines to detecttermination of the data transfer, which would result in a busfree phase and permit another SELECTION or a RESELECTION.

FIGURE 8 illustrates RESELECTION after a DISCONNECT, which proceeds in a fashion analogous to that just describedfor selection. In RESELECTION, the target reverses the stateof the i/o line. Theextender 30 responds to a auxiliary-busfirst connection-control signal from the target on theauxiliary bus 26 that contains the extender's own auxiliary-busID. When such a connection-control signal is received,theextender 30 immediately arbitrates for themain bus 26,and sends a main-bus connection-control, using its own main-busID in the initiator field. Since a RESELECT is merely thecontinuation of a prior information transfer, theextender 30preferably stores the ID of the initiator of the earlierSELECT within thelatch 49, and uses the stored initiator IDcorresponding with the target that performed the RESELECT togenerate the main-bus connection-control signals. Messagetransfer thereafter ensues.

In the event themain bus 26 is BUSY when theextender 30receives a RESELECT (e.g., thecomputer 14 is communicatingwith anotherdevice 16, 22 on the main bus 26), theextender30 waits until the main bus becomes free and then arbitratesfor control. During this time, theauxiliary bus 28 is hung,and no communication on that bus takes place.

Moreover, in the event a contention occurs between aSELECTION and a RESELECTION, theextender 30 preferably causesan "unexpected bus free" state, as specified in the SCSIstandards, to occur on themain bus 26 after the SELECTION hascompleted and the IDENTIFY message has been acquired.
Preferably, thehost computer 14 interprets such a state asindicating that a RESELECTION from theextender 30 is desired,and, e.g., permits RESELECTION to ensue.

The foregoing description has been limited to a specificembodiment of this invention.

Claims (9)

1. A bus extender for interconnecting a main bus having a first deviceconnected thereto to an auxiliary bus having a plurality of second devicesconnected thereto and for permitting communication between said first deviceand said second devices, comprising:

   main bus and auxiliary-bus transceivers for sending and receiving firstand second sets of connection-control signals and a plurality of messagedata signals over respective main and auxiliary buses, a plurality of saidfirst sets of connection-control signals containing identifierscorresponding to said extender; and

   transfer circuit means coupled between said main-bus and auxiliary-bustransceivers for receiving said extender-identifier-containing first sets ofconnection-control signals from one of said transceivers, selectivelytranslating said received extender-identifier-containing first sets ofconnection-control signals to the other of said transceivers, and forpassing a plurality of message data signals (1) received from said onetransceiver, and (2) corresponding to said extender-identifier-containingfirst connection-control signals, directly from said one transceiver to saidother transceiver, said transfer circuit means including:

   i) converter means for converting data in said first set ofconnection-control signals into target identifiers for use in identifying thesecond devices to which the message data signals are to be sent by saidother transceiver, and

   ii) connection-control signal generating means coupled with saidconverter means for forming said second sets of connection-controlsignals, said second sets of connection-control signals including said target identifiers.
2. The bus extender in accordance with claim 1, wherein said transfercircuit means further comprises first passing means coupled with saidconnection-control signal generating means for receiving said second sets ofconnection-control signals; and second passing means for receiving signalsincluding said first set of connection-control signals and said message datasignals, and, in response to a plurality of first control signals, passing themessage data signals to said first passing means and said first sets ofconnection-control signals to said converter means; said first passing meansbeing responsive to a plurality of second control signals for passing saidmessage data signals received from said second passing means and said secondsets of connection-control signals to said other transceiver.
3. The bus extender in accordance with claim 1, wherein one of said main-busand auxiliary-bus transceivers comprises a differential transceiver and theother comprises a single-ended transceiver.
4. The bus extender in accordance with claim 1, wherein said connection-controlsignal generating means forms second sets of connection-control signalshaving fields, containing an identifier corresponding to said extender, and fieldscontaining the target identifiers generated by said converter means.
5. The bus extender in accordance with claim 1, further comprising controllogic means for supplying said first and second control signals to said first andsecond passing means.
6. The bus extender in accordance with claim 5, wherein said control logic means includes first and second control logic modules for monitoring signalsreceived by said transceivers, and, in response thereto, controlling the directionof said transceivers.
7. The bus extender in accordance with claim 6, wherein said control logicmeans generates third connection-control signals in response to signals receivedby said one transceiver, and supplies said third connection-control signals tosaid other transceiver.
8. A method of operating a bus extender that interconnects a first bus and asecond bus for communication between a first device connected to said first busand a second device connected to said second bus, said bus extender having afirst identifier on said first bus and a second identifier on said second bus, said methodcomprising the steps of:

   (A) monitoring a plurality of target identifier fields of a plurality of firstconnection control signals received over said first bus to identify thosefirst connection-control signals containing said first identifier, thereby indicatingthat said bus extender is a designated recipient thereof;

   (B) in response to said first connection-control signals identified in step(A);

   generating a plurality of initiator identifiers from data in a plurality ofinitiator identifier fields of said first connection-control signals so as toidentify an initiator for each said first connection-control signals,and establishing a communication link for each over said first buswith said identified initiator;

   arbitrating for control of the second bus;

   translating data contained in a plurality of descriptor fields of said first connection-control signals into a plurality of target identifiers onsaid second bus;

   generating a plurality of second connection-control signalscorresponding to said first connection-control signals, said secondconnection-control signal representing said target identifiers on saidsecond bus in a plurality of target identifier fields, and said second identifiers ina plurality of initiator fields;

   sending said second connection-control signals over saidsecond bus to establish for each a communication link with a targetidentified by said target identifier.
9. The method in accordance with claim 8, wherein step (B) further includesthe step of storing said initiator identifiers.

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