EP0469583A2 - Semiconductor substrate with complete dielectric isolation structure and method of making the same - Google Patents
Semiconductor substrate with complete dielectric isolation structure and method of making the sameDownload PDFInfo
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- EP0469583A2 EP0469583A2EP91112887AEP91112887AEP0469583A2EP 0469583 A2EP0469583 A2EP 0469583A2EP 91112887 AEP91112887 AEP 91112887AEP 91112887 AEP91112887 AEP 91112887AEP 0469583 A2EP0469583 A2EP 0469583A2
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- semiconductor substrate
- insulating film
- grooves
- oxide film
- island regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76275—Vertical isolation by bonding techniques
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76289—Lateral isolation by air gap
Definitions
- the present inventionrelates to a semiconductor substrate having a complete dielectric isolation structure and a method of making the same.
- a p-n junction or a dielectric isolation structurehas been well known as an isolation structure.
- the dielectric isolation structurehas the following advantages as compared to the p-n junction isolation structure;
- a method using direct bonding of two substratesa method of epitaxially growing silicon on a sapphire substrate called an SOS, and a method of recrystallizing amorphous silicon deposited on an insulating film have been known.
- the following methodhas been also known. That is, a part of a silicon wafer is etched to form an oxide film, and a polysilicon layer is deposited thereon. Thereafter, the resultant structure is lapped from its lower surface, thereby obtaining island regions supported by the polysilicon layer and isolated from one another.
- the method using bonding of two substratesis an excellent one having the following characteristics. That is, a thick silicon layer having a high quality is provided as an active layer, and the bonded wafer has a relatively low warpage.
- a method of making a dielectric isolation substrate using the above bondingwill be described below with reference to Figs. 6A to 6D.
- Silicon wafers 31 and 32 each having at least one mirror surfaceare prepared, an oxide film 33 is formed on the surface of one of the silicon wafers 31 and 32.
- the two wafers 31 and 32are heat-treated to be integrally boned, while the oxide film 33 is interposed therebetween. Thereafter, the surface of the silicon wafer 32, which serves as an active layer for providing circuit elements therein, is lapped to have a predetermined thickness (Fig. 6A).
- the surface of the silicon wafer 32is selectively etched by anisotropic etching to form a groove 34 having a V-shaped section, and an oxide film 35 is formed on the surface of the silicon wafer 32 (Fig. 6B).
- a polysilicon layer 36is deposited on the entire surface of the oxide film 35 to bury the groove 34 therewith (Fig. 6C).
- the deposited surface of the polysilicon layer 36is lapped by lapping or the like so as to be planarized, thereby obtaining a dielectric isolation substrate (Fig. 6D).
- the thickness of the oxide film 33is defined by a dielectric breakdown voltage and a capacitance, which are required between the active layer, on which circuit elements are to be provided, and the wafer 31 serving as a support substrate.
- the oxide film 33 having a thickness of about several /1.mis required for circuit element characteristics.
- the thickness of the oxide film for dielectric isolationmust be structurally increased.
- Fig. 7shows a relationship between an isolation oxide film thickness (/1.m) and warpage d (/1.m) of a wafer, wherein a shift d between the edge and the center of the wafer having a diameter of 100 mm is measured.
- the warpageis increased in proportion to the thickness of the oxide film. This relationship can be obtained when the wafer has a large diameter.
- the warpage dis proportional to the square of the wafer diameter, the substrate is affected by the warpage as increasing the diameter.
- a fine PEPphotoetching process
- an object of the present inventionto provide a semiconductor substrate which has a dielectric isolation structure with a reduced warpage.
- a semiconductor substrate having dielectrically isolated island regionswhich comprises a first semiconductor substrate for providing circuit elements, a second semiconductor substrate for supporting the first semiconductor substrate, a first insulating film located between the first and second semiconductor substrates, a plurality of grooves formed in the first semiconductor substrate to expose a surface of the second semiconductor substrate, and a second insulating film formed on the exposed surface of the second semiconductor substrate.
- a plurality of island regionsare provided above the second semiconductor substrate through the first insulating film and the second insulating film is thinner than the first insulating film so as to reduce unwanted warpage produced in the semiconductor substrate.
- a semiconductor substrate according to the first embodiment of the present invention and steps in making the samewill be described below.
- 20 n-type silicon wafers 11each having a diameter of 125 mm, a thickness of 625 ⁇ m, a crystal plane of (100), and a resistivity p of about 0.15 Q. cm are prepared, and a thermal oxide film 13 having a thickness of 2 ⁇ m is formed on each of the silicon wafers 11.
- 20 silicon wafers 12each having a diameter of 125 mm, a thickness of 525 ⁇ m, a crystal plane of (100), and a resistivity of about 40 Q. cm are prepared.
- each of the wafers 11 and each of the wafers 12are bonded to each other in a clean atmosphere.
- the resultant structureis heat-treated in a mixed gas atmosphere, composed of an 0 2 gas and an N 2 gas, at a temperature of 1,100°C for 2 hours, thereby providing one complete wafer.
- the mixed gasis obtained by mixing the 0 2 gas with the N 2 gas at a ratio of 1 : 4.
- the silicon wafer 11is lapped to have a thickness of, e.g., 25 ⁇ m (Fig. 1A).
- An oxide film 14is formed on the surface of the wafer 11.
- An etching mask 15 of a photoresist layeris formed on the oxide film 14 by well-known techniques (Fig. 1 B).
- the resultant structureis anisotropically etched by a potassium hydroxide solution, using the remained oxide film 14 as a mask.
- V-shaped grooves 16are then formed in the wafer 11, thereby providing a plurality of isolated island regions 111 (Fig. 1 C).
- the oxide films 13 located on bottoms of the grooves 16are then removed by an aqueous solution composed of hydrofluoric acid and pure water at a mixing ratio of 1 : 2, thereby exposing the surface of the wafer 12 (Fig. 1 D).
- the oxide film 13 located on the bottom of each groove 16was removed from each of the 10 wafers of the 20 wafers, and the oxide film 13 was not removed from each of the 10 remaining wafers.
- a measurement of the warpagewas then carried out on both wafer groups, using a surface roughness gauge. The following results were obtained. That is, one wafer group with the oxide film 13 had a convex warpage of about 60 ⁇ m, but the other wafer group without the oxide film 13 had the warpage of about 30 tim.
- An oxide film 17 having a thickness of 0.5 ⁇ mis formed on the bottom of each groove 16 and the surface of each island region 111 (Fig. 1 E).
- a polysilicon layer 18is deposited on the entire surface of the resultant structures to have a thickness of 50 ⁇ m (Fig. 1 F).
- the island regions 111are lapped to have a thickness of 15 ⁇ m, thereby providing a dielectric isolation substrate (Fig. 1 G).
- both substrate groupshad the dielectric breakdown voltage of 1300 - 1500 V between each island region 111 and the support wafer 12, and had also the similar capacitance values to each other.
- the oxide film 13 located on each of the bottoms of the grooves 16is completely removed as shown in Fig. 1D.
- the substratemay be etched so as to leave a thin oxide film 130 as shown in Fig. 1 H.
- the thickness of the oxide film 17 located between the bottom portions of the grooves 16 and the wafer 12is sufficiently reduced as compared with the oxide film 13 located between the wafer 11 and wafer 12, the amount of the warpage can be reduced.
- the thickness of the wafer 11can be precisely controlled, processing precision can be improved, and the diameter of the wafer 11 can be increased.
- the dielectric isolation substratehas the small warpage, fine PEP or the like can be easily performed by lithography apparatus in the wafer process.
- the thickness of the oxide film 17is reduced, good results can be obtained.
- the area of the groove or the area of the thin oxide filmis increased, good advantages can be obtained.
- the oxide film formed on the bottom of each groovewas once removed by etching, and the exposed support wafer surface was oxidized to provide a thin oxide film thereon.
- the area of the groove and the film thicknesswere changed to investigate the advantages.
- the warpagewas reduced because the thickness of the oxide film formed on the bottom of the groove was decreased. The reason for the reduction of the warpage did not merely depend upon the reduction of the total amount of the oxide films.
- the resultshows that a stress is released by isolating the thick oxide film into a large number of parts.
- the ratio of the grooves to the substrate areaexceeded 1/3, conspicuous advantages could be obtained.
- the thickness of the oxide film 17was increased, crystal defects occurred in the island regions 111 and the wafer 12. Since the island regions 111 and the oxide film 13 serve as a mask when the bottom of the groove is oxidized, crystal defects may occur by a mechanism similar to that of LOCOS defects. The defects do not occur when the thickness of the oxide film 17 is 90% or less of that of the oxide film 13.
- FIG. 2Athe oxide film 17 of the first embodiment is not formed on the bottom of the groove 16, and the oxide film 17 are formed on only the side surface of the groove 16.
- the groove 16 having a V-shaped sectionis used in the first embodiment, a groove 16 having vertical side surface and formed by, e.g., an RIE (Reactive Ion Etching) technique are used as shown in Fig. 3.
- the thin film 17is formed on only the side surface of the groove 16.
- the second embodimentsince an oxide film is entirely removed from the bottom of the groove 16, the warpage of the wafer is greatly reduced, and a polysilicon layer 18 buried in the groove 16 can be electrically connected to the support wafer 12.
- the polysilicon layer 18 buried in the groove 16 and the support wafer 12are generally kept at a ground potential.
- a wiring layersince the polysilicon layers 18 is insulated from the wafer 12 by the oxide film 17, a wiring layer must be arranged to decrease the potential of the polysilicon layer 18 to the ground potential. However, according to the second embodiment, this wiring layer is not necessary.
- the grooves 16 between the island regions 111may be buried with an insulating material 19 such as resin.
- the semiconductor substratehas a structure similar to the structure shown in Figs. 1G, 2A, and 2B.
- grooves 16are not buried with a polysilicon layer 18, and the isolation is performed while exposing the groove 16.
- the structureis often used in a case where the thickness of the wafer 11 or the island region 111 is thin.
- the same advantages as described in the first embodimentcan be obtained.
- the present inventionis not limited to the above embodiments, and various modifications can be provided.
- the substrate obtained such that silicon substrates are integrally bonded to each other through the oxide film by the direct bonding techniquehas been described in the above embodiments.
- the present inventioncan be applied to a substrate obtained such that silicon substrates are integrally bonded through a dielectric film having a thermal expansion coefficient different from that of the silicon substrates by another bonding method such as electrostatic bonding techniques and CVD glass bonding techniques.
- the thick oxide filmis located only between island regions, which are made of silicon and in which circuit elements are to be formed, and the support substrate, and the oxide film on the bottom of the groove for isolating the island regions from each other has a thin thickness or is removed. Therefore, the warpage of the wafer can be greatly reduced, processing precision can be improved, and the wafer having the large diameter can be obtained.
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Abstract
Description
- The present invention relates to a semiconductor substrate having a complete dielectric isolation structure and a method of making the same.
- In a conventional semiconductor device, a p-n junction or a dielectric isolation structure has been well known as an isolation structure. The dielectric isolation structure has the following advantages as compared to the p-n junction isolation structure;
- (a) a leakage current is low and an unwanted latch-up phenomenon is not caused even in a high temperature operation,
- (b) an area required for the isolation is small even if circuit elements with a high breakdown voltage are isolated from each other;
- (c) it is not necessary to consider a polarity of voltage to be applied, and
- (d) a parasitic capacitance is low.
- Several methods have been known to obtain such a dielectric isolation structure. For example, a method using direct bonding of two substrates, a method of epitaxially growing silicon on a sapphire substrate called an SOS, and a method of recrystallizing amorphous silicon deposited on an insulating film have been known. In addition, the following method has been also known. That is, a part of a silicon wafer is etched to form an oxide film, and a polysilicon layer is deposited thereon. Thereafter, the resultant structure is lapped from its lower surface, thereby obtaining island regions supported by the polysilicon layer and isolated from one another.
- Of the above methods, the method using bonding of two substrates is an excellent one having the following characteristics. That is, a thick silicon layer having a high quality is provided as an active layer, and the bonded wafer has a relatively low warpage. A method of making a dielectric isolation substrate using the above bonding will be described below with reference to Figs. 6A to 6D.
- Silicon wafers 31 and 32 each having at least one mirror surface are prepared, an
oxide film 33 is formed on the surface of one of thesilicon wafers wafers oxide film 33 is interposed therebetween. Thereafter, the surface of thesilicon wafer 32, which serves as an active layer for providing circuit elements therein, is lapped to have a predetermined thickness (Fig. 6A). - In order to separate the active layer into island regions, the surface of the
silicon wafer 32 is selectively etched by anisotropic etching to form agroove 34 having a V-shaped section, and anoxide film 35 is formed on the surface of the silicon wafer 32 (Fig. 6B). - A
polysilicon layer 36 is deposited on the entire surface of theoxide film 35 to bury thegroove 34 therewith (Fig. 6C). - The deposited surface of the
polysilicon layer 36 is lapped by lapping or the like so as to be planarized, thereby obtaining a dielectric isolation substrate (Fig. 6D). - In this case, the thickness of the
oxide film 33 is defined by a dielectric breakdown voltage and a capacitance, which are required between the active layer, on which circuit elements are to be provided, and thewafer 31 serving as a support substrate. Theoxide film 33 having a thickness of about several /1.m is required for circuit element characteristics. - However, when the circuit element characteristics such as a low parasitic capacitance and a high dielectric breakdown voltage are required, the thickness of the oxide film for dielectric isolation must be structurally increased.
- However, when the thickness of the film is increased, a produced warpage is increased due to a difference between a thermal expansion coefficient of silicon and that of the oxide film. For this reason, it is difficult to precisely control the thickness of the island region. Fig. 7 shows a relationship between an isolation oxide film thickness (/1.m) and warpage d (/1.m) of a wafer, wherein a shift d between the edge and the center of the wafer having a diameter of 100 mm is measured. The warpage is increased in proportion to the thickness of the oxide film. This relationship can be obtained when the wafer has a large diameter. Further, since the warpage d is proportional to the square of the wafer diameter, the substrate is affected by the warpage as increasing the diameter. In a wafer process, when a wafer has the large warpage, a fine PEP (photoetching process) by lithography apparatus or the like is not easily performed.
- It is, therefore, an object of the present invention to provide a semiconductor substrate which has a dielectric isolation structure with a reduced warpage.
- It is another object of the present invention to provide a semiconductor substrate having a dielectric isolation structure which has a high precision in processing dimensions.
- It is still another object of the present invention to provide a method of making a semiconductor substrate which has a dielectric isolation structure with a reduced warpage.
- It is still another object of the present invention to provide a method of making a semiconductor substrate having a dielectric isolation structure which has a high precision in processing dimensions.
- According to one aspect of the present invention, there is provided a semiconductor substrate having dielectrically isolated island regions, which comprises a first semiconductor substrate for providing circuit elements, a second semiconductor substrate for supporting the first semiconductor substrate, a first insulating film located between the first and second semiconductor substrates, a plurality of grooves formed in the first semiconductor substrate to expose a surface of the second semiconductor substrate, and a second insulating film formed on the exposed surface of the second semiconductor substrate. In the structure, a plurality of island regions are provided above the second semiconductor substrate through the first insulating film and the second insulating film is thinner than the first insulating film so as to reduce unwanted warpage produced in the semiconductor substrate.
- According to another aspect of the present invention, there is provided a method of making the semiconductor substrate according to a principle incorporated in the first referred aspect of the present invention.
- The novel and distinctive features of the invention are set forth in the claims appended to the present application. The invention itself, however, together with further objects and advantages thereof may best be understood by reference to the following description and accompanying drawings in which:
- Figs. 1A to 1H are sectional views sequentially showing steps in making a semiconductor substrate according to the first embodiment of the present invention;
- Figs. 2A, 2B, and 3 are sectional views showing a semiconductor substrate according to the second embodiment of the present invention;
- Figs. 4 and 5 are sectional views showing a semiconductor substrate according to the third embodiment of the present invention;
- Figs. 6A to 6D are sectional views sequentially showing steps in making a conventional semiconductor substrate; and
- Fig. 7 is a graph showing a relationship between an oxide film thickness and warpage of a wafer in a semiconductor substrate made by a conventional method.
- The present invention will be described below with reference to embodiments in conjunction with the accompanying drawings.
- Referring to Figs. 1A to 1G, a semiconductor substrate according to the first embodiment of the present invention and steps in making the same will be described below. First, 20 n-type silicon wafers 11 each having a diameter of 125 mm, a thickness of 625 µm, a crystal plane of (100), and a resistivity p of about 0.15 Q. cm are prepared, and a
thermal oxide film 13 having a thickness of 2 µm is formed on each of thesilicon wafers 11. Independently of the silicon wafers 11, 20 silicon wafers 12 each having a diameter of 125 mm, a thickness of 525 µm, a crystal plane of (100), and a resistivity of about 40 Q. cm are prepared. Thereafter, each of thewafers 11 and each of thewafers 12 are bonded to each other in a clean atmosphere. The resultant structure is heat-treated in a mixed gas atmosphere, composed of an 02 gas and an N2 gas, at a temperature of 1,100°C for 2 hours, thereby providing one complete wafer. The mixed gas is obtained by mixing the 02 gas with the N2 gas at a ratio of 1 : 4. Thesilicon wafer 11 is lapped to have a thickness of, e.g., 25 µm (Fig. 1A). - An
oxide film 14 is formed on the surface of thewafer 11. Anetching mask 15 of a photoresist layer is formed on theoxide film 14 by well-known techniques (Fig. 1 B). - After the exposed
oxide film 14 is selectively removed, the resultant structure is anisotropically etched by a potassium hydroxide solution, using the remainedoxide film 14 as a mask. V-shapedgrooves 16 are then formed in thewafer 11, thereby providing a plurality of isolated island regions 111 (Fig. 1 C). - The
oxide films 13 located on bottoms of thegrooves 16 are then removed by an aqueous solution composed of hydrofluoric acid and pure water at a mixing ratio of 1 : 2, thereby exposing the surface of the wafer 12 (Fig. 1 D). - At this time, for the sake of comparison, the
oxide film 13 located on the bottom of eachgroove 16 was removed from each of the 10 wafers of the 20 wafers, and theoxide film 13 was not removed from each of the 10 remaining wafers. A measurement of the warpage was then carried out on both wafer groups, using a surface roughness gauge. The following results were obtained. That is, one wafer group with theoxide film 13 had a convex warpage of about 60 µm, but the other wafer group without theoxide film 13 had the warpage of about 30 tim. - An
oxide film 17 having a thickness of 0.5 µm is formed on the bottom of eachgroove 16 and the surface of each island region 111 (Fig. 1 E). - A
polysilicon layer 18 is deposited on the entire surface of the resultant structures to have a thickness of 50 µm (Fig. 1 F). - The
island regions 111 are lapped to have a thickness of 15 µm, thereby providing a dielectric isolation substrate (Fig. 1 G). - At this time, a measurement of the warpage was again carried out on both dielectric isolation substrate groups, using the surface roughness gauge. The following results were obtained. That is, one substrate group, which newly included the
thin oxide film 17 on the bottom of eachgroove 16 after removing theoxide film 13 therefrom, had the warpage of about 50 µm, and the variation in the island thickness was 15 ± 2 µm. On the contrary, the other substrate group, which included theoxide film 13 remained on the bottom of eachgroove 16, had the warpage of about 100 /1.m, and the variation in the island thickness was 15 ± 6 /1.m. - Further, both substrate groups had the dielectric breakdown voltage of 1300 - 1500 V between each
island region 111 and thesupport wafer 12, and had also the similar capacitance values to each other. - The
oxide film 13 located on each of the bottoms of thegrooves 16 is completely removed as shown in Fig. 1D. However, without completely removing theoxide film 13, the substrate may be etched so as to leave athin oxide film 130 as shown in Fig. 1 H. - As described above, since the thickness of the
oxide film 17 located between the bottom portions of thegrooves 16 and thewafer 12 is sufficiently reduced as compared with theoxide film 13 located between thewafer 11 andwafer 12, the amount of the warpage can be reduced. As a result, when circuit elements are provided using the dielectric isolation substrate having the structure shown in Fig. 1 G, the thickness of thewafer 11 can be precisely controlled, processing precision can be improved, and the diameter of thewafer 11 can be increased. In addition, since the dielectric isolation substrate has the small warpage, fine PEP or the like can be easily performed by lithography apparatus in the wafer process. - As the thickness of the
oxide film 17 is reduced, good results can be obtained. In addition, as the area of the groove or the area of the thin oxide film is increased, good advantages can be obtained. At this time, the oxide film formed on the bottom of each groove was once removed by etching, and the exposed support wafer surface was oxidized to provide a thin oxide film thereon. In such a substrate the area of the groove and the film thickness were changed to investigate the advantages. As a result, when the length of each short side of a rectangular island was given by 2 mm or less, remarkable advantages could be obtained. According to the result, the warpage was reduced because the thickness of the oxide film formed on the bottom of the groove was decreased. The reason for the reduction of the warpage did not merely depend upon the reduction of the total amount of the oxide films. Therefore, the result shows that a stress is released by isolating the thick oxide film into a large number of parts. In addition, when the ratio of the grooves to the substrate area exceeded 1/3, conspicuous advantages could be obtained. When the thickness of theoxide film 17 was increased, crystal defects occurred in theisland regions 111 and thewafer 12. Since theisland regions 111 and theoxide film 13 serve as a mask when the bottom of the groove is oxidized, crystal defects may occur by a mechanism similar to that of LOCOS defects. The defects do not occur when the thickness of theoxide film 17 is 90% or less of that of theoxide film 13. - A semiconductor substrate according to the second embodiment of the present invention will be described below with reference to Figs. 2A, 2B, and 3. In Fig. 2A, the
oxide film 17 of the first embodiment is not formed on the bottom of thegroove 16, and theoxide film 17 are formed on only the side surface of thegroove 16. Although thegroove 16 having a V-shaped section is used in the first embodiment, agroove 16 having vertical side surface and formed by, e.g., an RIE (Reactive Ion Etching) technique are used as shown in Fig. 3. Thethin film 17 is formed on only the side surface of thegroove 16. According to the second embodiment, since an oxide film is entirely removed from the bottom of thegroove 16, the warpage of the wafer is greatly reduced, and apolysilicon layer 18 buried in thegroove 16 can be electrically connected to thesupport wafer 12. In order to stabilize the characteristics of circuit elements formed insilicon island regions 111, thepolysilicon layer 18 buried in thegroove 16 and thesupport wafer 12 are generally kept at a ground potential. According to the first embodiment, since the polysilicon layers 18 is insulated from thewafer 12 by theoxide film 17, a wiring layer must be arranged to decrease the potential of thepolysilicon layer 18 to the ground potential. However, according to the second embodiment, this wiring layer is not necessary. - As shown in Fig. 2B, the
grooves 16 between theisland regions 111 may be buried with an insulatingmaterial 19 such as resin. - A semiconductor substrate according to the third embodiment of the present invention will be described below with reference to Figs. 4 and 5. In the embodiment, the semiconductor substrate has a structure similar to the structure shown in Figs. 1G, 2A, and 2B. In the third embodiment,
grooves 16 are not buried with apolysilicon layer 18, and the isolation is performed while exposing thegroove 16. The structure is often used in a case where the thickness of thewafer 11 or theisland region 111 is thin. In the second and third embodiments, the same advantages as described in the first embodiment can be obtained. - The present invention is not limited to the above embodiments, and various modifications can be provided. For example, the substrate obtained such that silicon substrates are integrally bonded to each other through the oxide film by the direct bonding technique has been described in the above embodiments. The present invention can be applied to a substrate obtained such that silicon substrates are integrally bonded through a dielectric film having a thermal expansion coefficient different from that of the silicon substrates by another bonding method such as electrostatic bonding techniques and CVD glass bonding techniques.
- As described above, according to the present invention, the thick oxide film is located only between island regions, which are made of silicon and in which circuit elements are to be formed, and the support substrate, and the oxide film on the bottom of the groove for isolating the island regions from each other has a thin thickness or is removed. Therefore, the warpage of the wafer can be greatly reduced, processing precision can be improved, and the wafer having the large diameter can be obtained.
- It is further understood by those skilled in the art that the foregoing description is preferred embodiments and that various changes and modifications may be made in the invention without departing from the spirit and scope thereof.
Claims (19)
1. A semiconductor substrate having dielectrically isolated island regions (111) including a first semiconductor substrate (11) for providing circuit elements, a second semiconductor substrate (12) for supporting said first semiconductor substrate (11), an insulating film (13) located between said first and second semiconductor substrates (11, 12), and a plurality of grooves (16) formed in said first semiconductor substrate (11) to expose a surface of said second semiconductor substrate (12), characterized in that a plurality of island regions (111) are provided above said second semiconductor substrate (12) through only said insulating film (13).
2. The semiconductor substrate according to claim 1, characterized in that a side surface of each of said island regions (111) is covered with a thin insulating film (17).
3. The semiconductor substrate according to claim 2, characterized in that said grooves (16) are filled with an insulating material (19).
4. The semiconductor substrate according to claim 1, characterized in that each of said grooves (16) has a V-shaped structure.
5. The semiconductor substrate according to claim 1, characterized in that each of said grooves (16) is comprised of a trench.
6. The semiconductor substrate according to claim 2, characterized in that said grooves are filled with polysilicon (18).
7. A semiconductor substrate having dielectrically isolated island regions (111) including a first semiconductor substrate (11) for providing circuit elements, a second semiconductor substrate (12) for supporting said first semiconductor substrate (11), a first insulating film (13) located between said first and second semiconductor substrates (11, 12), a plurality of grooves (16) formed in said first semiconductor substrate (11) to provide a plurality of island regions (111), and a second insulating film (17) provided on said second semiconductor substrate (12),
characterized in that said plurality of island regions (16) are provided above said second semiconductor substrate (12) through said first insulating film (13) and that said second insulating film (17) is thinner than said first insulating film (13).
8. The semiconductor substrate according to claim 7, characterized in that a side surface of each of said island regions (111) is covered with said second insulating film (17).
9. The semiconductor substrate according to claim 8, characterized in that said grooves (16) are filled with polysilicon (18).
10. The semiconductor substrate according to claim 7, characterized in that each of said grooves (16) has a V-shaped structure.
11. The semiconductor substrate according to claim 7, characterized in that each of said grooves (16) is comprised of trench.
12. A method of making a semiconductor substrate having dielectrically isolated island regions (111) comprising the steps of:
preparing first and second semiconductor substrates (11, 12);
forming an insulating film (13) on a surface of at least one of said first and second semiconductor substrates (11, 12);
directly bonding said first semiconductor substrate (11) to said second semiconductor substrate (12) through said insulating film (13); and
forming grooves (16) in said first semiconductor substrate (11) to provide a plurality of island regions (111) on said second semiconductor substrate (12).
13. The method according to claim 12, characterized in that said forming grooves (16) in said first semiconductor substrate (11) includes the step of removing said insulating film (13) to a desired thickness.
14. The method according to claim 12, characterized in that said forming grooves (16) in said first semiconductor substrate (11) includes the step of removing said insulating film (13) to expose a surface of said second semiconductor substrate (12).
15. The method according to claim 13, characterized in that said grooves (16) are filled with an insulating material (19).
16. The method according to claim 14, characterized in that a thin insulating film (17) is formed on the exposed surface of said second semiconductor substrate (12).
17. The method according to claim 16, characterized in that a thin insulating film (17) is formed on a side surface of each of said island regions (111).
18. The method according to claim 17, characterized in that said grooves (16) are filled with polysilicon (18).
19. The method according to claim 16, characterized in that said thin insulating film (17) is thinner than said insulating film (13).
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP203563/90 | 1990-07-31 | ||
| JP2203563AJPH0488657A (en) | 1990-07-31 | 1990-07-31 | Semiconductor device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP0469583A2true EP0469583A2 (en) | 1992-02-05 |
| EP0469583A3 EP0469583A3 (en) | 1993-02-03 |
Family
ID=16476208
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP19910112887WithdrawnEP0469583A3 (en) | 1990-07-31 | 1991-07-31 | Semiconductor substrate with complete dielectric isolation structure and method of making the same |
Country Status (2)
| Country | Link |
|---|---|
| EP (1) | EP0469583A3 (en) |
| JP (1) | JPH0488657A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1993026041A1 (en)* | 1992-06-17 | 1993-12-23 | Harris Corporation | Bonded wafer processing |
| CN100510824C (en)* | 2005-02-10 | 2009-07-08 | 奔瑞公司 | Sealed tube coupling for optical fiber tubes |
| CN113675220A (en)* | 2020-07-30 | 2021-11-19 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5457068A (en)* | 1992-11-30 | 1995-10-10 | Texas Instruments Incorporated | Monolithic integration of microwave silicon devices and low loss transmission lines |
| KR100319615B1 (en)* | 1999-04-16 | 2002-01-09 | 김영환 | Isolation method in seconductor device |
| US7262112B2 (en)* | 2005-06-27 | 2007-08-28 | The Regents Of The University Of California | Method for producing dislocation-free strained crystalline films |
| JP2011192882A (en)* | 2010-03-16 | 2011-09-29 | Nec Corp | Semiconductor structure, semiconductor device, and method of manufacturing the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6173345A (en)* | 1984-09-19 | 1986-04-15 | Toshiba Corp | semiconductor equipment |
| JPS63314844A (en)* | 1987-06-18 | 1988-12-22 | Toshiba Corp | Manufacture of semiconductor device |
| JP2777920B2 (en)* | 1989-12-20 | 1998-07-23 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
- 1990
- 1990-07-31JPJP2203563Apatent/JPH0488657A/enactivePending
- 1991
- 1991-07-31EPEP19910112887patent/EP0469583A3/ennot_activeWithdrawn
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1993026041A1 (en)* | 1992-06-17 | 1993-12-23 | Harris Corporation | Bonded wafer processing |
| US5780311A (en)* | 1992-06-17 | 1998-07-14 | Harris Corporation | bonded wafer processing |
| US5801084A (en)* | 1992-06-17 | 1998-09-01 | Harris Corporation | Bonded wafer processing |
| CN100510824C (en)* | 2005-02-10 | 2009-07-08 | 奔瑞公司 | Sealed tube coupling for optical fiber tubes |
| CN113675220A (en)* | 2020-07-30 | 2021-11-19 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
| EP3951847A1 (en)* | 2020-07-30 | 2022-02-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multilayer isolation structure for high voltage silicon-on-insulator device |
| TWI784571B (en)* | 2020-07-30 | 2022-11-21 | 台灣積體電路製造股份有限公司 | Integrated circuit device and method of forming the same |
| US11682578B2 (en) | 2020-07-30 | 2023-06-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multilayer isolation structure for high voltage silicon-on-insulator device |
| CN113675220B (en)* | 2020-07-30 | 2024-09-13 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0488657A (en) | 1992-03-23 |
| EP0469583A3 (en) | 1993-02-03 |
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