Die Erfindung bezieht sich auf eine Schaltungsanordung zum Betreiben eines ein- oder mehrphasigen Wechselsrichters, dessen Wechselspannungsausgang mit einer einen Primärstrom IP führenden Primärwicklung eines Transformators verbunden ist, wobei an zumindest einer einen Sekundärstrom IS führenden Sekundärwicklung des Transformators eine Last anschließbar ist und wobei die Schaltungsanordnung einen Regelkreis und eine Ansteuereinheit zur Pulsansteuerung von Leistungshalbleiterschaltern des Wechselrichters umfasst.The invention relates to a circuit arrangement for operating a single-phase or multi-phase inverter, the alternating voltage output of which is connected to a primary winding of a transformer carrying a primary current IP, a load being connectable to at least one secondary winding of the transformer carrying a secondary current IS , and wherein the circuit arrangement comprises a control circuit and a control unit for pulse control of power semiconductor switches of the inverter.
Derartige Wechselrichter sind aus dem Stand der Technik bekannt und werden vorwiegend in der Bahn-, Schiffs- und Automobiltechnik eingesetzt um aus einer durch das Bordnetz vorgegebenen Gleichspannung eine Wechselspannung bestimmter Frequenz und Amplitude zum Antrieb eines Wechselspannungsverbrauchers zu erzeugen.Such inverters are known from the prior art and are predominantlyused in rail, ship and automotive technology to create one through the electrical systempredetermined DC voltage an AC voltage of certain frequency and amplitudeto drive an AC voltage consumer.
Um die Ausgangswechselspannung des Wechselrichters anzupassen (vergrößern bzw. verkleinern) wird dem Ausgang des Wechselrichters ein Transformator nachgeschaltet, der die Ausgangswechselspannung des Wechselrichters auf einen angepaßten (höheren bzw. kleineren) Spannungswert transformiert.To adjust the output AC voltage of the inverter (enlarge or versmaller), a transformer is connected downstream of the output of the inverterOutput AC voltage of the inverter to an adapted (higher or smallren) voltage value transformed.
Die Eingangsspannung liegt üblicherweise im Bereich von 24 bis 750 VDC und kann auf Ausgangsspannungen im Bereich vom 220 bis 1500 VAC mit Frequenzen vom 16 2/3, 50 bis 400 Hz eingestellt werden.The input voltage is usually in the range from 24 to 750 VDC and can be set to Output voltages in the range from 220 to 1500 VAC with frequencies from 16 2/3, 50 to400 Hz can be set.
Insbesondere bei einer geringen Eingangsgleichspannung von ca. 24 VDC und einer Gesamtleistung des Wechselrichters von ca. 1 kW und mehr können Primärströme IP von 100 A und mehr fließen, die einen Gleichanteil aufweisen und den nachgeschalteten Transformator in die Sättigung treiben. Durch die Sättigung zeigt der Transformator ein unsymmetrisches Verhalten, das insgesamt den Wirkungsgrad des Wechselrichters erheblich verschlechtert und störende Netzrückwirkungen verursacht.In particular with a low DC input voltage of approx. 24 VDC and a total power of the inverter of approx. 1 kW and more, primary currents IP of 100 A and more can flow, which have a DC component and drive the downstream transformer into saturation. Due to the saturation, the transformer exhibits an asymmetrical behavior, which overall considerably reduces the efficiency of the inverter and causes disturbing grid effects.
Zur Ansteuerung eines Wechselrichters ist das Pulsweitenmodulationsverfahren (PWM-Verfahren) bekannt. Dabei ist zur Erzeugung einer Steuerspannung ein Vergleicher vorgesehen, dem ein Ist-Wert der ausgangsseitigen Wechselspannung und ein vorgegebener Soll-Wert eines Wechselspannungsverlaufs zum Vergleich zugeführt wird und dessen Ausgang mit einem Komparator verbunden ist, in dem die Steuerspannung mit einer sägezahnförmigen oder dreieckförmigen Vergleichsspannung zur Erzeugung von Ansteuersignalen für die Leistungshalbleiterschalter des Wechselrichters verglichen wird.To control an inverter, the pulse width modulation method (PWM verdrive) known. A comparator is provided to generate a control voltage,which is an actual value of the AC voltage on the output side and a predetermined target valuean AC voltage curve is supplied for comparison and its output witha comparator is connected in which the control voltage with a sawtoothor triangular reference voltage for generating control signals for thePower semiconductor switch of the inverter is compared.
Überschreitet jedoch die ermittelte Steuerspannung die sägezahn- oder dreieckförmige Vergleichsspannung, werden keine Ansteuersignale erzeugt, was zu einer Übermodulation führt und sich nachteilig auf den Stromflusswinkel bzw. Verlauf von Ausgangsspannung und/oder -strom auswirkt.However, the determined control voltage exceeds the sawtooth or triangular VerDC voltage, no control signals are generated, which leads to overmodulationand adversely affect the current flow angle or the course of the output voltage and / or-current affects.
Der vorliegenden Erfindung liegt das Problem zugrunde, eine Schaltungsanordnung und ein Verfahren zum Betreiben eines Wechselrichters derart weiterzubilden, so dass bei weitem Eingangsspannungsbereich und hohen Belastungen einerseits ein hoher Wirkungsgrad und andererseits ein stabiles Regelverhalten gewährleistet wird. Insbesondere soll ein am Ausgang des Wechselrichters liegender Transformator symmetrisch betrieben werden und die Schaltung soll beliebige Stromflusswinkel erfüllen.The present invention is based on the problem of a circuit arrangement and aDevelop methods of operating an inverter such that by farInput voltage range and high loads on the one hand high efficiency andon the other hand, a stable control behavior is guaranteed. In particular, one should be at the exitof the inverter lying transformer can be operated symmetrically and the circuitshould meet any current flow angle.
Das Problem wird durch eine Schaltungsanordnung einerseits dadurch gelöst, dass ein erstes Messelement zur Erfassung des Primärstroms IP und zweites Messelement zur Erfassung des Sekundärstrom IS vorgesehen ist, dass eine Regeldifferenz aus Primärstrom IP und Sekundärstrom IS einer überlagerten Spannungsregeleinrichtung zugeführt wird, dass ein Ausgang der Spannungsregeleinrichtung mit einem Vergleicher einer unterlagerten Stromregeleinrichtung verbunden ist, dass dem Vergleicher der Primärstrom IP als Strom-Istwert IPIST zugeführt wird und dass ein Ausgang der Stromregeleinrichtung mit einem Eingang der Ansteuereinheit verbunden ist.The problem is solved on the one hand by a circuit arrangement in that a first measuring element for detecting the primary current IP and a second measuring element for detecting the secondary current IS is provided, and a control difference between the primary current IP and the secondary current IS is fed to a superimposed voltage control device, that an output of the voltage control device is connected to a comparator of a subordinate current control device, that the primary current IP is supplied to the comparator as actual current value IPIST and that an output of the current control device is connected to an input of the control unit.
Andererseits wird das Problem dadurch gelöst, dass dass ein erstes Messelement zur Erfassung des Primärstromes IP und ein zweites Messelement zur Erfassung des Sekundärstroms IS vorgesehen ist, dass eine Regeldifferenz aus Primärstrom IP und Sekundärstrom IS einer überlagerten Spannungsregeleinrichtung zugeführt wird, dass eine Ausgangsgröße der Spannungsregeleinrichtung einer unterlagerten Stromregeleinrichtung zugeführt und mit dem Primärstrom IP als Strom-Istwert IPIST zur Anpassung an dessen Kurvenform verglichen wird, wobei beliebige Phasenwinkel ϕ und Kurvenformen des Ausgangsstromes bzw. Sekundärstromes IS zur Ausgangsspannung UA regelbar sind und dass ein Ausgang der Stromregeleinrichtung mit einem Eingang der Ansteuereinheit verbunden ist.On the other hand, the problem is solved in that a first measuring element for detecting the primary current IP and a second measuring element for detecting the secondary current IS is provided in that a control difference between the primary current IP and the secondary current IS is fed to a superimposed voltage control device that an output variable of the voltage regulating device is fed to a subordinate current regulating device and compared with the primary current IP as the actual current value IPIST for adaptation to its curve shape, any phase angle ϕ and curve forms of the output current or secondary current IS to the output voltage UA being controllable and that an output of the current control device is connected to an input of the control unit.
Durch die Erfassung der pimär- und sekundärseitigen Ströme IP, Is des Transformators kann eine Information über die symmetrische Auslastung des Transformators abgeleitet werden. Die Stromwerte werden wie beschrieben einer Regeleinrichtung zugeführt und als Störgrößenaufschaltung dem eingangsseitigen ersten Vergleicher zugeführt. Auf diese Weise wird eine dem Spannungsregler zuzuführende Regelabweichung beeinflusst, so dass eine in dem Transformator auftretende Unsymmetrie ausgeregelt wird. Ergänzend ist ein unterlagerter Stromregelkreis vorgesehen, dem der Primärstrom IP des Transformators als Ist-Wert und die Ausgangsgröße der ersten Regeleinrichtung als Soll-Wert zugeführt wird. Durch die erfindungsgemäße Anordnung können Unsymmetrien der Transformatorbelastung ausgeregelt werden. Durch den unterlagerten Stromregelkreis wird insgesamt eine stabile Regelung erreicht. Durch die Unterlagerung des Stromregelkreises kann die verstärkte Fehlerdifferenz des Spannungsregelkreises einer Kurvenform des Stromistwertes IPIST des Primärstroms angepasst werden. Der Primärstrom IPIST ist über dem Übersetzungsverhältnis ü des Tans formators mit dem Sekundärstrom IS und damit auch mit dem Ausgangsstrom verknüpft. Insbesondere müssen Ausgangsstrom und -spannung nicht in Phase liegen, so dass die Schaltung mit einem bliebigen Stromflusswinkel im Bereich von 0 ≦ cos ϕ ≦ ±1 betrieben werden kann. Es können beliebige Phasenwinkel ϕ und Kurvenformen des Ausgangsstromes zur Ausgangsspannung erfüllt werden.By detecting the primary and secondary currents IP , Is of the transformer, information about the symmetrical utilization of the transformer can be derived. As described, the current values are fed to a control device and fed to the input-side first comparator as a disturbance variable feed-in. In this way, a control deviation to be supplied to the voltage regulator is influenced, so that an asymmetry occurring in the transformer is corrected. In addition, a subordinate current control circuit is provided, to which the primary current IP of the transformer is supplied as the actual value and the output variable of the first control device as the target value. As a result of the arrangement according to the invention, asymmetries in the transformer load can be corrected. Overall, stable regulation is achieved by the subordinate current control loop. By superimposing the current control loop, the amplified error difference of the voltage control loop can be adapted to a curve shape of the actual current value IPIST of the primary current. The primary current IPIST is linked via the transmission ratio ü of the transformer with the secondary current IS and thus also with the output current. In particular, the output current and voltage do not have to be in phase, so that the circuit can be operated with a constant current flow angle in the range of 0 ≦ cos ϕ ≦ ± 1. Any phase angle ϕ and waveforms of the output current to the output voltage can be fulfilled.
Zur weiteren Verbesserung des Regelverhaltens ist vorgesehen, dass der Spannungsregler zur Begrenzung seines Ausgangssignal ein Rückkoppelglied aufweist, dessen Eingang mit dem Ausgang des Spannungsreglers und dessen Ausgang mit dem ersten Vergleicher verbunden ist. Das Ausgangssignal des Spannungsreglers dient als Soll-Wert für den nachgeschalteten Stromregler und wird mit dem Ist-Wert des Primärstroms IP verglichen. Die Begrenzung ist einstellbar.To further improve the control behavior, it is provided that the voltage regulator has a feedback element to limit its output signal, the input of which is connected to the output of the voltage regulator and the output of which is connected to the first comparator. The output signal of the voltage regulator serves as the target value for the downstream current regulator and is compared with the actual value of the primary current IP. The limitation is adjustable.
Um insbesondere im Leerlauffall einen stabilen Regelkreis zu erhalten, ist vorgesehen, dass dem Stromregler zur Resonanzdämpfung ein Rückkoppelglied, vorzugsweise ein LC-Filter zugeordnet ist.In order to maintain a stable control loop, especially when idling, it is provided thatthe current regulator for resonance damping a feedback element, preferably an LC filterassigned.
Bei einer bevorzugten Ausführungsform ist vorgesehen, dass die Messelemente zur Erfassung der Ströme IP und IS mit Eingängen eines zweiten Vergleichers verbunden sind und dass ein Ausgang des zweiten Vergleichers über einen Regler, vorzugsweise PI-Regler mit dem ersten Vergleicher des Spannungsreglers verbunden ist.In a preferred embodiment it is provided that the measuring elements for detecting the currents IP and IS are connected to inputs of a second comparator and that an output of the second comparator is connected to the first comparator of the voltage regulator via a regulator, preferably a PI regulator.
Zur Filterung der Ausgangsspannung des Wechselrichters wird vorgeschlagen, dass der Primärwicklung des Transformators zumindest eine Drosselspule in Reihe geschaltet ist, wobei die zumindest eine Drosselspule vorzugsweise integraler Bestandteil des Transformators ist. Auf diese Weise werden Anschlussklemmen eingespart, da mehrere Bauteile in einem vereinigt sind. Bei einer besonders bevorzugten Ausführungsform ist vorgesehen, dass der Primärwicklung des Transformators eine erste Drosselspule vorgeschaltet und eine zweite Drosselspule nachgeschaltet ist. Beide Drosselspulen sind dabei integraler Bestandteil des Transformators.To filter the output voltage of the inverter, it is proposed that thePrimary winding of the transformer at least one choke coil is connected in series,wherein the at least one choke coil is preferably an integral part of the transformators is. In this way, terminals are saved, since several components in oneare united. In a particularly preferred embodiment it is provided that thePrimary winding of the transformer upstream of a first choke coil and a secondChoke coil is connected downstream. Both choke coils are an integral part of theTransformer.
Vorzugsweise ist ein weiterer Kondensator als Filterelement vorgesehen, der parallel zu zumindest einer Sekundärwicklung angeschlossen ist. Hierzu ist anzumerken, dass dieser Kondensator nach dem Stand der Technik zwischen der zumindest einen Drosselspule und den Anschlüssen der Primärwicklung angeordnet ist. Durch die Verlagerung des Kondensators in den Senkundärstromkreis werden eine Vielzahl von Vorteilen erreicht. Insbesondere wird neben der Stabilisierung des Regelkreises das CV-Produkt verbessert wodurch ein Kondensator kleinerer Baugröße eingesetzt werden kann.A further capacitor is preferably provided as a filter element, which is parallel toat least one secondary winding is connected. It should be noted that thisState of the art capacitor between the at least one choke coil andthe connections of the primary winding is arranged. By moving the capacitorA number of advantages are achieved in the secondary circuit. In particularIn addition to the stabilization of the control loop, the CV product is improved, whereby a conSmaller size capacitor can be used.
Ferner bezieht sich die Erfindung auf ein Verfahren zum Betreiben eines Wechselrichtes, dessen Ausgangsspannung durch einen Transformator transformiert wird, wobei der Transformator eingangsseitig einen Primärstrom IP und ausgangsseitig einen Sekundärstrom IS führt, wobei ein Ausganggsspannungs-Ist-Wert des Transformators gemessen und zur Bildung einer Regelabweichung mit einem Ausgangsspannungs-Soll-Wert verglichen wird und wobei die Regelabweichung verstärkt und als Steuerspannung zur Erzeugung von pulsmodullierten Ansteuersignalen verwendet wird.The invention further relates to a method for operating an inverter, the output voltage of which is transformed by a transformer, the transformer carrying a primary current IP on the input side and a secondary current IS on the output side, an actual output voltage value of the transformer being measured and used Formation of a control deviation is compared with an output voltage target value and the control deviation is amplified and used as a control voltage for generating pulse-modulated control signals.
Das erfindungsgemäße Verfahren ist dadurch gekennzeichnet, dass der Primärstrom IP und der Sekundärstrom IS zur Bildung einer Störgröße gemessen, miteinander verglichen und mit der eingangsseitigen Regelabweichung verknüpft werden, dass die so gebildete Größe verstärkt und als Primärstrom-Soll-Wert IPSOLL zur Bildung einer Regelabweichung mit dem Primärstrom-Ist-Wert IPIST verknüpft und zur Bildung der Steuerspannung verknüpft wird.The method according to the invention is characterized in that the primary current IP and the secondary current IS are measured to form a disturbance variable, compared with one another and linked to the control deviation on the input side, that the quantity formed in this way is amplified and as the primary current target value IPSOLL for formation a control deviation is linked to the primary current actual value IPIST and is linked to form the control voltage.
Bei dem erfindungsgemäßen Verfahren wird ausgenutzt, dass die Differenz zwischen Primärstrom-Ist-Wert IPIST und Sekundärstrom-Ist-Wert ISIST ein Maß für die Unsymmetrie des Transformators ist. Durch die eingangsseitige Beaufschlagung des Regelkreises erfolgt eine Störgrößenaufschaltung der an dem Transformator auftretenden Spannungszeitflächen - Unsymmetrie, wodurch das Steuersignal zur Erzeugung der pulsweitenmodullierten Ansteuersignale der Leistungsschalter entsprechend verändert wird.In the methodaccording to the invention, use is made of the fact that the difference between the actual primary current value IPIST and the secondarycurrent actual value ISIST is a measure of the asymmetry of the transformer. By applying the control circuit on the input side, a disturbance variable is applied to the voltage time areas occurring on the transformer - asymmetry, as a result of which the control signal for generating the pulse-width-modulated control signals of the circuit breakers is changed accordingly.
Um zu verhindern, dass der Primärstrom IP einen vorgegebenen Wert überschreitet, ist vorgesehen, dass die den Primärstrom-Soll-Wert bildende Ausgangsgröße des eingangsseitigen Spannungsreglers begrenzt wird. Dazu wird das Ausgangssignal gemessen und über ein Rückkoppelglied zurückgeführt.In order to prevent the primary current IP from exceeding a predetermined value, it is provided that the output variable of the voltage regulator on the input side that forms the primary current target value is limited. For this purpose, the output signal is measured and fed back via a feedback element.
Durch die unterlagerte Stromregelung des Primärstroms IP kann der Regelkreis insgesamt stabilisiert werden. Auch wird der Vorteil erreicht, dass beliebige Stromflusswinkel 0 ≦ cos ϕ ≦ ±1 beherrschbar sind.The control circuit as a whole can be stabilized by the subordinate current control of the primary current IP. The advantage is also achieved that any current flow angle 0 ≦ cos ϕ ≦ ± 1 can be controlled.
Die Leistungsschalter des Wechselrichters werden nach dem Pulsweitenmodulationsverfahren (PWM-Verfahren) angesteuert. In diesem Zusammenhang ist besonders auf eine neuartige PWM-Steuerung mit symmetrischer Pulsweitenmodulation hinzuweisen, die einen eigenständigen erfinderischen Charakter aufweist.The circuit breakers of the inverter are based on the pulse width modulation method(PWM process). In this context, special attention is paid to a novelPWM control with symmetrical pulse width modulation to point out that ownhas a constant inventive character.
Aus dem Stand der Technik sind PWM-Steuerungen bekannt, die einen ersten Komparator zum Vergleich einer Steuerspannung mit einer Vergleichsspannung und einen zweiten Koparator zum Vergleich einer inversen Steuerspannung mit der Vergleichsspannung aufweisen, wobei an den Ausgängen der Komparatoren jeweils Steuersignale zur Ansteuerung von Leistungschaltern abgreifbar sind. Die hier beschriebene PWM-Steuerung ist dadurch gekennzeichnet, dass zur Ansteuerung von Leistungsschaltern zumindest eines Brückenzweiges zumindest eine Kippschaltung, mit einem Setzeingang und einem Rücksetzeingang vorgesehen ist, wobei ein Ausgang des ersten Komparators über zumindest ein UND-Gatter mit dem Rücksetzeingang und ein Ausgang des zweiten Komparators über zumindest ein UND-Gatter mit dem Setzeingang verbunden ist und wobei das dem Setzeingang zugeordnete UND-Gatter über einen Inverter und das dem Rücksetzeingang zugeordnete UND-Gatter direkt mit einem Ausgang einer Zählschaltung verbunden ist, an dem ein digitales Signal "H" anliegt, das mit der halben Frequenz der Vergleichsspannung schwingt.PWM controls are known from the prior art, which have a first comparatorto compare a control voltage with a reference voltage and a second oneCoparator for comparing an inverse control voltage with the reference voltagehave, wherein at the outputs of the comparators control signals for controlcan be tapped from circuit breakers. This is the PWM control described herecharacterized in that for controlling circuit breakers at least one bridgebranch at least one flip-flop, with a set input and a reset inputis provided, with an output of the first comparator via at least one AND gatewith the reset input and an output of the second comparator via at least oneAND gate is connected to the set input and the associated with the set inputAND gate via an inverter and the AND gate assigned to the reset inputis directly connected to an output of a counter circuit at which a digital signal "H"is applied, which vibrates at half the frequency of the reference voltage.
Um Pulsaussetzer für den Fall auszuschließen, wenn die Steuerspannung die Vergleichsspannung überschreitet, ist vorgesehen, dass die Ausgänge der Komparatoren über einen Inverter jeweils mit einem Eingang eines UND-Gatters verbunden sind, dessen Ausgang mit jeweils einem Eingang eines ODER-Gatters verbunden ist, wobei ein Ausgang des dem ersten Komparator zugeordneten ODER-Gatters mit einem Eingang des dem Rücksetzeingang zugeordneten UND-Gatters der ersten Kippschaltung und mit einem Eingang eines dem Setzeingang der zweiten Kippschaltung zugeordneten UND-Gatters verbunden ist und wobei ein Ausgang des dem zweiten Komparators zugeordneten ODER-Gatters mit einem Eingang des dem Setzeingang der ersten Kippschaltung zugeordneten UND-Gatters und mit einem Eingang eines dem Rücksetzeingang der zweiten Kippschaltung zugeordneten UND-Gatters verbunden ist.To rule out pulse dropouts in the event when the control voltage comparesvoltage exceeds, it is provided that the outputs of the comparators via aInverters are each connected to an input of an AND gate, the output of whicheach connected to an input of an OR gate, an output of the first Comparator associated OR gate with an input of the reset inputassigned AND gate of the first trigger circuit and with an input of theSet input of the second flip-flop associated AND gate is connected and whereinan output of the OR gate assigned to the second comparator with one inputof the AND gate assigned to the set input of the first trigger circuit and with aInput of an AND gate assigned to the reset input of the second trigger circuitconnected is.
Dabei sind die UND-Gatter mit einem Ausgang der Zählschaltung verbunden, an dem ein digitales Signal "MIN" anliegt, das bei einem vorgebbaren minimalen Zählerstand den logischen Pegel "LOW" einnimmt und wobei ein Eingang des ODER-Gatters mit einem Ausgang der Zählschaltung verbunden ist, an dem ein digitales Signal "MAX" anliegt, das bei einem vorgebbaren maximalen Zählerstand den logischen Pegel "HIGH" einnimmt.The AND gates are connected to an output of the counter circuit at which onedigital signal "MIN" is present, which with a predeterminable minimum counter readinglogic level "LOW" and where an input of the OR gate with aOutput of the counter circuit is connected to which a digital signal "MAX" is present, which ata logical maximum "HIGH" level.
Des Weiteren ist vorgesehen, dass ein Ausgang der Zählschaltung mit einem Steuereingang des Spannungsgenerators zum Setzen und Rücksetzen der sägezahnförmigen Vergleichsspannung verbunden ist.Furthermore, it is provided that an output of the counter circuit with a control inputof the voltage generator for setting and resetting the sawtooth comparisonvoltage is connected.
Dabei ist vorgesehen, dass die Zählschaltung vorzugsweise als 8-Bit-Zähler ausgebildet ist, um eine ausreichende Auflösung zu erhalten.It is provided that the counter circuit is preferably designed as an 8-bit counter,to get a sufficient resolution.
Auch bezieht sich die Erfindung auf ein Verfahren zur Erzeugung von pulsweitenmodullierten Signalen zur Ansteuerung von Leistungsschaltern zumindest eines Brückenzweiges eines Pulswechselrichters, wobei eine sägezahnförmige Vergleichsspannung mit einer Steuerspannung und einer inversen Steuerspannung zur Erzeugung von Ansteuerimpulsen verglichen wird und wobei erste Ansteuerimpulse erzeugt werden, wenn die Vergleichsspannung betragsmäßig größer als die Steuerspannung ist und zweite Ansteuerimpulse erzeugt werden, wenn die Vergleichsspannung betragsmäßig größer als die inverse Steuerspannung ist.The invention also relates to a method for generating pulse-width-modulatedSignals for controlling circuit breakers of at least one bridge branch of a pulseinverter, with a sawtooth reference voltage with a control voltageand an inverse control voltage for generating drive pulses is compared andwherein first drive pulses are generated when the comparison voltage is absoluteis greater than the control voltage and second drive pulses are generated when theComparative voltage is greater in magnitude than the inverse control voltage.
Dabei ist erfindungsgemäß vorgesehen, dass die Leistungsschalter simultan angesteuert werden, wobei das Setzen eines ersten Leistungsschalters das Rücksetzen eines zweiten Leistungsschalters bewirkt und wobei das Setzen der Leistungsschalter über eine ansteigende Flanke des ersten Impulses und das Rücksetzen über eine ansteigende Flanke des zweiten Impulses erfolgt. Durch das erfindungsgemäße Ansteuerverfahren wird der Vorteil erreicht, dass eine symmetrische Ansteuerung der Leistungsschalter ermöglicht wird. Insbesondere wird sowohl die Einschalt- als auch Ausschaltflanke der Leistungsschalter bei Veränderung des Spannungswertes der Steuerspannung variiert.It is provided according to the invention that the circuit breakers are activated simultaneouslybe, the setting of a first circuit breaker resetting a second Circuit breaker causes and the setting of the circuit breaker via a risingEdge of the first pulse and resetting via a rising edge of the secondImpulse occurs. The control method according to the invention achieves the advantage thatthat a symmetrical control of the circuit breaker is made possible. In particularboth the switch-on and switch-off edges of the circuit breakers when changedthe voltage value of the control voltage varies.
Um zu erreichen, dass bei einer Brückenschaltung die Leistungsschalter eines Brückenzweigs nach jeder zweiten Periode der Vergleichsspannung umgeschaltet werden, ist vorgesehen, dass die von den Komparatoren erzeugten Ansteuerimpulse mit einem digitalen Signal "H" der halben Frequenz der Vergleichsspannung logisch UND-verknüpft werden, wobei ein dem positiven Pol einer Brückenschaltung zugeordneter Leistungsschalter nur dann gesetzt werden kann, wenn das Signal "H" den logischen Pegel "LOW" aufweist und ein dem negativen Pol der Brückenschaltung zugeordneter Leistungsschalter nur dann gesetzt werden kann, wenn das Signal "H" den logischen Pegel "HIGH" aufweist.To achieve that the circuit breakers of a bridge branch in a bridge circuitare switched after every second period of the reference voltage, it is provided thatthe drive pulses generated by the comparators with a digital signal "H"half frequency of the reference voltage are logically AND-linked, one of whichonly then positive circuit breaker assigned to a bridge circuit can be setcan if the signal "H" has the logic level "LOW" and a negative polethe circuit breaker associated circuit breaker can only be set if thatSignal "H" has the logic level "HIGH".
Insgesamt werden die Leistungsschalter mit einer Frequenz angesteuert, die der Hälfte der Frequenz der Vergleichsspannung entspricht. Auf diese Weise können die Schaltverluste reduziert werden. Auch ergeben sich Vorteile bezüglich der durch die Schaltvorgänge erzeugten Oberwellen.Overall, the circuit breakers are controlled with a frequency that is half theFrequency corresponds to the reference voltage. In this way, the switching lossesbe reduced. There are also advantages with regard to those generated by the switching operationsth harmonics.
Um Schaltaussetzer bei hohen, d. h. die Vergleichsspannung überschreitenden Steuerspannungen zu verhindern, wird bei einem vorgebbaren minimalen Zählerstand ein logisches Signal "MIN" erzeugt, dass mit den Ansteuersignalen logisch UND-verknüpft wird und bei einem vorgebbaren maximalen Zählerstand ein logisches Signal "MAX" erzeugt, das mit den Ansteuersignalen ODER-verknüpft wird.To avoid misfires at high, d. H. control voltage exceeding the reference voltagea logical signal at a predeterminable minimum counter reading"MIN" generates that the control signals are logically AND-linked and at onePredeterminable maximum counter reading generates a logical signal "MAX", which with the Ancontrol signals OR-linked.
Weitere Einzelheiten, Vorteile und Merkmale der Erfindung ergeben sich nicht nur aus den Ansprüchen, den diesen zu entnehmenden Merkmalen - für sich und/oder in Kombination -, sondern auch aus der nachfolgenden Beschreibung eines den Zeichnungen zu entnehmenden bevorzugten Ausführungsbeispiels.Further details, advantages and features of the invention result not only from theClaims, the features to be extracted from these - individually and / or in combination -,but also from the following description of one of the drawingspreferred embodiment.
Es zeigen:Show it:
Fig. 1 einen Wechselrichter mit zugehörigem Regelkreis,Fig. 1 is an inverter with an associated control circuit,
Fig. 2 ein Blockschaltbild einer PWM-Steuerung undFig. 2 is a block diagram of a PWM controller and
Fig. 3 Signalverläufe von logischen Signalen der PWM-Steuerung gemäßFig. 2.Fig. 3 waveforms of logic signals of the PWM control in accordance withFIG. 2.
InFig. 1 ist eine Schaltungsanordnung10 zum Betreiben eines Wechselrichters12 mit nachgeschaltetem Transformator14 dargestellt.InFig. 1, a circuit arrangement10 is shown for the operation of an inverter12 having a downstream transformer14.
Der Wechselrichter12 ist in dem hier dargestellten Ausführungsbeispiel als Brückenschaltung ausgebildet und weist einen ersten Brückenzweig16 mit Leistungsschaltern T1, T2 und einen zweiten Brückenzweig18 mit Leistungsschaltern T3, T4 auf. Die Leistungsschalter T1-T4 sind als NPN-Transistoren wie z. B. FET's oder IGBT's ausgebildet, wobei die Leistungsschalter T1, T3 mit ihrem Kollektor an einem positiven Pol20 einer die Eingangsspannung UE liefernden Spannungsquelle und die Leistungsschalter T2, T4 jeweils mit ihrem Emitteranschluss mit einem negativen Pol22 der Spannungsquelle verbunden sind. Parallel zu den Leistungsschaltern T1-T4 ist jeweils eine Freilaufdiode24,26,28,30 bezogen auf die Leitstrecke der Transistoren T1-T4 antiparallel geschaltet. Ferner weisen die Leistungsschalter T1-T4 Steuereingänge32,34,36,38 auf, die mit Ausgängen einer PWM-Steuerung40 verbunden sind.In the exemplary embodiment shown here, the inverter12 is designed as a bridge circuit and has a first bridge branch16 with circuit breakers T1, T2 and a second bridge branch18 with circuit breakers T3, T4. The circuit breakers T1-T4 are as NPN transistors such. B. FET's or IGBT's are formed, the power switches T1, T3 with their collector on a positive pole20 of an input voltage UE supplying voltage source and the power switches T2, T4 each having their emitter connection with a negative pole22 of the voltage source. In parallel with the circuit breakers T1-T4, a free-wheeling diode24 ,26 ,28 ,30 is connected antiparallel with respect to the routing of the transistors T1-T4. Furthermore, the power switches T1-T4 have control inputs32 ,34 ,36 ,38 , which are connected to outputs of a PWM controller40 .
Zur Glättung der Eingangsspannung UE ist zwischen dem positiven Pol20 und dem negativen Pol22 der Spannungsquelle ein Kondensator42 angeordnet.A capacitor42 is arranged between the positive pole20 and the negative pole22 of the voltage source to smooth the input voltage UE.
Eine Mittelanzapfung44 zwischen dem Leistungsschalter T1 und dem Leistungsschalter T2 bildet einen ersten Ausgang des Wechselrichters12, der über eine Drosselspule46 mit einem ersten Anschluss48 einer Primärwicklung50 des Transformators14 verbunden ist. Eine Mittelanzapfung52 zwischen dem Leistungsschalter T3 und dem Leistungsschalter T4 bildet einen zweiten Ausgang des Wechselrichters12, der über eine zweite Drosselspule54 mit einem zweiten Anschluss56 der Primärwicklung50 des Transformators14 verbunden ist. Zur Erfassung des durch die Primärwicklung50 fließenden Primärstroms IP ist ein Messelement58 vorgesehen.A center tap44 between the circuit breaker T1 and the circuit breaker T2 forms a first output of the inverter12 , which is connected via a choke coil46 to a first connection48 of a primary winding50 of the transformer14 . A center tap52 between the circuit breaker T3 and the circuit breaker T4 forms a second output of the inverter12 , which is connected via a second choke coil54 to a second connection56 of the primary winding50 of the transformer14 . A measuring element58 is provided to detect the primary current IP flowing through the primary winding50 .
Der Transformator14 weist in dem hier dargestellten Ausführungsbeispiel zwei Sekundärwicklungen60,62 auf, die über eine Verbindung64 zu einer einzigen Sekundärwicklung verbunden sind. Es kann auch eine einzige Sekundärwicklung vorgesehen sein. Ein erster Anschluss66 der Sekundärwicklung60 bildet einen ersten Pol68 und ein weiterer Anschluss70 der Senkundärwicklung62 bildet einen zweiten Pol72 der Ausgangsspannung UA. Parallel zu der Reihenschaltung aus Senkundärwicklung60 und Senkundärwicklung62 ist ein Kondensator74 angeordnet, der zusammen mit den Drosselspulen46,54 einen Filter bildet. Zur Erfassung des Senkundärstroms IS ist ein Messelement76 vorgesehen.In the exemplary embodiment shown here, the transformer14 has two secondary windings60 ,62 which are connected via a connection64 to a single secondary winding. A single secondary winding can also be provided. A first connection66 of the secondary winding60 forms a first pole68 and a further connection70 of the secondary winding62 forms a second pole72 of the output voltage UA. In parallel to the series connection of secondary winding60 and secondary winding62 , a capacitor74 is arranged, which together with the choke coils46 ,54 forms a filter. A measuring element76 is provided to detect the secondary current IS.
Die Schaltungsanordnung10 zum Betreiben des Wechselrichters12 mit zugeordnetem Transformator14 besteht aus einem Regelkreis78 und der oben erwähnten PWM-Steuerung40. Erfindungsgemäß weist der Regelkreis78 eine überlagerte Spannungsregeleinrichtung80 auf, die aus einem Vergleicher82 und einem Spannungsregler84 besteht. Dem Vergleicher82 wird ein Ausgangsspannungs-Soll-Wert UASOLL sowie ein Ausgangsspannungs-Ist-Wert UAIST zugeführt. Ferner ist der Vergleicher82 mit dem Ausgang einer Stromregeleinrichtung86 verbunden, in der aus dem gemessenen Primärstrom-Ist-Wert IPIST und Sekundärstrom-Ist-Wert ISIST eine Regeldifferenz als Störgröße ermittelt wird. Die Stromregeleinrichtung86 besteht aus einem mit den Messelementen58 und76 verbundenen zweiten Vergleicher88 und einem Stromregler90.The circuit arrangement10 for operating the inverter12 with an associated transformer14 consists of a control circuit78 and the above-mentioned PWM controller40 . According to the invention, the control circuit78 has a superimposed voltage controldevice80 , which consists of a comparator82 and a voltage regulator84 . An output voltage setpoint value UASOLL and an actual output voltage value UAIST are fed to the comparator82 . Furthermore, the comparator82 is connected to the output of a current control device86 , in which a control difference is determined as a disturbance variable from the measured primary current actual value IPIST and secondary current actual value ISIST . The current control device86 consists of a second comparator88 connected to the measuring elements58 and76 and a current controller90 .
Ein Ausgang92 des Spannungsreglers84 ist über ein Rückkoppelglied94 mit dem Vergleicher82 verbunden. Dadurch wird eine Begrenzung eines am Ausgang anliegenden Ausgangssignals, das einen Soll-Wert für den Primärstrom IP bildet, begrenzt.An output92 of the voltage regulator84 is connected via a feedback element94 to the comparator82 . This limits the limitation of an output signal present at the output, which forms a target value for the primary current IP.
Der überlagerten Spannungsregeleinrichtung80 ist eine unterlagerte Stromregeleinrichtung96 nachgeschaltet, die aus einem Vergleicher98 und einem Stromregler100 besteht. Der Vergleicher98 ist mit dem Ausgang92 des Spannungsreglers84 verbunden. Ferner wird dem Vergleicher98 der Primärstrom-Ist-Wert IPIST zugeführt. Der Ausgang des Stromreglers100 ist über ein Rückkoppelglied102, das vorzugsweise als Filter zur Resonanzdämpfung ausgebildet ist, mit dem Vergleicher98 und mit einem Steuereingang der PWM-Steuerung40 verbunden.The superimposed voltage control device80 is followed by a subordinate current control device96 , which consists of a comparator98 and a current controller100 . The comparator98 is connected to the output92 of the voltage regulator84 . Furthermore, the primary current actual value IPIST is fed to the comparator98 . The output of the current regulator100 is connected to the comparator98 and to a control input of the PWM controller40 via a feedback element102 , which is preferably designed as a filter for resonance damping.
Die beschriebene Schaltungsanordnung10 zeichnet sich durch die Messelemente58,76 zur Erfassung des Primärstroms IP und des Sekundärstroms IS aus, wobei aus den ermittelten Messgrößen eine Regelabweichung berechnet und im Stromregler90 verstärkt wird, die dem Vergleicher88 als Störgrößenaufschaltung zugeführt wird. Die auf diese Art ermittelte Störgröße ist ein Maß für die unsymmetrische Auslastung des Transformators14. Zusammen mit dem Ausgangsspannungs-Soll-Wert UASOLL und dem Ausgangsspannungs-Ist-Wert UAIST wird eine Regelabweichung zur Verfügung gestellt, die von dem Spannungsregler84 verstärkt wird. Damit die verstärkte Regeldifferenz einen bestimmten Wert nicht überschreitet, ist die Begrenzung94 in Form eines Rückkoppelgliedes vorgesehen. Der Wert der Begrenzung kann vorzugsweise eingestellt werden. Die so ermittelte Größe IPSOLL dient als Soll-Wert für den Primärstrom IP und wird in dem Vergleicher98 mit dem Primärstrom-Ist-Wert IPIST Zur Bildung einer Regeldifferenz verknüpft. Die so gebildete Regeldifferenz wird dem Stromregler100 zur Verstärkung zugeführt und zur Regelkreisstabilisierung über den Filter102 auf den Vergleicher98 zurückgeführt. Am Ausgang101 des Stromreglers100 ist eine im wesentlichen sinusförmige Steuerspannung als PWM-Steuersignal abgreifbar.The circuit arrangement10 described is characterized by the measuring elements58 ,76 for detecting the primary current IP and the secondary current IS , a control deviation being calculated from the measured variables determined and amplified in the current controller90 , which is fed to the comparator88 as a disturbance variable application. The disturbance variable determined in this way is a measure of the asymmetrical utilization of the transformer14 . Together with the output voltage target value UASOLL and the output voltage actual value UAIST , a control deviation is made available, which is amplified by the voltage regulator84 . So that the amplified control difference does not exceed a certain value, the limit94 is provided in the form of a feedback element. The value of the limitation can preferably be set. The quantity IPSOLL determined in thisway serves as the target value for the primary current IP and is linked in the comparator98 with the primary current actual value IPIST in order to form a control difference. The control difference thus formed is fed to the Stromreg controller100 for amplification and fed back to the comparator98 via the filter102 for stabilizing the control loop. At the output101 of the current regulator100 , a sinusoidal control voltage can be tapped as a PWM control signal.
Die am Ausgang101 der Regeleinrichtung96 anliegende Steuerspannung kann mit unsymmetrischen Schwankungen behaftet sein. Bei herkömmlichen PWM-Steuerungen führen diese Spannungsschwankungen dazu, dass die Leistungsschalter T1-T4 fehlerhaft bzw. nicht angesteuert werden. Dies führt zu unerwünschten Netzrückwirkungen und verschlechtert den Wirkungsgrad des Wechselrichters.The control voltage applied to the output101 of the control device96 can be subject to asymmetrical fluctuations. In conventional PWM controls, these voltage fluctuations cause the circuit breakers T1-T4 to be activated incorrectly or not. This leads to undesirable grid repercussions and deteriorates the efficiency of the inverter.
Daher wird erfindungsgemäß eine PWM-Steuerung40 mit symmetrischer Pulsweitenmodulation vorgeschlagen. Der Aufbau der erfindungsgemäßen PWM-Steuerung40 wird anhand vonFig. 2 näher erläutert.A PWM controller40 with symmetrical pulse width modulation is therefore proposed according to the invention. The structure of the PWM controller40 according to the invention is explained in more detail with reference toFIG. 2.
Die PWM-Steuerung40 umfasst im wesentlichen einen ersten Komparator104, einen zweiten Komparator106, einer Ansteuereinheit108 für die Leistungsschalter T1 und T2, eine Ansteuereinheit110 für die Leistungsschalter T3 und T4, einen Spannungsgenerator112 zur Erzeugung einer Vergleichsspannung sowie eine Signalgeberschaltung114 mit zugehörigem Taktgenerator116.The PWM controller40 essentially comprises a first comparator104 , a second comparator106 , a control unit108 for the circuit breakers T1 and T2, a control unit110 for the circuit breakers T3 and T4, a voltage generator112 for generating a comparison voltage, and a signal generator circuit114 with associated clock generator116 .
Ein positiver Eingang118 des ersten Komparators104 bildet den Eingang der PWM-Steuerung40 und ist unmittelbar mit dem Ausgang101 verbunden, an dem die Steuerspannung USTEUER anliegt. Ein positiver Eingang120 des zweiten Komparators106 ist über eine Inverterschaltung122 mit der Steuerspannung verbunden, so dass an dem Eingang120 die invertierte Steuerspannung /USTEUER anliegt (/wird im folgenden als Negationszeichen verwendet). Ein Ausgang123 des Spannungsgenerators112 liegt über einem Kondensator124 zur Tiefpassfilterung jeweils an einem negativen Eingang126,128 der Komperatoren104,106. Des Weiteren ist zur Tiefpassfilterung ein Widerstand130 vorgesehen, der die negativen Eingänge126,128 mit Massepotential verbindet. Zum Setzen und Rücksetzen einer generierten Sägezahnspannung ist der Spannungsgenerator112 mit einem Ausgang132 der Zählschaltung114 verbunden.A positive input118 of the first comparator104 forms the input of the PWM controller40 and is directly connected to the output101 , at which the control voltage UCONTROL is applied. A positive input120 of the second comparator106 is connected to the control voltage via an inverter circuit122 , so that the inverted control voltage / UCONTROL is present at the input120 (/ is used in the following as anegative sign ). An output123 of the voltage generator112 is connected to a negative input126 ,128 of the comparators104 ,106 via a capacitor124 for low-pass filtering. Furthermore, a resistor130 is provided for low-pass filtering, which connects the negative inputs126 ,128 to ground potential. To set and reset a generated sawtooth voltage, the voltage generator112 is connected to an output132 of the counter circuit114 .
Die Komparatoren104,106 weisen jeweils einen Ausgang134,136 auf, der über jeweils ein Invertergatter138,140 mit einem Eingang142,144 eines Und-Gatters146,148 verbunden ist. Ein weiterer Eingang150,152 des Und-Gatters146,148 ist mit einem Ausgang154 der Signalgeberschaltung114 verbunden. An dem Ausgang154 liegt ein digitales Signal "MIN" an, das einen Pegel "HIGH" annimmt, wenn ein in die Signalgeberschaltung integrierter Zähler einen Mindestwert überschritten hat. Ein Ausgang156,158 des Und-Gatters146,148 ist mit einem Eingang160,162 eines Oder-Gatters164,166 verbunden. Ein weiterer Eingang168,170 des Oder-Gatters164,166 ist mit einem Ausgang172 der Signalgeberschaltung verbunden, an dem ein digitales Signal "MAX" anliegt, das dann den Pegel "HIGH" einnimmt, wenn ein bestimmter maximaler Zählerstand errreicht ist. Das Signal "MAX" wird am Ende einer Periode der Vergleichsspannung zurückgesetzt.The comparators104 ,106 each have an output134 ,136 , which is connected via an inverter gate138 ,140 to an input142 ,144 of an AND gate146 ,148 . Another input150 ,152 of the AND gate146 ,148 is connected to an output154 of the signal generator circuit114 . A digital signal "MIN" is present at output154 , which assumes a "HIGH" level when a counter integrated in the signal transmitter circuit has exceeded a minimum value. An output156 ,158 of the AND gate146 ,148 is connected to an input160 ,162 of an OR gate164 ,166 . Another input168 ,170 of the OR gate164 ,166 is connected to an output172 of the signal generator circuit, to which a digital signal "MAX" is present, which then assumes the level "HIGH" when a certain maximum counter reading has been reached. The signal "MAX" is reset at the end of a period of the reference voltage.
Ein Ausgang174 des Oder-Gatters164 ist mit einem Eingang176 eines Und-Gatters178 verbunden, dessen Ausgang mit einem Rücksetzeingang180 der Ansteuereinheit108 für die Leistungsschalter T1 und T2 verbunden ist. Ein weiterer Eingang182 des Und-Gatters178 ist mit einem Ausgang184 verbunden, an dem ein digitales Signal "H" anliegt, das die halbe Frequenz der Vergleichssägezahnspannung aufweist. Des Weiteren ist der Ausgang174 des Oder-Gatters164 mit einem Eingang186 eines Und-Gatters188 verbunden, dessen Ausgang mit dem Rücksetzeingang190 der Ansteuereinheit110 für die Leistungsschalter T3 und T4 verbunden ist.An output174 of the OR gate164 is connected to an input176 of an AND gate178 , the output of which is connected to a reset input180 of the control unit108 for the circuit breakers T1 and T2. Another input182 of the AND gate178 is connected to an output184 , to which a digital signal "H" is present, which has half the frequency of the comparative sawtooth voltage. Furthermore, the output174 of the OR gate164 is connected to an input186 of an AND gate188 , the output of which is connected to the reset input190 of the control unit110 for the circuit breakers T3 and T4.
Ein Ausgang192 des Oder-Gatters166 ist einerseits mit einem Eingang194 eines Und-Gatters196 verbunden, dessen Ausgang mit einem Rücksetzeingang198 der Ansteuerschaltung110 verbunden ist. Andererseits liegt der Ausgang192 des Oder-Gatters166 an einem Eingang200 eines Und-Gatters202, dessen Ausgang mit einem Setzeingang204 der Ansteuereinheit108 für die Leistungsschalter T1 und T2 verbunden ist. Ein weiterer Eingang206 des Und-Gatters202 ist über einen Inverter208 mit dem Ausgang184 verbunden. Gleiches gilt für einen Ausgang210 des Und-Gatters188, der über einen Inverter212 mit dem Ausgang184 verbunden ist. Ferner ist ein Eingang214 des Und-Gatters196 mit dem Ausgang184 verbunden.An output192 of the OR gate166 is connected on the one hand to an input194 of an AND gate196 , the output of which is connected to a reset input198 of the control circuit110 . On the other hand, the output192 of the OR gate166 is connected to an input200 of an AND gate202 , the output of which is connected to a set input204 of the control unit108 for the circuit breakers T1 and T2. Another input206 of the AND gate202 is connected to the output184 via an inverter208 . The same applies to an output210 of the AND gate188 , which is connected to the output184 via an inverter212 . Furthermore, an input214 of the AND gate196 is connected to the output184 .
Die Funktionsweise der PWM-Steuerung40 gemäßFig. 2 soll unter Bezugnahme auf die inFig. 3 dargestellten Signalverläufe erläutert werden.The mode of operation of the PWM controller40 according toFIG. 2 will be explained with reference to the signal profiles shown inFIG. 3.
InFig. 3a ist der Verlauf des Signals "H" dargestellt, das an dem Ausgang184 der Signalschaltung114 abgreifbar ist. In dem hier dargestellten Ausführungsbeispiel ist die Signalschaltung114 als 8-Bit-Zähler ausgebildet, wobei das Signal "H" den Pegel des Bits mit der höchsten Wertigkeit darstellt.InFig. 3a, the course of the signal "H" is shown, which can be tapped at the output184 of the signal circuit114 . In the embodiment shown here, the signal circuit114 is designed as an 8-bit counter, the signal "H" representing the level of the bit with the highest significance.
InFig. 3b ist einerseits der Verlauf der sägezahnförmigen Vergleichsspannung UVERGL und andererseits sind die Verläufe von Steuerspannung USTEUER und der inversen Steuerspannung /USTEUER dargestellt.FIG. 3b shows on the one hand the course of the sawtooth-shaped comparison voltage UVERGL and on the other hand the courses of the control voltage UCONTROL and the inverse control voltage / UCONTROL .
Übersteigt der Wert der Vergleichsspannung UVERGL den Wert der Steuerspannung USTEUER, ändert sich der Ausgangspegel am Ausgang des ersten Komparators104, der von dem Inverter138 invertiert wird. Ein entsprechender Signalverlauf /KOMP1 ist inFig. 3c dargestellt.If the value of the comparison voltage UVERGL exceeds the value of the control voltage UCONTROL , the output level at the output of the first comparator104 changes , which is inverted by the inverter138 . A corresponding signal curve / KOMP1 is shown inFig. 3c Darge.
Überschreitet die Vergleichsspannung UVERGL die inverse Steuerspannung /USTEUER, so ändert sich das Ausgangssignal des zweiten Komparators106, das ebenfalls durch den Inverter140 invertiert wird und als Signal /KOMP2 inFig. 3d dargestellt ist.If the comparison voltage UVERGL exceeds the inverse control voltage / UCONTROL , the output signal of the second comparator106 changes , which is also inverted by the inverter140 and is shown as the signal / COMP2 inFIG. 3d.
Die Signale /KOMP1 und /KOMP2 dienen zur symmetrischen Ansteuerung der Leistungsschalter T1-T4 des Wechselrichters12. Dabei ist vorgesehen, dass eine ansteigende Flanke des Signals /KOMP1 einen ersten Umschaltvorgang in dem Brückenzweig16 mit den Leistungsschaltern T1 und T2 auslöst und dass eine ansteigende Flanke des Signals /KOMP2 einen zweiten Umschaltvorgang der Leistungsschalter T1 und T2 in dem Brückenzweig16 auslöst. Um zu erreichen, dass bei einer Vollbrückenschaltung ein Umschaltvorgang eines Brückenzweiges bei jeder zweiten Periode der Vergleichsspannung UWRGL erzeugt wird, ist vorgesehen, dass die Signale /KOMP1 und /KOMP2 mit dem Signal "H" logisch verknüpft werden. So wird z. B. ein Ausschaltvorgang des Leistungsschalters T 1 des Brückenzweigs16 nur dann eingeleitet, wenn bei ansteigender Flanke des Signals /KOMP1 das Signal "H" den logischen Pegel "HIGH" aufweist. In einer folgenden Periode erfolgt ein Umschaltvorgang in den Leistungsschalter T3, T4 des Brückenzweigs18, wobei bei einer ansteigenden Flanke des Signals /KOMP1 und bei einem logischen Pegel "LOW" des Signals "H" ein Einschaltvorgang des Leitungsschalters T4 eingeleitet wird.The signals / KOMP1 and / KOMP2 serve for the symmetrical control of the circuit breakers T1-T4 of the inverter12 . It is provided that a rising edge of the signal / KOMP1 triggers a first switching process in the bridge branch16 with the circuit breakers T1 and T2 and that a rising edge of the signal / KOMP2 triggers a second switching process of the circuit breakers T1 and T2 in the bridge branch16 . In order to ensure that a switching operation of a bridge arm is generated every other period of the comparison voltage UWRGL in a full bridge circuit, it is provided that the signals / KOMP1 and / KOMP2 are logically combined with the signal "H". So z. B. initiated a turn-off of the circuit breaker T 1 of the bridge branch16 only when the signal "H" has the logic level "HIGH" on a rising edge of the signal / KOMP1. In a subsequent period, a switchover occurs in the circuit breaker T3, T4 of the bridge branch18 , with a switch-on operation of the line switch T4 being initiated on a rising edge of the signal / KOMP1 and at a logic level "LOW" of the signal "H".
Dieses Ansteuerverfahren zeichnet sich besonders dadurch aus, dass beide Flanken der Umschaltvorgänge der Leistungsschalter eines Brückenzweiges durch Veränderung der Steuerspannung USTEUER im wesentlichen symmetrisch bezogen auf eine abfallende Flanke der sägezahnförmigen Vergleichsspannung variiert werden. Dieser Effekt kann insbesondere bei hohen Steuerspannungen ausgenutzt werden.This control method is characterized in particular by the fact that both edges of the switching operations of the circuit breakers of a bridgearm are varied essentially symmetrically with respect to a falling edge of the sawtooth-shaped reference voltage by changing the control voltage UCONTROL . This effect can be exploited in particular at high control voltages.
Überschreitet die Steuerspannung USTEUER zum Beispiel den maximalen Wert der Vergleichsspannung UVERGL, werden von den Komperatoren104 bzw.106 keine Signale erzeugt, so dass eine Ansteuerung der Leistungsschalter nicht erfolgt, was zu Pulsaussetzern führt.If the control voltage UCONTROL exceeds, for example, the maximum value of the comparison voltage UCOMP , no signals are generated by the comparators104 or106 , so that the circuit breakers are not activated, which leads to pulse dropouts.
Um derartige Pulsaussetzer beim Überschreiten der Steuerspannung über den Wert der Vergleichsspannung zu verhindern, wird kurz vor dem Rücksetzen der Vergleichsspannung ein digitales Signal "MAX" gemäßFig. 3e erzeugt. Des Weiteren wird kurz nach dem Setzen der Vergleichsspannung ein digitales Signal "MIN" erzeugt. Dabei ist vorgesehen, dass das digitale Signal "MIN" jeweils mit den Signalen /KOMP1 und /KOMP2 über ein logisches UND-Gatter146,148 verknüpft wird. Ein am Ausgang des UND-Gatters146,148 liegendes Signal wird sodann mit dem digitalen Signal "MAX" logisch ODER-verknpüft, so dass auf diese Art und Weise sichergestellt ist, dass ein erster Umschaltvorgang in einem Brückenzweig dann eingeleitet wird, wenn entweder das Signal /KOMP1 oder das Signal "MAX" eine aufsteigende Flanke erzeugen.In order to prevent such pulse misfires when the control voltage exceeds the value of the comparison voltage, a digital signal "MAX" according toFIG. 3e is generated shortly before the comparison voltage is reset. Furthermore, a digital signal "MIN" is generated shortly after the comparison voltage is set. It is provided that the digital signal "MIN" is combined with the signals / KOMP1 and / KOMP2 via a logical AND gate146 ,148 . A signal at the output of the AND gate146 ,148 is then logically OR-linked with the digital signal "MAX", so that it is ensured in this way that a first switching operation in a bridge branch is initiated when either the signal / KOMP1 or the signal "MAX" generate a rising edge.
Der zweite Umschaltvorgang wird sodann von der ansteigenden Flanke des Signals "MIN" übernommen, wobei das Signal "MIN" mit dem Signal /KOMP2 logisch UND-verknüpft wird.The second switching process is then triggered by the rising edge of the "MIN" signal.taken over, whereby the signal "MIN" with the signal / KOMP2 logically AND-linkedbecomes.
Dadurch ist eine Mindestimpulsbreite festgelegt, die einerseits über die Impulsbreite des Signals "MAX" und andererseits über die Impulsbreite des Signals "MIN" definiert ist. Durch logische Verknüpfung mit dem Signal "H" wird eine Auswahl getroffen, welcher Brückenzweig zu schalten ist.As a result, a minimum pulse width is defined, which is on the one hand over the pulse width of theSignal "MAX" and the other hand is defined by the pulse width of the signal "MIN". ByLogical connection with the signal "H" makes a selection of which bridgesto switch branch.
Die Dauer der Signale "MIN" und "MAX" werden wie folgt festgelegt: Da es sich bei der Signalgeberschaltung114 um einen 8-Bit-Zähler handelt, verbleibt das Signal "H" während der Zählimpulse 0-126 auf dem logischen Pegel "LOW" und während der Zählimpulse 127-256 auf dem logischen Pegel "HIGH". Ferner ist vorgesehen, dass bei dem Zählerstand126 am Ausgang132 ein Entladesignal gesetzt wird, das bei dem Zählerstand 1 wieder zurückgesetzt wird, so dass die aufsteigende Rampe der Vergleichsspannung erzeugt wird. Das Signal "MIN" wird während der Zählerstände 2-4 von dem logischen Pegel "HIGH" auf den logischen Pegel "LOW" geschaltet. Andererseits wird das Signal "MAX" während der Zählerstände123-125 auf den logischen Pegel "HIGH" geschaltet.The duration of the signals "MIN" and "MAX" are determined as follows: Since the signal generator circuit114 is an 8-bit counter, the signal "H" remains at the logic level "LOW" during the counting pulses 0-126 "and during the counts 127-256 at the logic level" HIGH ". It is further provided that a discharge signal is set at the counter reading126 at the output132 , which is reset again at the counter reading 1, so that the ascending ramp of the reference voltage is generated. The signal "MIN" is switched from the logic level "HIGH" to the logic level "LOW" during the counts 2-4. On the other hand, the signal "MAX" is switched to the logic level "HIGH" during the counter readings123-125 .
Insgesamt dienen die Signale "MIN" und "MAX" dazu, die Pulsweitenmodulation in ihrer minimalen und maximalen Ansteuerung zu begrenzen. Insgesamt wird durch die erfindungsgemäße PWM-Steuerung eine symmetrische Pulsweitenmodulation für einen Wechselrichter zur Verfügung gestellt, wodurch insbesondere beim Einschaltverhalten und im Leerlauffall das Regelverhalten der Schaltungsanordnung zum Betreiben des Wechselrichtes verbessert wird.Overall, the signals "MIN" and "MAX" serve to change the pulse width modulation in theirlimit minimum and maximum control. Overall, the inventionPWM control according to a symmetrical pulse width modulation for an inverterprovided, which makes it particularly useful when switching on and when idlingimproves the control behavior of the circuit arrangement for operating the inverterbecomes.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19848540ADE19848540A1 (en) | 1998-10-21 | 1998-10-21 | Circuit layout and method for operating a single- or multiphase current inverter connects an AC voltage output to a primary winding and current and a working resistance to a transformer's secondary winding and current. |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19848540ADE19848540A1 (en) | 1998-10-21 | 1998-10-21 | Circuit layout and method for operating a single- or multiphase current inverter connects an AC voltage output to a primary winding and current and a working resistance to a transformer's secondary winding and current. |
| Publication Number | Publication Date |
|---|---|
| DE19848540A1true DE19848540A1 (en) | 2000-05-25 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19848540AWithdrawnDE19848540A1 (en) | 1998-10-21 | 1998-10-21 | Circuit layout and method for operating a single- or multiphase current inverter connects an AC voltage output to a primary winding and current and a working resistance to a transformer's secondary winding and current. |
| Country | Link |
|---|---|
| DE (1) | DE19848540A1 (en) |
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