CN87100490A - method for manufacturing multilayer printed circuit board - Google Patents

Abstract

Translated fromChinese

一种用分别设计并制造好的复合结构来制造叠加多层电路板的工艺，各复合结构由通过光可处理绝缘膜支承的形成图形的导电金属箔组成。把复合层的有箔图形一面向下粘到基板或先前存在的多层结构上，有选择地除去绝缘膜的表面向下直到达下层金属点，以便无电敷镀。接着对绝缘膜上的所有小孔无电敷镀充满金属直到与上表面齐平。加上附加的已形成图形的复合层并按需要敷镀以产生隐蔽通路和一层接一层的新的导体图形层。

A process for manufacturing stacked multilayer circuit boards from individually designed and fabricated composite structures consisting of patterned conductive metal foils supported by a photo-treatable insulating film. The composite layer is bonded foil pattern side down to a substrate or pre-existing multi-layer structure, selectively removing the surface of the insulating film down to the underlying metal points for electroless plating. Then all the small holes in the insulating film are electrolessly plated and filled with metal until they are flush with the upper surface. Additional patterned composite layers are added and plated as needed to create hidden vias and new conductor pattern layers one after the other.

Description

Method for manufacturing multilayer printed circuit board

This application is related to U.S. patent application 742, 742, filed concurrently herewith by us and entitled "method of making a resist pattern for a printed circuit board", filed on 10.6.1985 and assigned to the assignee of the present application and which is now incorporated by reference.

The present invention relates generally to the manufacture of printed circuit boards, and more particularly to the manufacture of multilayer printed circuit boards using a common additive process.

The limitations of printed circuit board technology due to the integration and miniaturization of electronic circuit components that has been carried out over the last 20 years have become an increasingly complex problem. Printed circuit boards, or more accurately referred to as Printed Wiring Boards (PWBs), serve several primary functions, first of all, electronic components such as specially packaged integrated circuits, resistors and the like are mounted or carried on a generally rugged card-like planar surface. In this way, the PWB provides a support for the components. Secondly, the PWB forms the required electrical connections between the components using chemical etching or plating of conductor patterns on the surface of the board. In addition, the PWB can also include metal areas that act as heat sinks. As the use of integrated circuits increases, higher density connections require a double-sided PWB in order to utilize the conductor pattern on the other side of the board as an additional connection. This trend has extended to the joining of many layers of boards known as multilayer PWBs. The layers are typically connected by plated through holes (metallized holes).

The conductor pattern is generally formed by photo-etching an epoxy resin glass fiber substrate coated with a copper foil. A photosensitive resin layer is applied to the copper foil and patterned by exposing ultraviolet light through a film-like pattern mask of the stencil …. The exposed areas of the photosensitive resin are polymerized. The unpolymerized areas are removed with a chemical solution leaving areas of copper. The desired conductor pattern is formed under the remaining polymerized photosensitive resin protective layer. The exposed copper foil is then etched away and the remaining photosensitive resin is chemically removed, exposing the conductor pattern formed thereby. Of course, there are many common variations of this process, such as forming a conductor by additionally plating a layer of copper against the etch pattern. However, all conductor patterns to be etched have different degrees of undercutting (undercut) because only the top surface is protected from the etchant. When extremely thin conductor patterns are required, undercutting becomes particularly prone to failure.

With the increasing integration of circuits, Surface Mount Technology (SMT) has greatly accelerated the densification of electronic circuits, enabling space requirements to be reduced by as much as 70%. Surface Mount Devices (SMDs) are mounted directly to the surface of the PWB and soldered using vapor phase solder, solder reflow or other techniques. For integrated circuit surface mount positioning with many lead ends in a fine pitch, very good resolution of the conductors of the PWB is required.

Meanwhile, electroless plating technology is rapidly improving. In such systems, it is widely used by japanese manufacturers to chemically create conductor circuits by metal deposition in large plating baths on multi-layer paper substrates. Recently, improvements in bath formulation and bath operating systems have facilitated the use of electroless plating techniques in countries other than japan. In one approach, the catalyzed substrate is coated with a layer of photosensitive resin. After the patterned protective layer is formed, the holes through the protective layer are filled with metal using electroless plating. This process is referred to as a "superposition" process because the conductors are created with superposed metal rather than subtractive (i.e., etched) metal. In this way, the conductor circuit can be made to a desired thickness. Generally, electroless plating techniques reduce or eliminate the effects of undercutting and produce straight-sided conductors of native metal. However, this method requires the use of a catalyst manufactured in a foreign country to promote copper deposition and increase adhesion.

However, SMD circuits have become so dense that multiple layers of PWBs have become a focus of attention and several technologies are competing. A single layer of fiberglass epoxy PWB can be bonded together and internally connected with metallization to the drilled holes. Cofired ceramic production technology is used in additional lamination processes, and prototype shielding wires have also been proposed. All of these systems have a number of drawbacks. For example, in a four-layer PWB, 2, 3 layers would require an intermediate connecting layer, and the perforations would have to pass through the entire structure, thus wasting "real estate" on 1layer 4 that could otherwise be allocated for use. It is therefore not well possible with the prior art to provide what is known as a blind via for buried connections between two or more inner layers.

It is therefore a general object of the present invention to provide a technique for fabricating a multilayer conductor circuit including blind vias and a new conductor pattern on a single substrate. It is another object of the present invention to create a multilayer PWB with hidden vias on unconnected layers that does not waste space. A related object of the invention is to provide a practical process for manufacturing complex multilayer PWBs on a single substrate for SMD.

These and other objects of the present invention are achieved by using separately fabricated composite structures comprised of a conductive foil coated with an insulating film. The conductive side is patterned and etched in a separate process. The conductive foil pattern side of the composite layer is then adhered to the underlying substrate or to a previously existing multilayer structure and the insulating film is removed in selected areas to the underlying metal locations for electroless plating. All of the pinhole patterns into the insulating film are filled with native metal by electroless plating, which rises to the upper surface to form conductors and vias. More unique patterned composite layers and platings can be used when it is desired to form a multilayer structure that includes blind vias, virtually without complexity constraints.

In terms of the best process, the insulating film is optically processable. Preferably a Permanent Drying Film (PDF). The metal foil is preferably a copper foil that can be photo-etched by conventional methods. Since the copper foil blocks the exposure energy, the uncured PDF is not affected by the operation of previously patterning the conductor wiring (which causes the foil to "de-plate"). After the foil pattern side is glued to the underlying PWB for compositing, the PDF is exposed through a mask and the required coating to expose itself under the coating or on the pre-existing underlying metal areas on the top surface of the PWB is removed. In the latter case, any adhesive material can be removed at the same time. The apertures in the PDF are then plated electroless to form conductors and vias. All the work on the board is done in a superimposed way, and the multilayer continuous primary metal conductive channel produced by this method is higher in the fineness of the wire (higher resolution) than can be reliably achieved by the prior art subtractive process. This technique provides the greatest flexibility in designing circuit patterns without being affected by the previous layer, since electroless plating can be re-performed in an area of the multilayer substrate where there is no metal. Furthermore, the composite can be produced simultaneously as an auxiliary element in a parallel assembly system.

In another technique that may be used, a foiled composite is also used, the upper side (i.e., the outer side) of the foil of which is bonded to a pre-existing PWB structure, and the foil on the board is subsequently patterned to form a resist pattern to selectively expose the insulating material of the interlayer connection regions. The insulating material exposed to the underlying metal is removed by an etching process to facilitate electroplating or electroless plating. All the pores in the insulation are then plated with metal so that they are above the surface of the foil layer. This layer is then resist patterned for a second pass to form additional foils of conductor coated insulating layers on the foil layers suitable for use on either or both sides of the PWB structure to form blind via connections to the multilayer PWB in virtually any combination.

FIG. 1 is a schematic cross-sectional view of a fabrication sequence of a multilayer circuit board made using the method of the present invention.

FIG. 2 is a schematic cross-sectional view of a composite layer before and after patterning for the multi-layer circuit board structure shown instep 7 of FIG. 1.

Fig. 3-6 are schematic cross-sectional views of the multilayer substrate betweensteps 6 and 8 of fig. 1 at points of differing properties.

Fig. 7 is a schematic cross-sectional view of a composite layer before and after foil patterning for another multilayer circuit board structure shown instep 8 of fig. 1.

Fig. 8 is a schematic sequence diagram showing another method for manufacturing a multilayer PWB using a foil-clad composite.

The process for multilayer PWB is described below as being continuously run in a high volume process plating tank using chemical plating to build up very dense and complex individual layers on conventional substrates, (such plating tanks can accommodate a large number of circuit boards at a time). When separate composite fabrication is required, the entire process can be done with a high degree of automation. The process will not only prove to be versatile, but also highly economical compared to competing technologies.

Fig. 1 shows a cross-section of a multilayer PWB structure representing nine stages. Since the conductor pattern in any given plane is very complex, the extent of a given conductor channel in a given layer plane is omitted for simplicity of illustration. As seen in the cross-section of fig. 1, the exposed metal regions on a given layer may simply correspond to the vertical connection point between the two layers, or may be a portion of a through conductor that runs, for example, perpendicular or oblique to the paper in the plane of the layer.Steps 1 through 5 illustrate electroless plating through a layer of permanently dried film to produce a single, coplanar conductive layer. Two different composites are applied atsteps 7 and 8, respectively. The detailed steps leading to step 8 in fig. 1 are specifically shown in fig. 3-6.

Instep 1, asubstrate 10 is covered with a conductive metal foil 12. The substrate may be a sheet made of any insulating material, for example, synthetic resin, glass, ceramic, metal-coated ceramic, laminated paper, card paper, or fibrous material. Examples of the synthetic resin include phenol resin, melamine resin and epoxy resin. The most preferred substrate is a fiberglass epoxy composite panel.

The conductive metal foil 12 is selected from metals having desired electrical and mechanical properties as well as chemical and thermal resistance. The preferred metal for the foil 12 is copper, with a typical thickness of about 0.5 to 3 mils.

Instep 2, the metal foil 12 is patterned to form conductive lines. A layer of photosensitive resin (not shown) may be applied to the foil 12 and exposed through a mask. Next, the exposed photosensitive resin is removed, and the underlying metal is etched to leave the desired metal circuit pattern lines 14. The photosensitive resin structure is generally applied in the form of a conventional laminated or centrifugally dried film using a liquid protective film. The protective layer may be patterned by exposure of a photographic master to Ultraviolet (UV) radiation, or directly with an electron beam, or laser. Another method of forming a wiring pattern on a metal foil is taught in our above-referenced copending application. Because the lines 14 are not used to form the final finished conductor, naturally, the metal foil 12 is preferably very thin to allow for a fine line pattern with high resolution without undercutting problems that often occur with subtractive techniques having thicker layers.

Instep 3 of fig. 1, the conductive pattern 14 formed from the metal foil 12 is coated with a photo-processable insulating material 16, preferably a photo-curable nonconductive film. The insulating material 16 is preferably uncured PDF applied by a dry layer method using a lamination method.

The best PDF material is the uv-cured polyacrylonitrile with a precise concentration called PAR-001 produced by e.i. dupout de Nemours & co. One undesirable characteristic of this material is that it does not adhere well to copper. Thus, the more widely used and commonly available PDF includes an adhesion promoter for copper to make this material suitable for use as a solder resist, or for other types of pattern insulation. A more general disadvantage of the known type of PDF is that it is not suitable for use as a plating mask. In particular, agents that promote copper adhesion leach into the bath, causing the bath to fail over an unacceptably short period of time. PAR-001 used in the present invention does not incorporate a copper adhesion promoter and, therefore, can be used as a plating mask without poisoning the plating bath. However, after curing, it does not adhere well to copper. The uncured PDF is soft and slightly tacky and it can temporarily adhere to copper. The uncured PDF, which is laminated to a non-copper substrate, once cured, adheres permanently to the substrate material (epoxy in this case).

Atstep 4, PDF16 is patterned by UV exposure through a mask outlined by the desired conductor pattern. The mask is the same as the negative photoresist mask instep 2. The exposed areas 18 polymerize, harden and remain (as shown in fig. 4). The areas between the hardened PDF18 are chemically removed to form voids or pinholes that expose the underlying copper traces 14. The copper dots thus exposed by the small holes are used for electroless plating. The exposed copper strands act as catalytic sites that have an affinity for copper ions in the plating bath. The thickness of the metal is "grown" by chemical growth until all the pores are filled or plated with pure copper 20 as high as the upper surface as shown instep 5.

In steps 1-5 shown in fig. 1, the problem of the PDF plating mask not adhering to copper is not encountered because all the copper lines 14 in the entire layer are exposed for plating. Only the interfaces between the layers are between the PDF and the epoxy of the substrate. Thus, the cured PDF and the conductor plated with metal according to the original copper lines 14 sandwiched between the layers is permanently bonded to thesubstrate 10, and the copper lines 14 themselves are bonded to thesubstrate 10.

As shown instep 6 of fig. 1, a second layer of PDF is added and processed to leave a permanent insulating pattern 22. Note that the pores are formed over a pre-existing metal. In this case, however, some of the metal conductor regions are covered by the PDF rather than being exposed.

Since there is an interface between the copper and PDF layer to layer atstep 6 where the copper conductor is "stripped" from the previous layer, adhesion problems must be addressed. The results demonstrate that PDF necessarily adheres very well to tin. Thus, one technique for PDF bonding is to coat the exposed surfaces of metal conductor 20 with a layer of tin instep 5. This can be achieved by a step of dip coating a tin layer before the lamination of the PDF is uncured. Dip-coated tin layers are used as flash plating to speed up soldering in other processes. The resulting coating is very thin, on the order of a few angstroms, but is fully applicable as a link between copper and PDF. Alternatively, electroless plating of the tin on the pre-existing on-board conductors instep 5 may suffice.

After lamination and patterning of PDF 22, exposed metal dots 20 must be plated. Electroless plating of copper, the more noble metal, onto tin is difficult, and it is best to consider removing the exposed ultra-thin tin plating first with a "tin stripping bath" prior to plating. The exposed copper is then electroless plated through the apertures in the PDF as insteps 4 and 5. The resulting structure is shown in fig. 3.

To apply a new, separate circuit conductor pattern where there is no underlying metal, it is fabricated in a separate "de-plater" process, shown in fig. 2 as "composite" 24. A very thin copper foil coating 26 (about one-half inch copper foil about one-half mil thick) is laminated to one side of the uncured PDF sheet 28 by hot rolling. The copper foil side is then patterned to produce thin conductor pattern lines 30. Thin foils can be etched into very fine lines. The metal foil 26 may be photo-etched using conventional techniques, such as applying an ultraviolet photosensitive resin, exposing to actinic ultraviolet light, stripping the exposed portions and then etching the underlying copper foil, and removing the unexposed protective layer. The metal foil 26 functions as a light shielding plate of the photosensitive PDF 28 so that the PDF is shielded from light by the conductor pattern to be kept as it is (i.e., to leave unpolymerized portions).

The composite 24, still with uncured PDF, is then bonded with the copper foil pattern side down to the upper surface 32 of the multilayer substrate (as depicted in FIG. 3). However, a double-sided, effective film adhesive is first applied to the preexisting substrate surface 32. Polypropylene film adhesives are suitable for use in strippable interlayers having a degree of originality of 1, 2 or 3 mils between supports. After the composite is bonded to the substrate, PDF 28 is photo-treated to leave a hardened insulator pattern 34 (shown in FIGS. 4 and 5). Fig. 5 corresponds to step 7 of the overall process outline in fig. 1. Wherever copper foil lines are present on the underside of the composite, the overlying PDF is apertured to leave holes and slots to form vias and conductors. The copper foil lines are catalytic dots or as open ends in the plating. Thus, the copper foil is only temporarily bonded to the PDF, and there is no problem in the uncured state of the PDF. In addition, the metal areas on the substrate surface 32 are to be plated through the new layer, which are exposed through the holes in the PDF. The same solvent (e.g. 1.1.1 trichloroethane) removes unpolymerized PDF as well as the polypropylene film. The copper base porosity is then electroless plated as shown in fig. 6.

The PDF patterning and plating operation shown in fig. 5 and 6 is similar tosteps 4 and 5 of fig. 1. However, as a starting point for some of the plating, the copper dots 30 shown in fig. 5 are clearly different from, for example, pre-existing copper dots specifically used forsteps 4 and 6 in fig. 1. Dot 30 in fig. 5, which is actually the underside of foil plating 26 (fig. 2), is formed over this layer as is conductor pattern 30. These very thin foil conductors 30 on the composite form new electroless plated spots on certain areas (those areas where there is no metal under the previous layer). The hardened PDF insulating layer 22 and the polypropylene adhesive film are located just below the copper foil dots 30. It is noted that the composite PDF in region 36 that does not conform to its own conductive pattern coating may be removed for plating to connect to adjacent layers. Thus, the use of the composite allows flexibility in plating existing or new metals. In addition, some of the conductors exposed on the preexisting substrate surface 32 will no longer be used, i.e., not electrically connected to new layers. In this way, the polypropylene film adhesion layer between the composite layer and the substrate solves two different problems: it not only adheres the lines on the bottom of the composite layer to the underlying cured PDF on the substrate surface 32, but it also adheres the exposed unused copper conductors to the uncured PDF of the composite layer.

It is noted that although the same polypropylene adhesive film technique can be used in steps 1-5 of fig. 1 instead of the conductor pattern tinning, it is preferable to minimize the number of adhesive films because they are less temperature stable than PDF. Thus, when PDF is added alone (i.e., not composite), it is preferable to plate the underlying copper with tin.

Fig. 6 corresponds to step 8 before the next layer is superimposed in fig. 1. After the process of plating the apertures flush with the top surface of the growing multilayer structure as shown in fig. 6, PDF may be added either separately as instep 6 of fig. 1 (as in steps 3-5) or another composite layer as in fig. 7 may be added instep 7 of fig. 1. Fig. 7 shows a second composite layer 40 on which, somewhat similarly to fig. 2, conductor patterns 30' of different properties are formed. The underside of the composite layer 40 is bonded with copper foil and the PDF is photo-treated using the same procedure as described above and illustrated in fig. 3, 4 and 5, optionally leaving the configuration shown instep 8 of fig. 1. The remaining hardened PDF 42 remains small through the old and new metal provided by the applied pattern 30'. The holes are plated as high from the copper dots to the top surface as shown instep 9 of fig. 1 to complete the multilayer structure in this illustration. The surface mounted components are attached directly to the top conductor surface. A solder resist (not shown) will be used to protect the surface conductors leaving only those exposed points where components need to be soldered.

When it is desired to produce a particular multi-layer PWB, steps 3 through 5 and 7 through 9 of fig. 1 can be altered or repeated.

Although this composite is illustrated as being used on a pre-existing multilayer substrate, the composite can be used as easily as the first circuit layer on an insulating substrate such as an epoxy glass plate. Additional composite and insulating layers may then be added as needed.

One of the main features of the method is the flexibility to design any conductive metal pattern 30 and 30' to work directly on top of the multilayer structure without difficulty. For example, various modification methods different from the properties of the multilayer substrate that has been originally constituted may be employed. Also, a large number of circuits can be prepared simultaneously or the actual assembly time can be minimized beforehand.

The method of compounding the photo processable insulating material with the patterned conductive foil has the following additional advantages over the prior art methods: (1) patterned copper foil formation can be applied directly to conductive circuits on multi-layer boards without further plating or etching, (2) without buried conductive lines, (3) composite formation of vertical connections and blind vias without drilling and plating multiple insulating layers, and (4) with improvements in conductor resolution, profile and shape, the on-board process is entirely additive. The resulting conductive path is formed from a continuous native metal. The ability to reduce process steps and increase substrate conductor metallization by simply dipping into an electroless plating bath allows the stacked circuit boards to be manufactured in larger volumes at lower cost for mass production than conventional processes. Furthermore, electroless plating provides a method for fabricating higher density boards with dense, small diameter vias (high aspect ratio) that is different from semi-additive processes or processes that utilize electroplating techniques.

One inherent disadvantage of the above-described technique illustrated in fig. 1-7 is that: since the uncured PDF is soft and slightly stretchable, it is necessary to take into account the dimensional stability of the graphic foil composite when it is laminated to the surface of the ready-made multilayer PWB. In addition, non-copper bonding of PDF suitable for plating baths requires additional bonding or tin plating procedures. The advantages of the above-described process, however, greatly outweigh the disadvantages thereof, and another technique that completely avoids these particular disadvantages is detailed in fig. 8, which uses an etchable insulating material for the foil coating, rather than a photo-processable PDF insulator.

The process begins with copper foil applied to both sides of an insulating material 50 (step 1 of fig. 8), and the outer foil layers 52 and 54 are etched using a resist process to form apertures or pores 56 in the foils to selectively expose the insulating material. Theholes 56 are not conductor patterns, but rather small windows or channels into the insulator 50 (step 2).

The outer foil layers 52 and 54 serve as a resist mask during etching of the insulatinglayer 50. Theinsulator 50 is exposed throughapertures 56 to be etched in either way from one foil layer to the other. Suitable methods for etching the polymer insulation are various chemical liquids, plasma or "dry" etching, or a suitable laser energy. The foil layers 52 and 54 protect the underlying insulator during the etching process, thereby allowing the insulator to selectively form holes or voids 58 therein fromrespective windows 56 in the foil to the underlying foil layer on the other side of the composite.

Next, thevoids 58 in theinsulator 50 are metal filled as shown instep 4, thereby forming interconnected columns orvias 60 between the foil layers 52 and 54. Since thepassage 60 extends completely through one layer to the other, this is no different from the windows formed on either one or the other or both of the faces shown insteps 2 and 3. In any case, thevoids 58 are filled with metal using a metallization process. Electroless plating may be used or, because the foil layers 52 and 54 are intact (i.e., not patterned), electroplating may be used after a thin initiation layer is electroless plated in a standard hole metallization process on the walls of thevoids 58. Electroless sensitization followed by electroplating involves electroless plating of a catalytic sensitizing solution in the cavities to form catalytic sites for electroless plating of a thin layer of copper. Once plated, the thin layer of copper in the hole forms a continuous electrical conductor with the outer foil surface, allowing for faster plating to be used for the remainder of the plating. Electroplating is difficult for holes with large aspect ratios, but the voids on the very thin insulator of FIG. 1 can have a relatively small aspect ratio, in which case electroplating can be performed. In general, it may be used to enhance the plating of the holes using any of a variety of known techniques that are desirable, such as pulse plating, mechanical agitation, and air sparging. A typical aperture or window is about 4 mils wide. The outer insulating layer is desirably about 1 to 2 mils thick, so the insulator voids have an aspect ratio of about 2 for ease of plating.

The outer foil layers 52 and 54 are then re-etched into conductor patterns 52 'and 54' using conventional techniques or by etching patterns as shown in our above-referenced copending application. The foil layer is patterned to leave a double-sided conductor pattern, and an overlying layer of insulating material, with only one side being foiled (blanket-out), may be adhered to one or both sides.Step 6 of fig. 8 illustrates a two-sided process in which insulatinglayers 64 and 66 with copper foil plies 68 and 70 on the outside thereof are bonded to the structure ofstep 5. As shown instep 7, copper foil plies 68 and 70 are etched to formapertures 72 that are aligned with the underlying copper points on the two conductor patterns formed on the surface of the original insulatinglayer 50. The exposed insulating material is etched away again using any of the techniques mentioned above except that apertures are formed in the two different insulatinglayers 64 and 66. As shown instep 8 of fig. 8, the resultingvoid 74 is then metallized to connect the underlying point such as 52' to the outer foil layer (as shown in step 9). And again plated with a separate electroless plating or sensitized electroless plating.

The foregoing process of fig. 8 is useful for a wide variety of material systems. For example, the foiled insulation can be bonded using a bonding technique such as that used in the method of FIG. 1, or by a bonding operation using a press or pad of thermosetting or thermoplastic insulating material which is inherently tacky. The invention is also particularly suitable for very thin materials. As an example, a (0.001-0.002 inch) thin thermoplastic sheet (e.g., Dupont teflon FEP) is used and the outer foil layer and insulating sheet are simultaneously bonded by hot rolling to a "core" structure, which may be a typical rigid double-sided sheet (PTH type) or a flexible thin core such as polyimide, manufactured as described above. When using thermoplastic insulation, the dimensional stability of the core structure must be considered, and in such cases, the use of a polytetrafluoroethylene thermoplastic core should be avoided.

The structure resulting fromstep 10 of fig. 8 represents a multi-layer PWB having four conductor layers and three insulating layers. The intermediate insulatinglayer 50 should be a material that is dimensionally stable for the application. A particularly desirable combination would be to use a polyimide Kapton material manufactured by Dupont for thecore 50 and a teflon layer for theinsulators 64 and 66. Afterstep 10 of fig. 8, if no additional layers are required, the bare copper body exposed on this surface should be covered with a solder resist film that exposes the required terminals for SMD soldering. These dots are then coated with solder.

For complex circuit patterns, etching of polyimide insulating materials such as Kapton or teflon uses dry plasma glow discharge or wet chemical etching rather than laser beam etching. Since laser etching is a non-batch process, each channel must be formed separately, one layer at a time. For polytetrafluoroethylene by rapid plasma etching, for polyimide, an etching technique using a solution of ethanolic potassium hydroxide, either sprayed or immersed, is suitable.

The plating of the via sites can be accomplished in a number of ways and with a variety of variations. For example, the entire outer foil layer can be plated to a given thickness simultaneously with the via points. In another variant, a protective film may be applied to the outer foil layer before the plating, so that only the desired conductor pattern is completely plated or only the vias are plated. Since the outer foil layer is continuous, the plated metal can be used as an etch resist there, such as by selectively plating a tin-lead alloy layer through a photosensitive resin film overlying the copper foil conductor pattern, which acts as an etch resist during background copper removal. A similar technique is detailed in our co-pending application for patterning resist cited above.

The method of fig. 8 provides advantages in terms of material and ease of alignment, thereby making it possible to finally synthesize a conductor pattern including blind vias. When the vias themselves are not photo-treated but formed by etching of the foil protective film, the choice of insulating material is not limited to photoreactive polymers, but on the other hand the permanently dried film is vulnerable to damage upon curing, so that the method of fig. 8 can be used with flexible thermoplastic materials as the insulating layer. However, in the case where an insulating layer made of, for example, polytetrafluoroethylene is used in connection with a stable core material and all conductor patterns are formed in one on-board process for the purpose of facilitating alignment, dimensional stability can be disregarded. There are many materials suitable for use in the process of fig. 8 if it is desired to bond the insulating layers with an adhesive material. For example, a polypropylene adhesive material may be used and plasma etched for removal to the underlying copper sites. A stable multi-layer PWB core structure may be provided by conventional PWB techniques such as overlay, semi-overlay or pattern plating processes to make a double-sided PTH board. Instead of the outer layer solder protection, multilayering may be applied to the core surface conductor pattern by foil-applied insulating sheets to form a structure similar to that shown instep 6 of fig. 8, except that the channels inside the core are PTH-based.

A typical multi-layer PWB has an internal core board with two insulating layers, one voltage layer and the other ground layer, to achieve high capacity. The signal layer is formed on the outer layer of the PWB. One particularly advantageous system would be to standardize the internal core boards with voltage and ground planes for the various circuits. I.e. should have a sufficient number of voltage and ground plane layers and through connections at various locations for various circuits. The standardized voltage ground plane structure provides a faster turn around for testing complex circuit prototypes constructed in the form of multiple layers of PWBs.

Another possible application of the insulating material system for the process of fig. 8 is the use of a glass mesh or screen impregnated with, for example, teflon or other thermoplastic or thermoset resin. The use of a mesh or screen not only enhances the dimensional stability of the plastic but also allows for accurate thickness. Another possibility is to use epoxy glass fibre board as the insulating layer. Plasma etching removes plastic from the glass cloth, but the desirability of plating through the glass cloth must be considered.

Various changes and modifications to this method of manufacturing a multilayer circuit board may be made by those skilled in the art without departing from the principles and spirit of the invention, from the foregoing detailed description and accompanying drawings. For example, while fig. 1 illustrates a method of manufacturing a single-sided multilayer PWB, in many cases it is possible, and is not suspected to be optimal, to use the method of fig. 1 for simultaneously manufacturing double-sided boards on both sides of a laminate somewhat similar to the double-sided boards illustrated in fig. 8 in another method. In addition, although the alternative methods of fig. 1 and 8 favor photo-processible insulating layers in one case and non-photo-processible insulating layers in another case, the method of fig. 1 can be used to drill holes directly in the insulating layers with a laser beam, e.g., the laser beam will be reflected by the underlying metal dots on an existing multilayer PWB structure. For pre-processing the composite layer 24 of figure 2. The disadvantage of this method is that it is not "mass produced" and requires direct energy. Such modifications, however, are to be considered as included within the scope of the appended claims.

Claims (57)

Translated fromChinese

1、一种制造电气内连板的方法，其特征在于包括以下步骤：1. A method for manufacturing an electrical interconnector plate, comprising the following steps:--在金属导体支承基板上敷设永久绝缘膜层，-- Laying a permanent insulating film layer on the metal conductor supporting substrate,--在所述绝缘层的预定图形上形成小孔，以便暴露下层金属点，和-- forming small holes in a predetermined pattern of the insulating layer to expose underlying metal dots, and--从所述暴露的金属点起敷镀金属，直到充满在所述绝缘层上的小孔，以形成实心的导体和内层通路。--Metal is plated from the exposed metal points until the small holes on the insulating layer are filled to form solid conductors and inner layer vias.2、如权利要求1的方法，特征在于其中所述绝缘层是由光可处理材料制成的，以及所述的在绝缘层上形成小孔的步骤是通过对所述绝缘层进行光处理来完成的。2. The method of claim 1, wherein said insulating layer is made of a photoprocessable material, and said step of forming the pores in the insulating layer is performed by photoprocessing said insulating layer.3、如权利要求2的方法，特征在于其中所述绝缘材料是永久干燥膜。3. The method of claim 2, wherein the insulating material is a permanent dry film.4、如权利要求3的方法，特征在于其中所述永久干燥膜当其涂到所述基板上时是一种未反应的紫外线敏感性膜。4. The method of claim 3, wherein said permanent dry film is an unreacted UV-sensitive film when applied to said substrate.5、如权利要求1的方法，特征在于其中所述绝缘层在形成小孔之前，就敷有一层金属箔，以及所述的在绝缘层上形成小孔的步骤是由首先在敷箔上形成小孔，然后通过敷箔上的小孔蚀刻所述绝缘层来完成的。5. The method of claim 1, wherein the insulating layer is coated with a metal foil before the holes are formed, and the step of forming the holes in the insulating layer is performed by first forming the holes in the foil and then etching the insulating layer through the holes in the foil.6、如权利要求1的方法，特征在于其中把所述绝缘层加到所述基板之前，所述绝缘层被敷有箔层，以及所述绝缘层以箔侧向外的方式加到所述基板，和6. The method of claim 1, wherein said insulating layer is coated with a foil layer before said insulating layer is applied to said substrate, and wherein said insulating layer is applied to said substrate with the foil side facing outwards, and在所述绝缘层上形成小孔的所述步骤是通过首先在所述箔上形成小孔，然后蚀刻所述绝缘层的暴露部分并向下到所述基板上的下层金属箔点来完成的。The step of forming apertures in the insulating layer is accomplished by first forming apertures in the foil and then etching the exposed portion of the insulating layer down to the underlying metal foil points on the substrate.7、如权利要求1的方法，特征在于其中把所述绝缘层加到所述基板之前，在所述绝缘层的一面上被限定了一个导电金属图形，以及所述绝缘层以导体图形面向下邻接到所述基板表面的方式加到所述基板上。7. The method of claim 1, wherein a conductive metal pattern is defined on one side of said insulating layer before said insulating layer is applied to said substrate, and said insulating layer is applied to said substrate with the conductive pattern facing downwardly adjacent to said substrate surface.8、如权利要求7的方法，特征在于其中在所述绝缘层上形成小孔的步骤包括在所述绝缘上形成这样的小孔的步骤，这些空洞点可向下到达由所述绝缘层支承的导电图形以及到达在所述基板上的金属点。8. The method of claim 7, wherein the step of forming holes in said insulating layer includes the step of forming holes in said insulating layer that reach down to conductive patterns supported by said insulating layer and to metal points on said substrate.9、一种制造电气内连板的方法，其特征在于包括以下步骤：9. A method for manufacturing an electrical interconnector plate, comprising the following steps:-准备在其一面敷有可形成图形的绝缘膜，同带有可形成图形，可无电敷镀的金属箔的复合层，- preparing a composite layer having a patternable insulating film on one side and a patternable, electrolessly plated metal foil,-除去所述复合层上的部分所述箔以确定一个导体图形，- removing portions of said foil on said composite layer to define a conductor pattern,-把所述复合层向下加到先存的基板导体图形面，- adding the composite layer downwards onto the pre-existing substrate conductor pattern surface,-有选择性地除去部分所述膜来形成孔洞，这些孔洞至少部分地露出作为敷镀催化点的所述敷箔导体图形的下面，和- selectively removing portions of the film to form holes which at least partially expose the underlying surface of the foil conductor pattern as plating catalyst sites, and-无电敷镀，使孔洞充满金属。-Electroless plating to fill the holes with metal.10、如权利要求9的方法，特征在于还包括以复合层为基础，构成多层复合层的重复详述的各步骤。10. The method according to claim 9, further comprising repeating the detailed steps to form a multi-layer composite layer based on the composite layer.11、如权利要求9的方法，特征在于其中所述绝缘膜是可光处理的以及所述除去所述膜的步骤是通过对所述膜进行光处理来完成的。11. The method of claim 9, wherein said insulating film is photoprocessable and said step of removing said film is performed by photoprocessing said film.12、如权利要求11的方法，特征在于其中所述绝缘膜是未固化的PDF。12. The method of claim 11, wherein the insulating film is uncured PDF.13、如权利要求12的方法，特征在于其中所述金属是铜;所述PDF实际上没有铜的附着力促进附加剂，以免使所述无电敷镀步骤中所用的镀液中毒。13. The method of claim 12 wherein said metal is copper and said PDF is substantially free of copper adhesion promoting additives to avoid poisoning the plating solution used in said electroless plating step.14、如权利要求13的方法，特征在于其中所述施加复合层的步骤包括一种粘接层施加在所述基板和所述复合层之间。14. The method of claim 13, wherein said step of applying a composite layer comprises applying an adhesive layer between said substrate and said composite layer.15、如权利要求17的方法，特征在于其中所述粘接层是由可与所述膜部分一起被除去以形成所述孔洞的材料所形成的。15. The method of claim 17, wherein said adhesive layer is formed of a material that can be removed together with said film portion to form said hole.16、如权利要求9的方法，特征在于其中所述除去箔步骤包括使用感光性树脂来确定所述导体图形。16. The method of claim 9, wherein said step of removing foil includes using a photosensitive resin to define said conductor pattern.17、如权利要求9的方法，特征在于还包括以下步骤：17. The method according to claim 9, further comprising the steps of:-首先准备表面上暴露有金属导体的基板，及- first prepare a substrate with a metal conductor exposed on the surface, and-有选择地除去部分所述膜的步骤，以露出所有所述敷箔图形的下面和至少某些在基板表面上的金属导体点。- the step of selectively removing portions of said film to expose all of said foil pattern underneath and at least some of the metal conductor points on the substrate surface.18、如权利要求17的方法，特征在于其中所述施加步骤包括把所述复合层粘合到带有粘接材料层的基板上。18. The method of claim 17, wherein said applying step comprises bonding said composite layer to a substrate having a layer of adhesive material.19、制造PWB复合层的方法，特征在于包括：19. A method for manufacturing a PWB composite layer, comprising:-把导电金属箔加到一种未反应的光可处理绝缘材料上，和- applying a conductive metal foil to an unreacted photoprocessable insulating material, and-金属箔采用使未反应绝缘材料由金属箔隔离的方法来形成图形。- The metal foil is patterned by isolating the unreacted insulating material with the metal foil.20、如权利要求19的方法，特征在于其中金属箔通过施加感光树脂，把感光树脂暴露在有光化性的光照射下来形成图形的，其中金属箔使未聚合绝缘材料不受照射，除去保护膜并暴露金属箔，以形成导电金属图形，接着除去导电金属图形上留下的保护膜。20. The method of claim 19, wherein the metal foil is patterned by applying a photosensitive resin, exposing the photosensitive resin to actinic light, wherein the metal foil shields the unpolymerized insulating material from light, removing the protective film and exposing the metal foil to form a conductive metal pattern, and then removing the protective film remaining on the conductive metal pattern.21、如权利要求1的方法，特征在于还包括把绝缘材料-形成图形的金属箔的复合层以该金属箔邻接基板的方式加到基板上。21. The method of claim 1, further comprising applying the insulating material-patterned metal foil composite layer to the substrate with the metal foil adjacent the substrate.22、制造电路板的方法，特征在于包括：22. A method for manufacturing a circuit board, comprising:-制备由用于支承已经形成图形的导电金属层的绝缘材料板组成的复合层，- preparing a composite layer consisting of a sheet of insulating material for supporting a patterned conductive metal layer,-把所述的复合层加到基板上，和- applying said composite layer to a substrate, and-把复合层贴到基板上之后，在所述绝缘材料板上形成图形。- After attaching the composite layer to the substrate, a pattern is formed on the insulating material sheet.23、如权利要求22的方法，特征在于其中所述绝缘材料是一种未反应的光可处理材料;在所述绝缘材料板上形成图形的步骤是用光处理来完成的。23. The method of claim 22, wherein said insulating material is an unreacted photoprocessable material; and wherein the step of forming a pattern on said insulating material sheet is performed by photoprocessing.24、如权利要求22的方法，特征在于还包括从所述基板上的下层铜点通过形成图形的绝缘材料进行无电敷镀。24. The method of claim 22 further comprising electroless plating from underlying copper dots on said substrate through the patterned insulating material.25、制造多层电路板的方法，特征在于包括：25. A method for manufacturing a multilayer circuit board, comprising:1）把导电金属箔涂到一块绝缘基板上，1) Apply conductive metal foil to an insulating substrate,2）在导电金属箔上形成图形，2) Forming patterns on the conductive metal foil,3）把光可处理的绝缘材料施加到该形成图形的金属箔上，3) applying a photoprocessable insulating material to the patterned metal foil,4）在绝缘材料上形成图形以形成空洞，这些空洞暴露出下层的形成图形的金属箔的表面，4) Patterning the insulating material to form cavities that expose the surface of the underlying patterned metal foil,5）通过所述空洞对暴露的导电金属进行无电敷镀，一直到所述绝缘材料的表面，和5) electrolessly plating the exposed conductive metal through the cavity to the surface of the insulating material, and6）加上光可处理绝缘材料附加层，并在其上形成图形，对通过绝缘材料光处理而暴露的导电金属进行无电敷镀以形成垂直连接，6) adding an additional layer of photo-processable insulating material and patterning it, and electrolessly plating the conductive metal exposed by the photo-processing of the insulating material to form vertical connections,7）制备其一面敷有导电金属箔的光可处理绝缘材料复合层，其中箔上被形成有作为导电金属电路的图形，其中的绝缘材料在形成图形的工序中被箔隔离，7) preparing a composite layer of a photoprocessable insulating material having a conductive metal foil applied to one side thereof, wherein the foil is patterned as a conductive metal circuit, and wherein the insulating material is isolated by the foil during the patterning step;8）把复合层上形成图形的金属电路面粘接到基板上的经过无电敷镀-形成图形的绝缘材料的顶层，8) Bonding the patterned metal circuit surface on the composite layer to the top layer of the insulating material on the substrate that has been patterned by electroless plating,9）在复合层的绝缘材料上形成图形，并对暴露的导电金属进行无电敷镀以形成一个平的表面，和9) patterning the insulating material of the composite layer and electrolessly plating the exposed conductive metal to form a flat surface, and10）把步骤6与步骤7至9交换以形成多层电路板。10) Swap step 6 with steps 7 to 9 to form a multilayer circuit board.26、如权利要求25的方法，特征在于还包括从这样的一组材料中选择绝缘材料：这些材料不需要附加的催化点，便能用导电金属溶液来无电敷镀。26. The method of claim 25 further comprising selecting the insulating material from the group of materials that can be electrolessly plated with a conductive metal solution without requiring additional catalytic sites.27、如权利要求25的方法，特征在于进一步包括使绝缘材料形成催化点的处理，以便接着用导电金属溶液进行无电敷镀。27. The method of claim 25 further comprising treating the insulating material to form catalytic sites for subsequent electroless plating with a conductive metal solution.28、如权利要求25的方法，特征在于还包括在导电金属箔上施加感光树脂来形成图形，通过掩膜使感光树脂暴光，蚀刻感光树脂和暴露的下层金属箔，以形成电路图形。28. The method of claim 25, further comprising applying a photosensitive resin on the conductive metal foil to form a pattern, exposing the photosensitive resin through a mask, and etching the photosensitive resin and the exposed underlying metal foil to form a circuit pattern.29、如权利要求25的方法，特征在于其所述金属是铜，并进一步包括在步骤（3）之前，对形成图形的箔镀以锡。29. The method of claim 25, wherein said metal is copper and further comprising plating the patterned foil with tin prior to step (3).30、如权利要求29的方法，特征在于其中粘接步骤（8）是通过在基板和复合层之间加一粘接膜层来完成的。30. The method of claim 29, wherein the bonding step (8) is performed by interposing an adhesive film layer between the substrate and the composite layer.31、如权利要求25的方法，特征在于还包括绝缘材料利用激光束来形成图形。31. The method of claim 25, further comprising patterning the insulating material using a laser beam.32、制造多层PWB的方法，特征在于包括：32. A method for manufacturing a multilayer PWB, comprising:-在先存的支承导体图形的基板上形成敷箔绝缘层，- forming a foil-coated insulating layer on a pre-existing substrate supporting a conductor pattern,-在预定的中间层上穿过敷箔形成连接图形的窗口，- forming a window of connection pattern through the foil on the predetermined intermediate layer,-除去暴露在所述窗口下面的绝缘层部分，以形成开孔，该开孔通过所述绝缘层向下到达所述基板上的所述下层导体图形的选择点，- removing the portion of the insulating layer exposed below the window to form an opening through the insulating layer down to a selected point of the underlying conductor pattern on the substrate,-从所述的点通过所述小孔进行敷镀，和- plating from said point through said aperture, and-有选择地除去所述箔的表面，在所述PWB的上表面上留下新的导体图形。- Selectively removing the surface of the foil, leaving a new conductor pattern on the upper surface of the PWB.33、如权利要求32的方法，特征在于还包括重复这些步骤以产生多层新的（通过各自的绝缘层连接到下层的）导体层。33. The method of claim 32, further comprising repeating the steps to produce a plurality of new conductor layers connected to the underlying layer through respective insulating layers.34、如权利要求32的方法，特征在于其中所述的基板是一块穿孔的PWB平板。34. The method of claim 32, wherein said substrate is a perforated PWB plate.35、如权利要求32的方法，特征在于其中所述的基板是一块穿孔的双面PWB平板，其加工步骤是在所述基板的两面同时进行的。35. The method of claim 32, wherein said substrate is a perforated double-sided PWB and said processing steps are performed simultaneously on both sides of said substrate.36、如权利要求32的方法，特征在于其中所述形成窗口的步骤是通过对所述箔进行光蚀刻来完成的。36. The method of claim 32, wherein said step of forming windows is performed by photoetching said foil.37、如权利要求32的方法，特征在于其中所述除去绝缘层部分的步骤是利用等离子体蚀刻法来完成的。37. The method of claim 32, wherein the step of removing portions of the insulating layer is performed by plasma etching.38、如权利要求32的方法，特征在于其中所述绝缘层是由一种从热塑和热固树脂组中选择的材料制成的。38. The method of claim 32, wherein said insulating layer is made of a material selected from the group consisting of thermoplastics and thermosetting resins.39、如权利要求32的方法，特征在于其中所述穿过所述绝缘层的开孔的高宽比约为2或更小些。39. The method of claim 32, wherein said opening through said insulating layer has an aspect ratio of about 2 or less.40、制造多层PWB的方法，特征在于包括：40. A method for manufacturing a multilayer PWB, comprising:-提供一块两面敷有箔的绝缘芯板层，- provide an insulating core layer with foil coated on both sides,-在预定中间层的至少一面的箔上形成连接图形的窗口，- forming a window for the connection pattern on the foil of at least one side of the predetermined intermediate layer,-消除暴露在所述窗口下面的所述芯板层部分，以提供向下到达另一面下层箔的开口，- eliminating the portion of the core layer exposed below the window to provide an opening down to the other underlying foil,-从所述下层箔穿过所述开孔进行敷镀，和- plating from the underlying foil through the opening, and-除去所选的所述芯板两面箔的表面，留下各自的导体图形。- removing selected surfaces of the foils on both sides of the core board, leaving respective conductor patterns.41、如权利要求40的方法，特征在于还包括：41. The method of claim 40, further comprising:-在所述芯板两面形成有导体图形的顶上制作敷箔绝缘层，- a foil-coated insulating layer is formed on top of the conductor patterns formed on both sides of the core board,-在予定的相应中间层的敷箔上形成连接图形的窗口，- forming windows of connection patterns on predetermined corresponding intermediate layer foils,-清除暴露在所述窗口下面的所述绝缘层部分，以提供向下到达下层导体图形点的开孔，- removing the portion of the insulating layer exposed below the window to provide an opening down to the underlying conductor pattern point,-从所述点穿过所述绝缘层进行敷镀，和- plating from said point through said insulating layer, and-除去所选的PWB两面上所述敷箔的表面，留下各自的导电图形。- Remove the foiled surfaces on both sides of the selected PWB, leaving the respective conductive patterns.42、如权利要求40的方法，特征在于其中所述形成窗口的步骤是通过进行光蚀刻来完成的。42. The method of claim 40, wherein the step of forming the window is performed by photolithography.43、如权利要求40的方法，特征在于其中所述除去绝缘层部分的步骤是用等离子体蚀刻法来实现的。43. The method of claim 40, wherein the step of removing portions of the insulating layer is performed by plasma etching.44、如权利要求41的方法，特征在于其中所述绝缘芯板层是用尺寸稳定的材料制成的，所述加到所述芯板层顶上的绝缘层是由一种从热塑和热固树脂组中选择的材料制成的。44. The method of claim 41 wherein said insulating core layer is formed of a dimensionally stable material and said insulating layer applied atop said core layer is formed of a material selected from the group consisting of thermoplastics and thermosetting resins.45、如权利要求41的方法，特征在于其中所述绝缘芯板层是由Kapton制成的，所述附加绝缘层是由聚四氟乙烯制成的。45. The method of claim 41, wherein said insulating core layer is made of Kapton and said additional insulating layer is made of polytetrafluoroethylene.46、利用权利要求1的方法制成的PWB。46. A PWB made by the method of claim 1.47、利用权利要求9的方法制成的PWB。47. A PWB made by the method of claim 9.48、利用权利要求19的方法制成的PWB。48. A PWB made by the method of claim 19.49、利用权利要求22的方法制成的PWB。49. A PWB made by the method of claim 22.50、利用权利要求25的方法制成的PWB。50. A PWB made by the method of claim 25.51、利用权利要求32的方法制成的PWB。51. A PWB made by the method of claim 32.52、利用权利要求40的方法制成的PWB。52. A PWB made by the method of claim 40.53、利用权利要求41的方法制成的PWB。53. A PWB made by the method of claim 41.54、一种多层PWB，特征在于具有包括隐蔽通路在内的完全用添加工艺形成的板上导体。54. A multilayer PWB characterized by having on-board conductors, including buried vias, formed entirely by additive processes.55、一种多层PWB，特征在于其中所有的中间层的连接件是由从下层金属点上敷镀的实心通路来构成的。55. A multilayer PWB wherein all intermediate layer connections are formed by solid vias plated from underlying metal points.56、一种多层PWB，特征在于具有由PDF制成的绝缘层，该绝缘层上带有从先前层金属点开始形成的空洞，所述的空洞被充以敷镀的金属，以形成实心的导体和中间层通路。56. A multi-layer PWB characterized by having an insulating layer made of PDF with cavities formed therein starting from metal points of a previous layer, said cavities being filled with plated metal to form solid conductors and inter-layer vias.57、一种多层PWB，特征在于包括一块双面的尺寸稳定的芯板，在该板的两面具有内部连接的导体图形和至少两个各与塑性绝缘层形成复合层的外层，支承外面导体图形的塑性绝缘层是由一种从热塑和热固树脂组中选择的材料构成的，所述塑性绝缘层在所述芯板上的下层导体图形所选的金属点上面形成小孔，所述小孔被充以实心金属直到所述绝缘层的外表面上的导体层。57. A multilayer PWB characterized by comprising a double-sided dimensionally stable core board having internally connected conductor patterns and at least two outer layers each forming a composite layer with a plastic insulating layer on both sides of the board, the plastic insulating layer supporting the outer conductor pattern being made of a material selected from the group consisting of thermoplastic and thermosetting resins, the plastic insulating layer forming small holes above selected metal points of the lower conductor pattern on the core board, the small holes being filled with solid metal up to the conductor layer on the outer surface of the insulating layer.

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