Drawings
The accompanying drawings provide a further understanding of the embodiments of the utility model and are incorporated in and constitute a part of this specification. These drawings and description serve to illustrate principles of some embodiments. It should be noted that all illustrations are schematic, and relative dimensions and proportions are adjusted for ease of illustration and drawing. The same reference signs represent corresponding or similar features in different embodiments.
Fig. 1 to 3 are schematic views of a semiconductor device according to a first preferred embodiment of the utility model; wherein:
fig. 1 is a schematic top view of a semiconductor device of the present utility model;
FIG. 2 is a schematic cross-sectional view taken along line A-A' of FIG. 1; and
Fig. 3 is a schematic cross-sectional view along the line B-B' in fig. 1.
Fig. 4 to 15 are schematic views illustrating a method for fabricating a semiconductor device according to a first preferred embodiment of the utility model; wherein:
fig. 4 is a schematic cross-sectional view of the semiconductor device of the present utility model after forming plug holes;
fig. 5 is another cross-sectional view of the semiconductor device of the present utility model after forming plug holes;
fig. 6 is a schematic cross-sectional view of the semiconductor device of the present utility model after forming a semiconductor material layer;
Fig. 7 is another schematic cross-sectional view of the semiconductor device of the present utility model after forming a semiconductor material layer;
Fig. 8 is a schematic cross-sectional view of the semiconductor device of the present utility model after performing a first etching process;
fig. 9 is another cross-sectional view of the semiconductor device of the present utility model after performing a first etching process;
fig. 10 is a schematic cross-sectional view of a semiconductor device of the present utility model after forming a dielectric material layer;
fig. 11 is another schematic cross-sectional view of the semiconductor device of the present utility model after forming a dielectric material layer;
fig. 12 is a schematic cross-sectional view of the semiconductor device of the present utility model after forming the first spacer structure;
Fig. 13 is another schematic cross-sectional view of the semiconductor device of the present utility model after forming the first spacer structure;
Fig. 14 is a schematic cross-sectional view of the semiconductor device of the present utility model after forming a second etching process; and
Fig. 15 is another schematic cross-sectional view of the semiconductor device of the present utility model after forming a second etching process.
Fig. 16 is a schematic top view of a semiconductor device according to a second preferred embodiment of the utility model.
Wherein reference numerals are as follows:
10. 30 semiconductor device
100. Substrate and method for manufacturing the same
100A storage area
100B peripheral region
102. Active region
104. Shallow trench isolation
110. Insulating layer
112. Oxide layer
114. Nitride layer
116. Oxide layer
120. Word line
122. Dielectric layer
124. Gate dielectric layer
126. Gate electrode
128. Cover layer
130. Bit line
130A bit line plug
132. Semiconductor layer
134. Barrier layer
136. Metal layer
138. Capping layer
140. 340 Dummy bit line
142. 342 Isolation structure
150. First spacer structure
152. First spacer layer
154. Insulating interlayer
156. Second spacer layer
160. 360 Second spacer structure
162. Third spacer layer
164. Conductive intermediate layer
166. Fourth spacer layer
170. Plug-in connector
172. First plug
174. Third plug
176. Second plug
180. Connecting pad
182. Conductive barrier layer
182A first conductive material
184. Contact metal layer
184A second conductive material
200. Mask layer
202. 204, 206, 212, 220 Plug holes
202A insulating material
208. Semiconductor material
210. Perforating the hole
214. Dielectric material layer
214A second dielectric material
216. Dielectric layer
218. Void layer
254. A first material layer
254A first dielectric material
264. A second material layer
266. Spacer material layer
342. First dummy bit line
344. Second dummy bit line
D1 Direction of
D2 First direction
D3 Second direction
E1 First etching process
E2 Second etching process
Y vertical direction
Detailed Description
The following description sets forth the preferred embodiments of the present utility model and, together with the accompanying drawings, provides a further understanding of the utility model, as well as details of the structure and advantages to be achieved, to those skilled in the art to which the utility model pertains. It is to be understood that the following exemplary embodiments may be substituted, rearranged, and mixed for the features of several different embodiments without departing from the spirit of the utility model to accomplish other embodiments.
Referring to fig. 1 to 3, a schematic diagram of a semiconductor device 10 according to a first embodiment of the present utility model is shown, wherein fig. 1 is a schematic top view of the semiconductor device 10, and fig. 2 and 3 are schematic cross-sectional views of the semiconductor device 10. As shown in fig. 1, the semiconductor device 10 includes a substrate 100, a plurality of bit lines 130, a plurality of first spacer structures 150, and a plurality of second spacer structures 160. The substrate 100 may be, for example, but not limited to, a silicon substrate, a silicon-containing substrate (e.g., siC, siGe), an epitaxial silicon substrate (epitaxial silicon substrate), a silicon-on-insulator substrate (silicon-on-insulator substrate), or other suitable material. A plurality of shallow trench isolations 104 (e.g., comprising silicon oxide) are further disposed within the substrate 100 to define a plurality of active regions 102 extending in the direction D1 within the substrate 100. A plurality of bit lines 130 are disposed on the substrate 100 to be spaced apart from each other and extend along the first direction D2 so as to simultaneously interleave with the plurality of active regions 102. The first spacer structures 150 are disposed on two opposite sidewalls of each bit line 130. The second spacer structure 160 is disposed on the substrate 100, and an end of the second spacer structure 160 and an end of the first spacer structure 150 are coupled to each other. It should be noted that, at least some of the materials in the first spacer structure 150 and the second spacer structure 160 are different, for example, include an insulating material and a conductive material, so as to achieve different isolation effects in different regions, which is beneficial to improving the structural reliability of the semiconductor device 10 and further improving the operation performance thereof.
In one embodiment, the second spacer structures 160 are disposed on sidewalls of the plurality of dummy bit lines 140 that also extend in the first direction D2, respectively. One end of the dummy bit line 140 is connected to the end of the bit line 130 in the first direction D2, and the other end is connected to each other in the second direction D3, so that each of the second spacer structures 160 has a U-shaped top view structure, as shown in fig. 1, but not limited thereto. On the other hand, each of the first spacer structures 150 has an I-shaped top view structure. It should be noted that, in fig. 1 of the present embodiment, the arrangement and relative relationship between specific components (such as the word line 120, the bit line 130, etc.) are omitted for clarity, such as the detailed compositions of the first spacer structure 150 and the second spacer structure 160, but those skilled in the art should clearly understand the positions of the components in fig. 1 through the schematic cross-sectional views shown in fig. 2 or fig. 3.
As shown in fig. 2 and 3, each of the first spacer structures 150 includes a first spacer layer 152 (e.g., including silicon nitride, silicon carbonitride), an insulating intermediate layer 154, and a second spacer layer 156 (e.g., including silicon nitride, silicon carbonitride) sequentially disposed on sidewalls of each of the bit lines 130, and each of the second spacer structures 160 includes a third spacer layer 162 (e.g., including silicon nitride, silicon carbonitride), a conductive intermediate layer 164, and a fourth spacer layer 166 (e.g., including silicon nitride, silicon carbonitride) sequentially disposed on sidewalls of each of the dummy bit lines 140. The insulating interlayer 154 further includes a first dielectric material 254a (e.g., including silicon nitride, silicon carbonitride) and a second dielectric material 214a (e.g., including silicon oxide, silicon oxycarbide) sequentially stacked in the vertical direction Y, and the conductive interlayer 164 includes, but is not limited to, materials such as titanium, titanium nitride, tantalum nitride, and the like. Since each dummy bit line 140 is coupled to an end of each bit line 130, an end of the first spacer layer 152 of each first spacer structure 150 is coupled to an end of the third spacer layer 162 of each second spacer structure 160, and an end of the second spacer layer 156 of each first spacer structure 150 is coupled to an end of the fourth spacer layer 166 of each second spacer structure 160, but not limited thereto. In a preferred embodiment, the first spacer layer 152 and the third spacer layer 162, and/or the second spacer layer 156 and the fourth spacer layer 166 comprise the same material, for example, so that the first spacer layer 152 and the third spacer layer 162, and/or the second spacer layer 156 and the fourth spacer layer 166 may extend continuously in the first direction D2, or be integrally formed.
As shown in fig. 1, the substrate 100 of the semiconductor device 10 includes a memory region (cell region) 100A with relatively high device integration and a peripheral region 100B with relatively low device integration, where the memory region 100A and the peripheral region 100B are disposed, for example, but not limited to, adjacently. The active region 102, the bit line 130 and the first spacer structure 150 are all disposed in the memory region 100A, and the dummy bit line 140 and the second spacer structure 160 are all disposed in the peripheral region 100B. Further, the memory region 100A includes a plurality of word lines 120 disposed in the substrate 100 and extending along the second direction D3 while being spaced apart from each other. It should be readily understood by those skilled in the art that the extending directions of the active regions 102, the word lines 120 and the bit lines 130 are different, and the extending direction of the word lines 120 (the second direction D3) is perpendicular to the extending direction of the bit lines 130 (the first direction D2), and is staggered with the active regions 102 and the bit lines 130.
In detail, as shown in fig. 1 and 2, each bit line 130 includes a semiconductor layer 132 (e.g., including a semiconductor material such as doped polysilicon, doped amorphous silicon, etc.), a barrier layer 134 (e.g., including a conductive barrier material such as titanium and/or titanium nitride, tantalum, and/or tantalum oxide), a metal layer 136 (e.g., including a low-resistance metal material such as tungsten, aluminum, or copper), and a capping layer 138 (e.g., including an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride) stacked in order. The bit line 130 is in principle disposed on the insulating layer 110 on the substrate 100, and a portion of the semiconductor layer 132 extends into a portion of the substrate 100 to form a Bit Line Contact (BLC) 130a. Thus, the bit line 130 is electrically connected to the active region 102 through the bit line plug 130a integrally formed therewith, and receives or transmits signals from the substrate 100. On the other hand, as shown in fig. 1 and 3, each word line 120 includes a dielectric layer 122, a gate dielectric layer 124 and a gate 126, and a cap layer 128 covering the gate 126, which are sequentially stacked, wherein the surface of the cap layer 128 may be aligned with the top surface of the substrate 110, such that each word line 120 serves as a Buried Word Line (BWL) of the semiconductor device 10. The word line 120 is isolated from the bit line 130 by an insulating layer 110 disposed on the substrate 110. In one embodiment, the insulating layer 110 preferably has a composite layer structure, for example, but not limited to, an oxide-nitride-oxide (ONO) layer including an oxide layer 112, a nitride layer 114 and an oxide layer 116, which are stacked in sequence.
As further shown in fig. 1, 2 and 3, the semiconductor device 10 further includes a plurality of plugs 170 disposed between the adjacent bit lines 130 and the adjacent dummy bit lines 140, respectively, and electrically isolating each plug 170 adjacent thereto in the first direction D2 by a plurality of isolation structures 142. The plug 170 further includes a plurality of first plugs 172 and a plurality of second plugs 176. The first plugs 172 are alternately arranged with the bit lines 130 in the second direction D3, such that the first spacers 150 are disposed between the first plugs 172 and the bit lines 130, and the second plugs 176 are alternately arranged with the bit lines 130 or the dummy bit lines 140 in the second direction D3, such that the first spacers 150 or the second spacers 160 are disposed between the second plugs 176 and the bit lines 130 or the dummy bit lines 140.
In detail, the bottom portion of each first plug 172 extends into the substrate 100 to electrically connect to each active region 102, and the top portion of each first plug 172 is further provided with a connection pad 180, as shown in fig. 2. Thus, the first plugs 172 may be used as storage node plugs (storage node contact, SNC) of the semiconductor device 10 to electrically connect to Storage Nodes (SN) disposed later, respectively. In one embodiment, the first plugs 172 are made of a semiconductor material such as doped polysilicon, doped amorphous silicon, or a metal material with low resistance such as aluminum (Al), titanium, copper (Cu), or tungsten (W), and preferably include the same semiconductor material 208 as the semiconductor layer 132 of each bit line 130, but not limited thereto. In another embodiment, the connection pad 180 includes a conductive barrier layer (barrier layer) 182 and a contact metal layer (contact METAL LAYER) 184 stacked in sequence, wherein the conductive barrier layer 182 includes, for example, titanium nitride, tantalum nitride, tungsten nitride (WN) or other suitable conductive barrier materials, preferably includes the same conductive material as the intermediate layer 164, and the contact metal layer includes, for example, a low-resistance metal material including aluminum, titanium, copper or tungsten, preferably includes tungsten, but is not limited thereto.
On the other hand, the second plug 176 is disposed on the insulating layer 110 of the substrate 100, and does not contact any active region 102, as shown in fig. 3. Thus, the second plug 176 can be used as a dummy plug of the semiconductor device 10, and the device integration of the memory region 100A and the peripheral region 100B is balanced during the process of manufacturing the plug 170, so as to improve the manufacturing yield. In detail, each of the second plugs 176 is alternately arranged with each of the isolation structures 142 in the first direction D2, and includes a cross section having a smaller upper portion and a larger lower portion. That is, the semiconductor device 10 further includes a plurality of dielectric layers 216 respectively disposed on the upper half sidewalls of the second plugs 176. The dielectric layer 216 physically contacts the isolation structure 142 and the upper half of the third spacer layer 162 of the second spacer structure 160 to further isolate the adjacent second plug 176 and define the cross-sectional structure of the second plug 176. In one embodiment, the second plug 176 includes a first conductive material 182a and a second conductive material 184a stacked in sequence, wherein the first conductive material 182a includes, for example, titanium nitride, tantalum nitride, tungsten nitride or other suitable conductive barrier material, preferably includes a conductive material similar to the conductive intermediate layer 164, and the second conductive material 184a includes, for example, a metal material with a low resistance such as aluminum, titanium, copper or tungsten, preferably includes a conductive material similar to the contact metal layer 184, but is not limited thereto. In addition, in another embodiment, the plug 170 may further include at least one third plug 174, for example, disposed between the second plug 176 and the first plug 172. The third plug 174 is also disposed on the insulating layer 110 of the substrate 100 without contacting any of the active regions 102. In one embodiment, the third plug 174 includes, for example, the insulating material 202a and the semiconductor material 208 stacked sequentially in the vertical direction Y to be synchronized as a dummy plug of the semiconductor device 10. The semiconductor material 208 is, for example, the same as the semiconductor material 208 of the first plug 172, but not limited thereto.
According to the semiconductor device 10 of the present embodiment, the first spacer structure 150 including the insulating interlayer 154 and the second spacer structure 160 including the conductive interlayer 164 are disposed on the sidewalls of the bit line 130 and the dummy bit line 140, respectively, so that the first spacer structure 150 and the second spacer structure 160 are at least partially made of different materials. Accordingly, the first spacer structure 150 and the second spacer structure 160 can achieve different isolation effects in the storage region 100A and the peripheral region 100B of the semiconductor device 10, thereby improving the structural reliability of the semiconductor device 10 and further improving the operation performance thereof. On the other hand, the first spacer layer 152 and the second spacer layer 156 on both sides of the insulating interlayer 154 and the third spacer layer 162 and the fourth spacer layer 166 on both sides of the conductive interlayer 164 may be made of the same material or integrally formed, so that the manufacturing process of the first spacer structure 150 and the second spacer structure 160 may be simplified. In this arrangement, the semiconductor device 10 of the present embodiment may be used as a dynamic random access memory (dynamic random access memory, DRAM) device, and the minimum memory cell (memory cell) in the DRAM array is formed by at least one capacitor (not shown) disposed over the first plug 172 and at least one transistor element (not shown) disposed in the substrate 100, which receives voltage information from the bit line 130 and the word line 120.
In order to enable those skilled in the art to easily understand the semiconductor device 10 of the present utility model, a method for fabricating the semiconductor device 10 of the present utility model will be further described below.
Referring to fig. 4 to 15, which are schematic diagrams illustrating a method for fabricating a semiconductor device 10 according to a preferred embodiment of the present utility model, fig. 4, 6, 8, 10, 12 and 14 are schematic diagrams illustrating a cross section of the semiconductor device 10 along a tangent line A-A 'during fabrication, and fig. 5, 7, 9, 11, 13 and 15 are schematic diagrams illustrating a cross section of the semiconductor device 10 along a tangent line B-B' during fabrication. Although the top view of the semiconductor device 10 during the manufacturing process is not shown in the present embodiment, the specific positions of the tangent line A-A 'and the tangent line B-B' on the semiconductor device 10 and the top view of the semiconductor device 10 during the manufacturing process can be clearly understood by those skilled in the art with reference to the top view of the semiconductor device 10 shown in fig. 1.
First, as shown in fig. 4 and 5, a substrate 100 is provided, and shallow trench isolation 104 is formed in the substrate 100 to define a plurality of active regions 102 in the substrate 100. In one embodiment, the shallow trench isolation 104 is formed, for example, by forming a plurality of trenches (not shown) in the substrate 100 by an etching process, and then filling at least one insulating material (such as silicon oxide) into the trenches to form the shallow trench isolation 104 with a surface flush with the top surface of the substrate 100, but not limited thereto. Next, a plurality of word lines 120 extending along the second direction D3 are formed within the substrate 100. In one embodiment, the word line 120 is fabricated by, but not limited to, forming a plurality of trenches (not shown) through the active regions 102 and the shallow trench isolation 104, and then sequentially forming a dielectric layer 122 covering the entire surface of the trenches, a gate dielectric layer 124 covering the bottom half of the trenches, a gate 126 filling the bottom half of the trenches, and a cap layer 128 filling the top half of the trenches. Further, an insulating layer 110, a plurality of bit lines 130 extending along the first direction D2, and a plurality of dummy bit lines 140 respectively connecting end portions of the respective bit lines 130 are formed on the substrate 100. Each bit line 130 is electrically connected to the active region 102 through a bit line plug 130a correspondingly formed below. In one embodiment, the fabrication process of the bit line 130 and the bit line plug 130a includes, but is not limited to, the following steps. Firstly, an opening (not shown) penetrating the insulating layer 110 and partially exposing the surface of the substrate 100 is formed through a mask layer (not shown), a semiconductor material (not shown) is formed on the substrate 100, for example, a semiconductor material including polysilicon, doped amorphous silicon, etc. is filled into the opening, then a barrier material layer (not shown), for example, a conductive barrier material including titanium and/or titanium nitride, tantalum and/or tantalum oxide, etc., a metal material layer (not shown), for example, a metal material including a low-resistance metal material including tungsten, aluminum, copper, etc., and a capping material layer (not shown), for example, an insulating material including silicon oxide, silicon nitride, silicon oxynitride, etc., are sequentially formed, and finally, the bit line 130 and the bit line plug 130a are simultaneously formed through a patterning process. Then, a plurality of isolation structures 142 are formed between the adjacent bit lines 130 and the adjacent dummy bit lines 140, and then deposition and etching back processes are sequentially performed to deposit an insulating material layer 202 on the insulating layer 110, so as to fill the remaining spaces between the adjacent bit lines 130 and the adjacent dummy bit lines 140. In one embodiment, the insulating material layer 202 includes, but is not limited to, an insulating material such as silicon oxide, silicon oxynitride, etc.
Then, as shown in fig. 4 and 5, a mask layer 200 is formed on the insulating material layer 202 to cover the peripheral region 100B and a portion of the storage region 100A of the substrate 100, and an etching process is performed on the insulating material layer 202 through the mask layer 200 to remove the insulating material layer 202, so as to form a plurality of plug holes 204 under which the corresponding active regions 102 are exposed, and at least one plug hole 206 exposing no active region 102 and retaining the insulating material 202a of the insulating material layer 202 at the bottom portion. Plug hole 204 and plug hole 206 are located in memory area 100A, for example, but not limited thereto. It should be noted that although only one plug hole 206 is illustrated in the drawings of the present embodiment, it should be understood that, if viewed from a top view (not shown) as shown in fig. 1, the method of manufacturing the present embodiment can simultaneously form a plurality of plug holes 206 through the etching process. Then, the mask layer 200 is completely removed.
Before forming the isolation structure 142, the first spacer layer 152 and the first material layer 254 and a spacer material layer (not shown) that entirely covers the bit line 130, the first spacer layer 152 and the first material layer 254 are sequentially formed on the sidewalls of the bit line 130, and the third spacer layer 162 and the second material layer 264 and a spacer material layer 266 that entirely covers the dummy bit line 140, the third spacer layer 162 and the second material layer 264 are sequentially formed on the sidewalls of the dummy bit line 140. In one embodiment, the first spacer layer 152 and the third spacer layer 162 (e.g., including silicon nitride, silicon carbonitride), the first material layer 254 and the second material layer 264 (e.g., including silicon oxide, silicon oxycarbide), and the spacer material layer 266 (e.g., including silicon nitride, silicon carbonitride) are formed by, for example, a same deposition process, such that the first spacer layer 152 and the third spacer layer 162, the first material layer 254 and the second material layer 264, and the spacer material layer 266 comprise a same material, are continuously extended, and are integrally formed, respectively. The first spacer layer 152, the third spacer layer 162, the spacer material layer and the spacer material layer 266 preferably comprise the same material, but are not limited thereto. Note that the etching process Shi Hangshi removes the spacer material layer overlying the bit line 130, the first spacer layer 152, and the top surface of the first material layer 254, forming a second spacer layer 156 as shown in fig. 4. The spacer material layer 266 covering the top surfaces of the dummy bit line 140, the third spacer layer 162, and the second material layer 264 is not removed due to the mask layer 200, and remains covered on the top surfaces of the dummy bit line 140, the third spacer layer 162, and the second material layer 264, as shown in fig. 5.
As shown in fig. 6 and 7, a deposition process is performed on the substrate 100 to form a semiconductor material layer (not shown) filled into the plug holes 204 and 206 and further covering the top surfaces of the components such as the bit lines 130, the dummy bit lines 140, and the isolation structures 142, and then an etch back process is performed to remove the semiconductor material layer covering the top surfaces of the components such as the bit lines 130, the dummy bit lines 140, and the isolation structures 142, and the semiconductor material 208 filled into the plug holes 204 and 206 remains. The semiconductor material 208 filled in the plug hole 206 is directly located on the insulating material 202a in the vertical direction Y.
As shown in fig. 8 and 9, a first etching process E1 is performed to partially remove the remaining insulating material layer 202, forming a plurality of plug holes 212 that do not expose the active region 102 and retain the insulating material 202a of the insulating material layer 202 at the bottom portion. And, the first material layer 254 similar to the material of the insulating material layer 202 is removed through the first etching process E1, and a plurality of openings 210 are formed between the first spacer layer 152 and the second spacer layer 156, wherein the bottom portion of the openings remains the dielectric material 254a of the first material layer 254. Note that spacer layer 264, which is also similar to the material of insulating material layer 202, is still covered by spacer material layer 266 and is not partially removed, as shown in fig. 9.
As shown in fig. 10 and 11, a dielectric material layer 214, such as a dielectric material including silicon nitride, silicon carbonitride, etc., is formed on the substrate 100 to conformally cover the exposed surfaces of the components such as the spacer material layer 266, the isolation structure 142, the plug hole 212, etc., and also to cover the semiconductor material 208 between the first spacer layer 152, the second spacer layer 156, the bit line 130, and the adjacent bit line 130, and further to fill the opening 210 between the first spacer layer 152 and the second spacer layer 156.
As shown in fig. 12 and 13, a planarization process is performed on the dielectric material layer 214 (shown in fig. 11), and the dielectric material layer 214 covering the spacer material layer 266, the isolation structure 142, the semiconductor material 208, and other components is removed to form a plurality of dielectric layers 216 on the upper half sidewalls of the isolation structure 142. At the same time, the planarization process is performed to partially remove the spacer material layer 266 (as shown in fig. 11) similar to the material of the dielectric material layer 214, so as to form the fourth spacer layer 166, and expose the second material layer 264 between the third spacer layer 162 and the fourth spacer layer 166. On the other hand, the planarization process also removes the dielectric material layer 214 (shown in fig. 10) covering the first spacer layer 152, the second spacer layer 156, the bit line 130 and the semiconductor material 208 simultaneously, and only the dielectric material 214a of the dielectric material layer 214 filled in the openings 210 remains. Thus, the dielectric material 254a and the dielectric material 214a sequentially stacked between the first spacer layer 152 and the second spacer layer 156 together form the insulating interlayer 154, and the insulating interlayer 154 and the first spacer layer 152 and the second spacer layer 156 on both sides thereof together form the first spacer structure 150 as shown in fig. 1 and 2.
As shown in fig. 14 and 15, a second etching process E2 is performed to completely remove the insulating material 202a remaining between the adjacent isolation structures 142 and the second material layer 264 with similar material, so as to form a plurality of plug holes 220 exposing the top surface of the insulating layer 110, and a gap layer 218 is formed between the third spacer layer 162 and the fourth spacer layer 166. On the other hand, the second etching process E2 further removes the semiconductor material 208 with similar etching selectivity to a height that does not fill the plug holes 204 and 206.
Subsequently, at least one deposition process may be performed on the substrate 100 to sequentially form a conductive barrier material layer (not shown, for example, comprising titanium, titanium nitride, tantalum nitride, tungsten nitride, or other suitable conductive barrier material) and a contact metal material layer (not shown, for example, comprising a low-resistance metal material such as aluminum, titanium, copper, or tungsten) such that the conductive barrier material layer fills the void layer 218 and conformally covers the exposed surfaces of the dummy bit line 140, the dielectric layer 216, the plug hole 220, the plug hole 204, the plug hole 206, and the bit line 130, and the contact metal material layer fills the remaining spaces of all of the plug holes 220, 204, 206 and further covers the top surfaces of the components such as the dummy bit line 140, the isolation structure 142, and the bit line. Then, the contact metal material layer and the conductive barrier material layer covering the dummy bit line 140, the isolation structure 142, the bit line, and the like are partially removed by a patterning process, so that the conductive barrier material layer filled in the void layer 218 forms a conductive intermediate layer 164, and the conductive intermediate layer 164 and the third spacer layer 162 and the fourth spacer layer 166 on both sides thereof together form the second spacer structure 160 as shown in fig. 1 and 3. On the other hand, the contact metal material layer and the conductive barrier material layer filled in the plug holes 220 form a plurality of second plugs 176, and the contact metal material layer and the conductive barrier material layer filled in the plug holes 204, 206 form a plurality of connection pads 180, respectively physically contacting the plurality of first plugs 172 and the at least one third plug 174 formed simultaneously thereunder. Thus, the fabrication of the plurality of plugs 170 as shown in fig. 1, 2 and 3 is completed. Then, a deposition and etch back process is performed on the substrate 100, and an insulating material (not shown) is filled between the connection pads 180, thereby completing the fabrication of the semiconductor device 10 shown in fig. 1, 2 and 3.
According to the method of fabricating the semiconductor device 10 of the present embodiment, the first spacer structure 150 and the second spacer structure 160 with at least partial materials different from each other are formed in different regions (the storage region 100A and the peripheral region 100B) on the substrate 100, for example, the insulating interlayer 154 and the conductive interlayer 164 are respectively included to achieve different isolation effects in different regions. Since the manufacturing processes of the first spacer structure 150 and the second spacer structure 160 are reasonably integrated in the manufacturing process of the plug 170, no extra operation is required, and therefore, the manufacturing method of the semiconductor device 10 of the embodiment can form the semiconductor device 10 with more optimized component structure and performance on the premise of simplifying the overall manufacturing process, thereby improving the operation performance of the semiconductor device 10. Then, a plurality of capacitors (not shown) can be further formed over the first plugs 172 of the semiconductor device 10, so that the semiconductor device 10 can function as the dynamic random access memory.
It should be readily understood by those skilled in the art that the semiconductor device and the method for manufacturing the same of the present utility model may have other aspects and are not limited to the foregoing, so as to meet the actual product requirements. Further embodiments or variations of the semiconductor device of the present utility model and its method of fabrication are described below. In order to simplify the description, the following description mainly aims at the differences of the embodiments, and the details of the differences will not be repeated. In addition, like elements in the various embodiments of the present utility model are labeled with like reference numerals to facilitate cross-reference between the various embodiments.
Referring to fig. 16, a top view of a semiconductor device 30 according to a second embodiment of the utility model is shown. The structure of the semiconductor device 30 of the present embodiment is substantially the same as that of the semiconductor device 10 of the foregoing embodiment, as shown in fig. 1 to 3 of the foregoing embodiment, and the same is not repeated here. The main difference between the semiconductor device 30 of the present embodiment and the foregoing embodiments is that the plurality of dummy bit lines 340 further includes a plurality of first dummy bit lines 342 and a plurality of second dummy bit lines 344 having different extension lengths, such that the second spacer structures 360 disposed on the sidewalls of each of the dummy bit lines 340 have a U-shaped top-down structure and an I-shaped top-down structure, respectively.
In detail, as shown in fig. 16, the first dummy bit lines 342 and the second dummy bit lines 344 extend in the first direction D2, respectively, and are alternately arranged in the second direction D3. One end of each first dummy bit line 342 is connected to an end of the bit line 130, and the other end is connected to an isolation structure 324. One end of each second dummy bit line 344 is also connected to the end of the bit line 130, and the other ends are connected to each other in the second direction D3. In this arrangement, the second spacer structures 360 disposed on the sidewalls of the first dummy bit line 342 and the second dummy bit line 344 have a corresponding U-shaped top-down structure and I-shaped top-down structure, and the second spacer structures 360 having the I-shaped top-down structure are just located between two opposite sidewalls of the second spacer structures 360 having the U-shaped top-down structure in the second direction D3, but not limited thereto. In addition, the features of the second spacer structure 360 in this embodiment, such as the detailed composition and the cross-sectional structure, are the same as those of the second spacer structure 160 in the previous embodiment, and will not be described again here, so that those skilled in the art can clearly understand the specific features with reference to the cross-sectional schematic diagram shown in fig. 3.
According to the semiconductor device 30 of the present embodiment, the first spacer structure 150 and the second spacer structure 360 with at least partial materials being different are disposed on the sidewalls of the bit line 130 and the dummy bit line 340, respectively, so as to achieve different isolation effects in different regions of the semiconductor device 30, thereby improving the structural reliability of the semiconductor device 30 and further improving the operation performance thereof.
The above description is only of the preferred embodiments of the present utility model and is not intended to limit the present utility model, but various modifications and variations can be made to the present utility model by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model should be included in the protection scope of the present utility model.