CN218585323U - High-efficiency acquisition gateway and system based on heterogeneous multi-core processor - Google Patents

Abstract

The utility model relates to a gateway technical field, in particular to gateway and system are gathered to high efficiency based on different structure multicore processor, the high efficiency gather the gateway including be used for with host computer communication connection's net gape for with application equipment end communication connection's bus port, different structure multicore processor and the data storage unit of being connected with different structure multicore processor electricity that is connected with net gape, bus port electricity respectively. The heterogeneous multi-core processor is loaded with a Li nux system and a freeRTOS system. The utility model provides a gateway system is gathered to high efficiency, through the application of heterogeneous multicore processor, the advantage of the two kinds of operating system of performance Li nux and freeRTOS can use complex functions such as Li nux system's database, network, can realize the high-efficient utilization of RS485 bus through the real-time of freeRTOS system again, has alleviateed the CPU rate of utilization of Li nux system simultaneously, effectively promotes communication efficiency.

Description

Translated fromChinese

一种基于异构多核处理器的高效采集网关及系统A high-efficiency acquisition gateway and system based on heterogeneous multi-core processors

技术领域technical field

本实用新型涉及网关技术领域，特别涉及一种基于异构多核处理器的高效采集网关及系统。The utility model relates to the technical field of gateways, in particular to an efficient acquisition gateway and system based on heterogeneous multi-core processors.

背景技术Background technique

工业测试领域，测试系统由网关和多台终端组成，网关和终端通过总线连接(如RS485)。网关需要通过轮询读取终端的数据，同时进行数据存储以及负责同上位机的通信。网关需要使用数据库和网络功能，通常采用Linux系统。In the field of industrial testing, the test system consists of a gateway and multiple terminals, and the gateway and terminals are connected by a bus (such as RS485). The gateway needs to read the data of the terminal through polling, and at the same time store the data and be responsible for the communication with the host computer. The gateway needs to use database and network functions, usually using Linux system.

目前现有的智能网关有两种类型，第一种类型是单采用Linux系统，实现RS485收发和数据库存储、上位机通信功能。采用这类网关的测试系统，其RS485总线利用率较低，且CPU使用率过高。第二种类型是采用两块芯片，一块运行Linux系统，实现数据库存储和上位机通信；另一块运行裸机或FreeRTOS程序，实现RS485收发。采用这类网关的测试系统，需要使用两块芯片，占用更多的布板空间，且芯片之间无法使用片内通信，CPU运行时间占比较高，无法得到保证测试系统的运行可靠性。At present, there are two types of existing intelligent gateways. The first type uses only the Linux system to realize RS485 transceiver, database storage, and host computer communication functions. The test system using this type of gateway has a low utilization rate of the RS485 bus and a high CPU utilization rate. The second type uses two chips, one runs Linux system to realize database storage and host computer communication; the other runs bare metal or FreeRTOS program to realize RS485 transceiver. The test system using this type of gateway needs to use two chips, which takes up more layout space, and the on-chip communication cannot be used between the chips, and the CPU running time accounts for a relatively high proportion, so the operation reliability of the test system cannot be guaranteed.

实用新型内容Utility model content

为解决上述现有技术中RS485总线的闲置率过高以及CPU使用率过高的不足，本实用新型提供一种基于异构多核处理器的高效采集网关，包括网口，用于与上位机通信连接；总线端口，用于与应用设备端通信连接；异构多核处理器，异构多核处理器分别与网口、总线端口电连接；数据存储单元，数据存储单元与异构多核处理器电连接。In order to solve the above-mentioned shortcomings of the high idle rate of the RS485 bus and the high CPU usage rate in the prior art, the utility model provides a high-efficiency acquisition gateway based on a heterogeneous multi-core processor, including a network port, for communicating with the host computer Connection; bus port, used for communication connection with application equipment; heterogeneous multi-core processor, heterogeneous multi-core processor is electrically connected to network port and bus port respectively; data storage unit, data storage unit is electrically connected to heterogeneous multi-core processor .

其中，异构多核处理器搭载Linux系统和freeRTOS系统；freeRTOS系统与总线端口通信连接，以用于采集应用设备端的数据信息；Linux系统与freeRTOS系统通信连接，以用于接收freeRTOS系统的数据信息并将数据信息存储至数据存储单元；Linux系统还与网口通信连接以用于接收上位机的查询数据命令以及将数据存储单元内的数据信息上传至上位机。Among them, the heterogeneous multi-core processor is equipped with Linux system and freeRTOS system; the freeRTOS system is connected to the bus port for collecting data information on the application device side; the Linux system is connected to the freeRTOS system for receiving the data information of the freeRTOS system and The data information is stored in the data storage unit; the Linux system is also connected to the network port for receiving the query data command of the host computer and uploading the data information in the data storage unit to the host computer.

在一实施例中，freeRTOS系统包括轮询线程单元以及优先级高于轮询线程单元的收发线程单元，轮询线程单元用于向应用设备端下发轮询命令并采集应用设备端的数据信息；收发线程单元用于接收Linux系统下发的命令并向Linux系统发送采集到的数据信息。In one embodiment, the freeRTOS system includes a polling thread unit and a sending and receiving thread unit with a higher priority than the polling thread unit, and the polling thread unit is used to issue a polling command to the application device and collect data information on the application device; The sending and receiving thread unit is used to receive commands issued by the Linux system and send the collected data information to the Linux system.

在一实施例中，收发线程单元具有休眠模块，休眠模块用于在向Linux系统发送采集到的数据信息后，控制收发线程单元进入线程休眠。In one embodiment, the sending and receiving thread unit has a dormancy module, and the dormancy module is used to control the sending and receiving thread unit to enter thread dormancy after sending the collected data information to the Linux system.

在一实施例中，Linux系统和freeRTOS系统通过RPMsg接口通信连接。In one embodiment, the Linux system and the freeRTOS system are communicatively connected through the RPMsg interface.

在一实施例中，异构多核处理器包含异构多核芯片，异构多核芯片包括Cotex-A53和Cotex-M4，Cotex-A53搭载Linux系统，Cotex-M4搭载freeRTOS系统。In one embodiment, the heterogeneous multi-core processor includes a heterogeneous multi-core chip, the heterogeneous multi-core chip includes Cotex-A53 and Cotex-M4, the Cotex-A53 is equipped with a Linux system, and the Cotex-M4 is equipped with a freeRTOS system.

在一实施例中，Cotex-A53有4个，Cotex-M4有1个。In one embodiment, there are four for Cotex-A53 and one for Cotex-M4.

在一实施例中，总线端口设置为uart串口。In one embodiment, the bus port is configured as a uart serial port.

在一实施例中，数据存储单元设置为eMMC存储器。In one embodiment, the data storage unit is configured as an eMMC memory.

本实用新型还提供一种高效采集网关系统，采用如上任一实施例所述的基于异构多核处理器的高效采集网关，还包括上位机、至少一个应用设备端以及数据传输总线，上位机、应用设备端分别通过数据传输总线与高效采集网关通信连接。The utility model also provides a high-efficiency collection gateway system, which adopts the high-efficiency collection gateway based on heterogeneous multi-core processors as described in any one of the above embodiments, and also includes a host computer, at least one application device end and a data transmission bus, the host computer, The application device side communicates with the high-efficiency acquisition gateway through the data transmission bus.

在一实施例中，数据传输总线设置为RS485总线。In one embodiment, the data transmission bus is configured as an RS485 bus.

基于上述，与现有技术相比，本实用新型提供的一种基于异构多核处理器的高效采集网关，通过异构多核处理器的运用，发挥Linux和freeRTOS两种操作系统的优点，既能使用Linux系统的数据库、网络等复杂功能，又能通过freeRTOS系统的实时性实现RS485总线的高效利用，同时减轻了Linux系统的CPU使用率，有效提升通信效率。Based on the above, compared with the prior art, the utility model provides a high-efficiency collection gateway based on heterogeneous multi-core processors. Through the use of heterogeneous multi-core processors, the advantages of both Linux and freeRTOS operating systems can be used. Using the database, network and other complex functions of the Linux system can realize the efficient utilization of the RS485 bus through the real-time performance of the freeRTOS system, and at the same time reduce the CPU usage of the Linux system and effectively improve communication efficiency.

本实用新型的其它特征和有益效果将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本实用新型而了解。本实用新型的目的和其他有益效果可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。Other features and beneficial effects of the utility model will be set forth in the following description, and partly become obvious from the description, or can be understood by implementing the utility model. The purpose and other beneficial effects of the utility model can be realized and obtained through the structures particularly pointed out in the specification, claims and accompanying drawings.

附图说明Description of drawings

为了更清楚地说明本实用新型实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本实用新型的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图；在下面描述中附图所述的位置关系，若无特别指明，皆是图示中组件绘示的方向为基准。In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the appended drawings in the following description The drawings are some embodiments of the present utility model. For those skilled in the art, other drawings can also be obtained according to these drawings without creative work; the positions described in the drawings in the following description Relationships, unless otherwise specified, are based on the directions drawn by the components in the diagram.

图1为本实用新型提供的高效采集网关的结构示意图；Fig. 1 is the structural representation of the efficient collection gateway that the utility model provides;

图2为本实用新型提供的高效采集网关在采集数据过程中测试RS485接口电平的时序图；Fig. 2 tests the sequence diagram of RS485 interface level in the high-efficiency collection gateway that the utility model provides in the process of collecting data;

图3为本实用新型提供的高效采集网关系统的结构示意图。Fig. 3 is a schematic structural diagram of the high-efficiency acquisition gateway system provided by the present invention.

具体实施方式Detailed ways

为使本实用新型实施例的目的、技术方案和优点更加清楚，下面将结合本实用新型实施例中的附图，对本实用新型实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本实用新型一部分实施例，而不是全部的实施例；下面所描述的本实用新型不同实施方式中所设计的技术特征只要彼此之间未构成冲突就可以相互结合；基于本实用新型中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本实用新型保护的范围。In order to make the purpose, technical solutions and advantages of the embodiments of the utility model more clear, the technical solutions in the embodiments of the utility model will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the utility model. Obviously, the described The embodiments are a part of the embodiments of the present invention, rather than all embodiments; the technical features designed in different embodiments of the present invention described below can be combined with each other as long as they do not constitute conflicts; based on the present invention All other embodiments obtained by persons of ordinary skill in the art without creative efforts, all belong to the scope of protection of the present utility model.

在本实用新型的描述中，需要说明的是，本实用新型所使用的所有术语(包括技术术语和科学术语)具有与本实用新型所属领域的普通技术人员通常所理解的含义相同的含义，不能理解为对本实用新型的限制；应进一步理解，本实用新型所使用的术语应被理解为具有与这些术语在本说明书的上下文和相关领域中的含义一致的含义，并且不应以理想化或过于正式的意义来理解，除本实用新型中明确如此定义之外。In the description of the present utility model, it should be noted that all terms (including technical terms and scientific terms) used in the present utility model have the same meanings as commonly understood by those of ordinary skill in the art to which the utility model belongs, and cannot It should be understood as a limitation of the present utility model; it should be further understood that the terms used in the present utility model should be understood as having meanings consistent with the meanings of these terms in the context of this description and in related fields, and should not be idealized or overly It should be understood in a formal sense, unless it is clearly defined in this utility model.

为了解决现有技术中采用单个系统RS485总线的闲置率过高，且单个系统进行频繁的存储和读写造成CPU使用率过高，进而容易导致系统卡顿甚至奔溃死机，双系统需更多布板空间，芯片之间无法使用片内通信，CPU运行时间占比较高，测试系统的运行可靠性无法保证的问题，本申请提供了一种基于异构多核处理器的高效采集网关。In order to solve the high idle rate of the RS485 bus in a single system in the prior art, and the frequent storage and reading and writing of a single system will cause the CPU usage to be too high, which will easily cause the system to freeze or even crash, the dual system needs more Board layout space, inability to use on-chip communication between chips, high proportion of CPU running time, and unguaranteed operational reliability of the test system. This application provides an efficient acquisition gateway based on heterogeneous multi-core processors.

请参考图1，图1为本申请实施例所提供的一种基于异构多核处理器的高效采集网关结构示意图，该网关包括：网口，用于与上位机通信连接；总线端口，用于与应用设备端通信连接；异构多核处理器，所述异构多核处理器分别与所述网口、总线端口电连接；数据存储单元，所述数据存储单元与异构多核处理器电连接。在网关内部中，网口与异构多核处理器通信连接，上位机通过网口与网关通信连接，直接控制异构多核处理器执行相应的工作。Please refer to FIG. 1. FIG. 1 is a structural schematic diagram of a high-efficiency acquisition gateway based on a heterogeneous multi-core processor provided by an embodiment of the present application. The gateway includes: a network port for communicating with an upper computer; a bus port for Communication connection with the application device; heterogeneous multi-core processor, the heterogeneous multi-core processor is electrically connected to the network port and the bus port; a data storage unit, the data storage unit is electrically connected to the heterogeneous multi-core processor. Inside the gateway, the network port communicates with the heterogeneous multi-core processor, and the host computer communicates with the gateway through the network port to directly control the heterogeneous multi-core processor to perform corresponding tasks.

本实施例中，异构多核处理器搭载有Linux系统和freeRTOS系统，freeRTOS系统与总线端口通信连接，以用于采集应用设备端的数据信息；Linux系统与freeRTOS系统通信连接，以用于接收freeRTOS系统的数据信息并将数据信息存储至数据存储单元；Linux系统还与网口通信连接以用于接收上位机的查询数据命令以及将数据存储单元内的数据信息上传至上位机。In this embodiment, the heterogeneous multi-core processor is equipped with a Linux system and a freeRTOS system, and the freeRTOS system communicates with the bus port to collect data information from the application device; the Linux system communicates with the freeRTOS system to receive the freeRTOS system and store the data information in the data storage unit; the Linux system is also connected to the network port for receiving the query data command of the host computer and uploading the data information in the data storage unit to the host computer.

通过上述两种系统分工协作的设置方式，能够有效利用两种系统的优势，使得Linux系统负责与上位机的通信和执行对数据的存储命令，freeRTOS系统负责发出轮询命令以对应用设备端的数据进行采集，从而降低了传统采用单个Linux系统及单个芯片的负担，进而有效降低CPU的使用率，提高通信效率。Through the setting method of the division of labor and cooperation of the above two systems, the advantages of the two systems can be effectively used, so that the Linux system is responsible for communicating with the host computer and executing data storage commands, and the freeRTOS system is responsible for issuing polling commands to collect data from the application device. Collecting, thereby reducing the traditional use of a single Linux system and the burden of a single chip, thereby effectively reducing the CPU usage and improving communication efficiency.

具体地，异构多核处理器的芯片优选为i.MX8芯片。在一些较佳的实施例中，芯片由4个Cotex-A53和1个Cotex-M4构成并分别搭载于不同的内核，其中Cotex-A53搭载Linux系统，Cotex-M4搭载freeRTOS系统。应当说明的是，本领域技术人员还可根据功能需求选用其他能够搭载Linux系统和freeRTOS系统的异构多核处理器的芯片类型及芯片个数，在此不做限定。Specifically, the chip of the heterogeneous multi-core processor is preferably an i.MX8 chip. In some preferred embodiments, the chip is composed of 4 Cotex-A53 and 1 Cotex-M4, which are respectively installed in different kernels, wherein the Cotex-A53 is equipped with a Linux system, and the Cotex-M4 is equipped with a freeRTOS system. It should be noted that those skilled in the art can also choose other heterogeneous multi-core processor chip types and chip numbers that can be equipped with Linux system and freeRTOS system according to functional requirements, which are not limited here.

进一步地，Linux系统拥有数据库、文件系统以及网络功能，这些功能特点使得Linux系统能用于接收上位机的命令，并进行相关任务执行，Linux系统自身也可以生成命令让下位系统执行，并且系统自身的数据库可以很好的接收相应的数据信息，并将其安全地保存。因此，在具体实施时，当上位机向采集网关发出查询数据命令时，由Linux系统通过与网口的通信来接收该命令，并执行从数据存储单元中获取相应的数据信息，通过TCP协议上传至上位机的工作。同时，Linux系统还与freeRTOS系统通信连接，以接收所述freeRTOS系统的数据信息并将数据信息存储至数据存储单元。Furthermore, the Linux system has database, file system, and network functions. These functional features enable the Linux system to receive commands from the upper computer and perform related tasks. The Linux system itself can also generate commands for the lower system to execute, and the system itself The database can receive the corresponding data information very well and store it safely. Therefore, in specific implementation, when the upper computer sends a query data command to the acquisition gateway, the Linux system receives the command through communication with the network port, and executes obtaining the corresponding data information from the data storage unit, uploading it through the TCP protocol The work of the upper computer. At the same time, the Linux system is also communicated with the freeRTOS system to receive the data information of the freeRTOS system and store the data information in the data storage unit.

进一步地，freeRTOS系统具有实时性、占用资源小以及支持抢占式调度、合作式调度和时间片调度的特点，这些特点使得freeRTOS系统可以实时迅速的采集下端应用设备端的数据并且支持多线程操作，同时在运行过程中能够占用较少的CPU内存。因此，在本实施例中，freeRTOS系统与Linux系统通信连接，能够接收Linux系统的命令，并且向Linux系统传递数据信息。同时freeRTOS系统还通过总线端口的通信向应用设备端发出轮询命令以采集应用设备端的数据信息。Furthermore, the freeRTOS system has the characteristics of real-time performance, small resource occupation, and support for preemptive scheduling, cooperative scheduling, and time slice scheduling. It can occupy less CPU memory during operation. Therefore, in this embodiment, the freeRTOS system communicates with the Linux system, can receive commands from the Linux system, and transmit data information to the Linux system. At the same time, the freeRTOS system also sends a polling command to the application device through the communication of the bus port to collect the data information of the application device.

较佳地，Linux系统和freeRTOS系统通过异构多核芯片内部共享的RPMsg接口进行通信连接，RPMsg接口采用开源组件。其工作原理为：当Linux系统需要接收freeRTOS系统采集的数据信息时，Linux系统通过RPMsg接口向freeRTOS系统下发查询数据命令，Linux系统驱动生成"/dev/ttyRPMSG30"节点，应用程序可以按RPMsg接口方法进行读写操作，从而与freeRTOS系统进行通信。freeRTOS系统执行相应操作，将数据信息通过RPMsg接口上传至Linux系统，Linux系统接收到数据后调用数据库接口，将其存储至数据存储单元。通过上述芯片内部共享的通信连接方式，使得片内通信占用CPU内存的运行时间大幅下降且通信更加高效可靠。Preferably, the Linux system and the freeRTOS system are connected through the RPMsg interface shared inside the heterogeneous multi-core chip, and the RPMsg interface uses open source components. Its working principle is: when the Linux system needs to receive the data information collected by the freeRTOS system, the Linux system sends a query data command to the freeRTOS system through the RPMsg interface, and the Linux system driver generates a "/dev/ttyRPMSG30" node, and the application program can press the RPMsg interface The method performs read and write operations to communicate with the freeRTOS system. The freeRTOS system performs corresponding operations, uploads the data information to the Linux system through the RPMsg interface, and the Linux system calls the database interface after receiving the data, and stores it in the data storage unit. Through the above-mentioned communication connection method shared inside the chip, the running time of the CPU memory occupied by the on-chip communication is greatly reduced and the communication is more efficient and reliable.

优选地，freeRTOS系统包含有轮询线程单元和收发线程单元，freeRTOS系统在收到Linux系统的数据查询命令后，轮询线程单元开始执行工作，对应用设备端的数据信息开始采集，轮询线程单元采集到的数据信息会缓存到ram中，等待Linux系统的读取命令；收发线程单元开始工作时，Linux系统通过RPMsg接口向freeRTOS系统下发数据信息读取命令，freeRTOS系统接收到命令后，通过RPMsg接口将ram中缓存的数据发出。其中收发线程单元具休眠模块，当freeRTOS系统将ram中缓存的数据发出后，休眠模块开始工作，收发线程单元随后进入线程休眠。Preferably, the freeRTOS system includes a polling thread unit and a sending and receiving thread unit. After the freeRTOS system receives the data query command from the Linux system, the polling thread unit starts to perform work, and the data information on the application device side starts to be collected, and the polling thread unit The collected data information will be cached in ram, waiting for the read command of the Linux system; when the sending and receiving thread unit starts to work, the Linux system sends the data information reading command to the freeRTOS system through the RPMsg interface, and the freeRTOS system receives the command, through The RPMsg interface sends out the data cached in ram. The sending and receiving thread unit has a dormancy module. When the freeRTOS system sends out the data cached in ram, the dormancy module starts to work, and the sending and receiving thread unit then enters the thread dormancy.

进一步地，收发线程单元的优先级高于轮询线程单元的优先级，且轮询线程单元没有休眠模块，这使得轮询线程会在收发线程执行完毕之后，持续对应用设备端的数据信息进行采集。不仅提高了CPU的利用率，还能对应用设备端进行实时的监控。通过上述设置方式，能够避免采用传统的Linux系统存在总线会有一定的空闲时间无法进行轮询而造成总线利用率低，通信效率下降的问题。此外，RPMsg接口在收发线程单元占用freeRTOS系统的时间极短，不会对轮询线程单元的时序造成影响。请参阅图2，图2为应用本实施例提供的高效采集网关在采集数据过程中测试RS485接口电平的时序图，由时序图可知，一个轮询线程单元工作的周期为4.46ms，而RS485总线的空闲时间仅159.48μs,轮询效率可以达到95％以上，趋近理论值。因此，这也进一步表明，采用本实施例提供的高效采集网关能够极大提高总线的利用率，进而提升数据的通信效率。Furthermore, the priority of the sending and receiving thread unit is higher than that of the polling thread unit, and the polling thread unit does not have a sleep module, which makes the polling thread continue to collect data information on the application device after the execution of the sending and receiving thread is completed. . It not only improves the CPU utilization rate, but also performs real-time monitoring on the application device side. Through the above-mentioned setting method, it is possible to avoid the problems of low bus utilization rate and decreased communication efficiency due to the fact that the bus will have a certain idle time and cannot be polled in the traditional Linux system. In addition, the RPMsg interface occupies a very short time in the freeRTOS system in the sending and receiving thread unit, and will not affect the timing of polling the thread unit. Please refer to Fig. 2, Fig. 2 is the sequence diagram of testing the RS485 interface level in the process of collecting data by applying the high-efficiency acquisition gateway provided by this embodiment, as can be seen from the sequence diagram, the cycle of a polling thread unit work is 4.46ms, and the RS485 The idle time of the bus is only 159.48μs, and the polling efficiency can reach more than 95%, approaching the theoretical value. Therefore, this further shows that the use of the high-efficiency acquisition gateway provided by this embodiment can greatly improve the utilization rate of the bus, thereby improving the communication efficiency of data.

优选地，网关通过总线端口与应用设备端通信连接，总线端口优选为uart串口，其适用于远距离通信，可以和RS485总线更好的适配。当然，总线端口还可根据实际工作需求选用其他例如usb、spi等端口，在此不做限制。Preferably, the gateway communicates with the application device through a bus port. The bus port is preferably a uart serial port, which is suitable for long-distance communication and can be better adapted to the RS485 bus. Of course, other ports such as usb, spi, etc. can also be selected for the bus port according to actual work requirements, and there is no limitation here.

作为一种优选方案，数据存储单元优选为eMMC存储器，其体积小、功耗低、容量大，适合网关等移动互联网设备等消费类电子设备的存储介质。当然，还可根据实际工作需求选用其他无实物形式的具有存储功能的电路，例如RAM或FIFO等，或选用具有实用形式的存储设备或芯片，例如Nandflash、Norflash、UFS、SD卡、U盘等。As a preferred solution, the data storage unit is preferably an eMMC memory, which has small volume, low power consumption, and large capacity, and is suitable for storage media of consumer electronic devices such as mobile Internet devices such as gateways. Of course, other non-physical circuits with storage functions, such as RAM or FIFO, can also be selected according to actual work requirements, or storage devices or chips with practical forms, such as Nandflash, Norflash, UFS, SD card, U disk, etc. .

请参阅图3，本申请实施例还提供一种高效采集网关系统，应用于网关轮询读取应用设备端的数据信息，该系统包括：上位机、如上任一实施例中的高效采集网关、至少一个应用设备端以及数据传输总线。上位机、应用设备端分别通过数据传输总线与高效采集网关通信连接。Please refer to Fig. 3, the embodiment of the present application also provides a high-efficiency collection gateway system, which is applied to the gateway to poll and read the data information of the application device. An application device side and data transfer bus. The upper computer and the application device are respectively connected to the high-efficiency acquisition gateway through the data transmission bus.

其中，上位机通过数据传输总线控制高效采集网关获取应用设备端的数据。当需要时，上位机发出查询数据命令以控制高效采集网关将应用设备端的数据上传至上位机。高效采集网关则通过数据传输总线采集应用设备端的数据，并将应用设备端的数据存储到网关的数据库中。Among them, the upper computer controls the high-efficiency acquisition gateway through the data transmission bus to obtain the data of the application device. When needed, the upper computer issues a query data command to control the efficient collection gateway to upload the data from the application device to the upper computer. The high-efficiency collection gateway collects the data of the application device through the data transmission bus, and stores the data of the application device in the database of the gateway.

应当说明的是，应用设备端可以是任何可以通过网关传输或收集数据的设备，在本实施例中为工业应用设备终端，其中设备终端至少有一个。It should be noted that the application device end can be any device that can transmit or collect data through the gateway, in this embodiment, it is an industrial application device terminal, and there is at least one device terminal.

其中，数据传输总线优选为RS485总线，其具有多点双向通信，可以连接多个应用终端设备，抗干扰能力强、传输距离大以及传输速度快等优点。Among them, the data transmission bus is preferably RS485 bus, which has the advantages of multi-point two-way communication, can connect multiple application terminal devices, strong anti-interference ability, large transmission distance and fast transmission speed.

综上所述，与现有技术相比，本实用新型提供的基于异构多核处理器的高效采集网关及系统，通过异构多核处理器的运用，发挥Linux和freeRTOS两种操作系统的优点，既能使用Linux系统的数据库、网络等复杂功能，又能通过freeRTOS系统的实时性实现RS485总线的高效利用，同时减轻了Linux系统的CPU使用率，降低了传输总线闲置率，提高了通信效率；此外，芯片内部共享的通信连接方式，使得片内通信占用CPU内存的时间大幅下降且通信过程高效可靠。In summary, compared with the prior art, the utility model provides an efficient collection gateway and system based on heterogeneous multi-core processors, through the use of heterogeneous multi-core processors, the advantages of Linux and freeRTOS two operating systems are brought into play, It can not only use complex functions such as the database and network of the Linux system, but also realize the efficient utilization of the RS485 bus through the real-time performance of the freeRTOS system, and at the same time reduce the CPU usage of the Linux system, reduce the idle rate of the transmission bus, and improve communication efficiency; In addition, the shared communication connection mode inside the chip makes the CPU memory time occupied by the on-chip communication greatly reduced and the communication process is efficient and reliable.

另外，本领域技术人员应当理解，尽管现有技术中存在许多问题，但是，本实用新型的每个实施例或技术方案可以仅在一个或几个方面进行改进，而不必同时解决现有技术中或者背景技术中列出的全部技术问题。本领域技术人员应当理解，对于一个权利要求中没有提到的内容不应当作为对于该权利要求的限制。In addition, those skilled in the art should understand that although there are many problems in the prior art, each embodiment or technical solution of the utility model can only be improved in one or several aspects, and it is not necessary to solve the problems in the prior art at the same time. Or all the technical problems listed in the background technology. It should be understood by those skilled in the art that anything that is not mentioned in a claim should not be taken as a limitation on the claim.

尽管本文中较多的使用了诸如异构多核处理器、数据存储单元、总线端口、应用设备端、轮询线程单元、收发线程单元以及休眠模块等术语，但并不排除使用其它术语的可能性。使用这些术语仅仅是为了更方便地描述和解释本实用新型的本质；把它们解释成任何一种附加的限制都是与本实用新型精神相违背的；本实用新型实施例的说明书和权利要求书及上述附图中的术语“第一”、“第二”、等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。Although terms such as heterogeneous multi-core processor, data storage unit, bus port, application device side, polling thread unit, sending and receiving thread unit, and sleep module are often used in this article, the possibility of using other terms is not excluded . These terms are only used to describe and explain the essence of the utility model more conveniently; they are interpreted as any kind of additional restriction and all go against the spirit of the utility model; Description and claims of the utility model embodiment The terms "first", "second", etc., if present, in the above-mentioned figures are used to distinguish similar objects and not necessarily to describe a specific order or sequence.

最后应说明的是：以上各实施例仅用以说明本实用新型的技术方案，而非对其限制；尽管参照前述各实施例对本实用新型进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本实用新型各实施例技术方案的范围。Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present utility model, and are not intended to limit it; although the present utility model has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand : It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements to some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions depart from the various embodiments of the present invention Scope of technical solutions.

Claims (10)

Translated fromChinese

1.一种基于异构多核处理器的高效采集网关，其特征在于：包括1. A high-efficiency acquisition gateway based on heterogeneous multi-core processors, characterized in that: comprising网口，用于与上位机通信连接；Network port, used to communicate with the host computer;总线端口，用于与应用设备端通信连接；The bus port is used to communicate with the application device;异构多核处理器，所述异构多核处理器分别与所述网口、所述总线端口电连接；a heterogeneous multi-core processor, the heterogeneous multi-core processor is electrically connected to the network port and the bus port respectively;数据存储单元，所述数据存储单元与所述异构多核处理器电连接；a data storage unit, the data storage unit is electrically connected to the heterogeneous multi-core processor;其中，所述异构多核处理器搭载Linux系统和freeRTOS系统；所述freeRTOS系统与所述总线端口通信连接，以用于采集所述应用设备端的数据信息；所述Linux系统与所述freeRTOS系统通信连接，以用于接收所述freeRTOS系统的数据信息并将数据信息存储至所述数据存储单元；所述Linux系统还与所述网口通信连接以用于接收所述上位机的查询数据命令以及将所述数据存储单元内的数据信息上传至所述上位机。Wherein, the heterogeneous multi-core processor is equipped with a Linux system and a freeRTOS system; the freeRTOS system communicates with the bus port for collecting data information on the application device side; the Linux system communicates with the freeRTOS system Connected, for receiving the data information of the freeRTOS system and storing the data information to the data storage unit; the Linux system is also connected with the network port for receiving the query data command of the host computer and Upload the data information in the data storage unit to the host computer.2.根据权利要求1所述的基于异构多核处理器的高效采集网关，其特征在于：所述freeRTOS系统包括轮询线程单元以及优先级高于所述轮询线程单元的收发线程单元，所述轮询线程单元用于向所述应用设备端下发轮询命令并采集所述应用设备端的数据信息；所述收发线程单元用于接收所述Linux系统下发的命令并向所述Linux系统发送采集到的数据信息。2. the efficient collection gateway based on heterogeneous multi-core processor according to claim 1, is characterized in that: described freeRTOS system comprises polling thread unit and priority is higher than the sending and receiving thread unit of described polling thread unit, so The polling thread unit is used to issue a polling command to the application device and collect the data information of the application device; the sending and receiving thread unit is used to receive the command issued by the Linux system and send the command to the Linux system Send the collected data information.3.根据权利要求2所述的基于异构多核处理器的高效采集网关，其特征在于：所述收发线程单元具有休眠模块，所述休眠模块用于在向所述Linux系统发送采集到的数据信息后，控制所述收发线程单元进入线程休眠。3. the efficient acquisition gateway based on heterogeneous multi-core processors according to claim 2, characterized in that: the transceiver thread unit has a dormancy module, and the dormancy module is used to send the collected data to the Linux system After receiving the message, control the sending and receiving thread unit to enter thread dormancy.4.根据权利要求1所述的基于异构多核处理器的高效采集网关，其特征在于：所述Linux系统和所述freeRTOS系统通过RPMsg接口通信连接。4. The efficient collection gateway based on heterogeneous multi-core processors according to claim 1, characterized in that: the Linux system and the freeRTOS system are connected through the RPMsg interface.5.根据权利要求1所述的基于异构多核处理器的高效采集网关，其特征在于：所述异构多核处理器包含异构多核芯片，所述异构多核芯片包括Cotex-A53和Cotex-M4，所述Cotex-A53搭载所述Linux系统，所述Cotex-M4搭载所述freeRTOS系统。5. The efficient collection gateway based on heterogeneous multi-core processor according to claim 1, characterized in that: said heterogeneous multi-core processor comprises a heterogeneous multi-core chip, and said heterogeneous multi-core chip comprises Cotex-A53 and Cotex- M4, the Cotex-A53 is equipped with the Linux system, and the Cotex-M4 is equipped with the freeRTOS system.6.根据权利要求5所述的基于异构多核处理器的高效采集网关，其特征在于：所述Cotex-A53有4个，所述Cotex-M4有1个。6. The high-efficiency acquisition gateway based on heterogeneous multi-core processors according to claim 5, wherein there are four Cotex-A53s and one Cotex-M4.7.根据权利要求1所述的基于异构多核处理器的高效采集网关，其特征在于：所述总线端口设置为uart串口。7. The efficient collection gateway based on heterogeneous multi-core processors according to claim 1, characterized in that: the bus port is set to a uart serial port.8.根据权利要求1所述的基于异构多核处理器的高效采集网关，其特征在于：所述数据存储单元设置为eMMC存储器。8. The high-efficiency acquisition gateway based on heterogeneous multi-core processors according to claim 1, characterized in that: the data storage unit is set as an eMMC memory.9.一种高效采集网关系统，其特征在于：采用如权利要求1-8任一项所述的基于异构多核处理器的高效采集网关；还包括上位机、至少一个应用设备端以及数据传输总线，所述上位机、应用设备端分别通过所述数据传输总线与所述高效采集网关通信连接。9. A high-efficiency collection gateway system, characterized in that: adopt the high-efficiency collection gateway based on heterogeneous multi-core processors as claimed in any one of claims 1-8; also include host computer, at least one application device end and data transmission bus, the host computer and the application device are respectively connected to the high-efficiency collection gateway through the data transmission bus.10.根据权利要求9所述的高效采集网关系统，其特征在于：所述数据传输总线设置为RS485总线。10. The high-efficiency acquisition gateway system according to claim 9, characterized in that: the data transmission bus is configured as an RS485 bus.

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