CN215266301U - Oxide thin film transistor array substrate - Google Patents

Abstract

The utility model relates to the technical field of array substrates, in particular to an oxide thin film transistor array substrate, which comprises a glass substrate and a buffer layer arranged on one side surface of the glass substrate, wherein a capacitor area on one side surface of the buffer layer far away from the glass substrate is provided with at least one groove, the groove is filled with a first electrode layer, a first insulating layer, a second electrode layer, a first etching barrier layer, a third electrode layer and a first passivation layer are sequentially laminated and covered on one side surface of the first electrode layer far away from the buffer layer, the first electrode layer, the first insulating layer and the second electrode layer form a capacitor, the second electrode layer, the first etching barrier layer and the third electrode layer form a capacitor to form two capacitors connected in parallel, therefore, the capacitance capacity is further increased, the occupied area of the capacitor can be reduced, and the PPI panel and the frame size of the panel are improved.

Description

Oxide thin film transistor array substrate

Technical Field

The utility model relates to an array substrate technical field, in particular to oxide thin film transistor array substrate.

Background

With the development of active matrix organic light emitting diode displays (AMOLEDs) and high performance Active Matrix Liquid Crystal Displays (AMLCDs), in order to obtain high resolution and high frame rate displays, how to design and fabricate high performance and small size array substrate structures is an increasingly challenging research topic.

IGZO is an amorphous oxide containing indium, gallium and zinc, the carrier mobility is 20-30 times of that of amorphous silicon, the charge and discharge rate of a TFT (Thin Film Transistor, english is called a Thin Film Transistor) to a pixel electrode can be greatly increased, the response speed of a pixel is increased, the panel refresh rate is higher, and an ultrahigh-resolution display panel can be realized. Meanwhile, the existing amorphous silicon production line can be compatible with the IGZO process only by slightly changing, so that the cost is more competitive than that of low-temperature polycrystalline silicon (LTPS).

The oxide semiconductor mobility (10-30cm2/V.s) can meet the driving requirement of the AMOLED display array substrate, the IGZO TFT device has a better Ioff compared with a low-temperature polysilicon TFT, the pixel TFT can inhibit the electric leakage problem only by a single grid electrode, the miniaturization of the TFT device is facilitated, and the manufacturing of the ultra-high resolution TFT substrate is realized. Therefore, the high-resolution OLED display matched with the IGZO TFT drive circuit has good market prospect and is a research and development hotspot of main panel manufacturing factories at home and abroad at present.

The GOA technology (GOA: Gate Driver IC on Array) is a new type of panel development in recent years, which directly etches the IC driving the Gate signal on the panel, and saves the cost of the Gate Driver IC and the process of binding the IC on the panel, and more importantly, because the Gate Driver IC and the display panel are integrated, the product is thinner, the resolution is higher, and the stability and the vibration resistance are better. At present, the GOA technology has become the mainstream of the mobile terminal industry, and smart phones almost use the liquid crystal panel.

In order to make the driving circuit have a better voltage stabilizing effect in the array substrate, a capacitor with a larger capacity is usually required to be arranged, which causes the occupied area of the driving circuit to be larger, and the frame size and the pixel size of the display panel cannot be further reduced.

SUMMERY OF THE UTILITY MODEL

The utility model discloses the technical problem that will solve is: provided is an oxide thin film transistor array substrate capable of improving capacitance capacity.

In order to solve the technical problem, the utility model discloses a technical scheme be:

an oxide thin film transistor array substrate comprises a glass substrate and a buffer layer arranged on one side face of the glass substrate, wherein at least one groove is formed in a capacitor area on one side face, far away from the glass substrate, of the buffer layer, a first electrode layer is filled in the groove, and a first insulating layer, a second electrode layer, a first etching barrier layer, a third electrode layer and a first passivation layer are sequentially stacked and covered on one side face, far away from the buffer layer, of the first electrode layer;

a first active layer, a grid electrode insulating layer, a first transparent conducting layer, a grid electrode metal layer, a second etching barrier layer, a second transparent conducting layer, a source drain electrode metal layer and a second passivation layer are sequentially laminated and covered on a TFT region on one side face, away from the glass substrate, of the buffer layer, a first through hole is formed in the second etching barrier layer, the second transparent conducting layer is filled in the first through hole, a second through hole is formed in the second transparent conducting layer, a third through hole is formed in the source drain electrode metal layer, the third through hole and the second through hole are oppositely arranged and communicated, and the second passivation layer is filled in the second through hole and the third through hole;

the material of the first electrode layer is the same as that of the first active layer;

the material of the second electrode layer is the same as that of the first transparent conducting layer;

the material of the third electrode layer is the same as that of the second transparent conducting layer.

The beneficial effects of the utility model reside in that:

the capacitor comprises a buffer layer, a glass substrate, a capacitor body and a first electrode layer, wherein at least one groove is formed in a capacitor area on one side face, far away from the glass substrate, of the buffer layer, the groove is filled with the first electrode layer, a first insulating layer, a second electrode layer, a first etching barrier layer, a third electrode layer and a first passivation layer are sequentially overlapped on one side face, far away from the buffer layer, of the first electrode layer, the second electrode layer, the third electrode layer and the first passivation layer are respectively used as electrode layers of the capacitor, the first electrode layer, the first insulating layer and the second electrode layer form a capacitor, and the second electrode layer, the first etching barrier layer and the third electrode layer form a capacitor to form two capacitors connected in parallel, so that the capacity of the capacitor is further increased; the TFT region on one side of the buffer layer far away from the glass substrate is sequentially laminated and covered with a first active layer, a grid electrode insulating layer, a first transparent conducting layer, a grid electrode metal layer, a second etching barrier layer, a second transparent conducting layer, a source drain metal layer and a second passivation layer, the material of the first electrode layer is the same as that of the first active layer, the material of the second electrode layer is the same as that of the first transparent conducting layer, and the material of the third electrode layer is the same as that of the second transparent conducting layer, so that the capacitance can be further improved, the occupied area of a capacitor can be reduced, and the TFT LCD panel has the advantages of improving PPI (Pixels on diagonal lines of every Inch) of a panel and reducing the size of a panel frame.

Drawings

Fig. 1 is a schematic structural diagram of an oxide thin film transistor array substrate according to the present invention;

description of reference numerals:

1. a glass substrate;

2. a buffer layer;

3. a capacitive region; 31. a first electrode layer; 32. a first insulating layer; 33. a second electrode layer; 34. a first etch stop layer; 35. a third electrode layer; 36. a first passivation layer;

4. a TFT region; 41. a first active layer; 42. a gate insulating layer; 43. a first transparent conductive layer; 44. a gate metal layer; 45. a second etch stop layer; 46. a second transparent conductive layer; 47. a source drain metal layer; 48. a second passivation layer.

Detailed Description

In order to explain the technical content, the objects and the effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.

Referring to fig. 1, the present invention provides a technical solution:

an oxide thin film transistor array substrate comprises a glass substrate and a buffer layer arranged on one side face of the glass substrate, wherein at least one groove is formed in a capacitor area on one side face, far away from the glass substrate, of the buffer layer, a first electrode layer is filled in the groove, and a first insulating layer, a second electrode layer, a first etching barrier layer, a third electrode layer and a first passivation layer are sequentially stacked and covered on one side face, far away from the buffer layer, of the first electrode layer;

a first active layer, a grid electrode insulating layer, a first transparent conducting layer, a grid electrode metal layer, a second etching barrier layer, a second transparent conducting layer, a source drain electrode metal layer and a second passivation layer are sequentially laminated and covered on a TFT region on one side face, away from the glass substrate, of the buffer layer, a first through hole is formed in the second etching barrier layer, the second transparent conducting layer is filled in the first through hole, a second through hole is formed in the second transparent conducting layer, a third through hole is formed in the source drain electrode metal layer, the third through hole and the second through hole are oppositely arranged and communicated, and the second passivation layer is filled in the second through hole and the third through hole;

the material of the first electrode layer is the same as that of the first active layer;

the material of the second electrode layer is the same as that of the first transparent conducting layer;

the material of the third electrode layer is the same as that of the second transparent conducting layer.

From the above description, the beneficial effects of the present invention are:

the capacitor comprises a buffer layer, a glass substrate, a capacitor body and a first electrode layer, wherein at least one groove is formed in a capacitor area on one side face, far away from the glass substrate, of the buffer layer, the groove is filled with the first electrode layer, a first insulating layer, a second electrode layer, a first etching barrier layer, a third electrode layer and a first passivation layer are sequentially overlapped on one side face, far away from the buffer layer, of the first electrode layer, the second electrode layer, the third electrode layer and the first passivation layer are respectively used as electrode layers of the capacitor, the first electrode layer, the first insulating layer and the second electrode layer form a capacitor, and the second electrode layer, the first etching barrier layer and the third electrode layer form a capacitor to form two capacitors connected in parallel, so that the capacity of the capacitor is further increased; the TFT area of one side of the buffer layer far away from the glass substrate is sequentially laminated and covered with a first active layer, a grid electrode insulating layer, a first transparent conducting layer, a grid electrode metal layer, a second etching barrier layer, a second transparent conducting layer, a source drain electrode metal layer and a second passivation layer, the material of the first electrode layer is the same as that of the first active layer, the material of the second electrode layer is the same as that of the first transparent conducting layer, and the material of the third electrode layer is the same as that of the second transparent conducting layer, so that the capacitance capacity can be further improved, meanwhile, the occupied area of the capacitor can be reduced, and the PPI of the panel is improved, and the frame size of the panel is reduced.

Furthermore, the first electrode layer is made of indium tin oxide, and the thickness range of the first electrode layer is

As can be seen from the above description, the first electrode layer is made of ITO and has a thickness in the range of

The capacitance capacity can be further improved.

Further, the first electrode layer in the groove is in contact with the glass substrate.

Further, the vertical cross section of the groove is square.

Furthermore, the number of the first via holes is two, and the second via hole and the third via hole are both located between the two first via holes.

Referring to fig. 1, a first embodiment of the present invention is:

an oxide thin film transistor array substrate comprises a glass substrate 1 and abuffer layer 2 arranged on one side face of the glass substrate 1, wherein at least one groove is formed in a capacitor area 3 on one side face, far away from the glass substrate 1, of thebuffer layer 2, afirst electrode layer 31 is filled in the groove, and afirst insulating layer 32, asecond electrode layer 33, a firstetching barrier layer 34, athird electrode layer 35 and afirst passivation layer 36 are sequentially stacked and covered on one side face, far away from thebuffer layer 2, of thefirst electrode layer 31;

a firstactive layer 41, agate insulating layer 42, a first transparent conductinglayer 43, agate metal layer 44, a secondetching barrier layer 45, a secondtransparent conducting layer 46, a sourcedrain metal layer 47 and asecond passivation layer 48 are sequentially laminated and covered on the TFT region 4 on one side surface of thebuffer layer 2, which is far away from the glass substrate 1, wherein a first through hole is formed in the secondetching barrier layer 45, the second transparent conductinglayer 46 is filled in the first through hole, a second through hole is formed in the second transparent conductinglayer 46, a third through hole is formed in the sourcedrain metal layer 47, the third through hole and the second through hole are oppositely arranged and communicated, and thesecond passivation layer 48 is filled in the second through hole and the third through hole;

the material of thefirst electrode layer 31 is the same as that of the firstactive layer 41; the thickness of the firstactive layer 41 is in the range of

Preferably, it is

The material of thesecond electrode layer 33 is the same as that of the first transparentconductive layer 43; the thickness range of the first transparentconductive layer 43 is

Preferably, it is

The material of thethird electrode layer 35 is the same as that of the second transparentconductive layer 46; the second transparentconductive layer 46 has a thickness in the range of

Preferably, it is

The thickness range of thefirst electrode layer 31 is

Preferably, it is

Thefirst electrode layer 31 is made of indium tin oxide, and the thickness of thefirst electrode layer 31 is within a range

Thefirst electrode layer 31 in the recess is in contact with the glass substrate 1.

The vertical cross-sectional shape of the groove is square or semi-cylindrical.

The number of the first via holes is two, and the second via holes and the third via holes are located between the two first via holes.

The thickness range of thebuffer layer 2 is 0.2-3 μm, preferably 2 μm; thebuffer layer 2 can be made of organic photosensitive materials, PI, SiOx, SiNx, titanium oxide and the like;

the thickness of thegate metal layer 44 is in the range of

Preferably, it is

Thegate metal layer 44 may be made of one or more of aluminum, molybdenum, titanium, nickel, copper, silver, chromium and other metals with good conductivity, and alloys;

the thickness of the first insulatinglayer 32 is in the range of

Preferably, it is

The thickness range of the gate insulating layer 42Is composed of

Preferably, it is

The first insulatinglayer 32 and thegate insulating layer 42 are made of the same material, and may be made of SiOx, SiNx, titanium oxide, aluminum oxide, or the like;

the thickness range of thesecond electrode layer 33 is

Preferably, it is

Thesecond electrode layer 33 and the first transparentconductive layer 43 are made of the same material, and may be made of metal oxide such as IGZO, IZO, IGZTO, etc.;

the thickness range of thethird electrode layer 35 is

Preferably, it is

Thethird electrode layer 35 and the second transparentconductive layer 46 are made of the same material, and indium tin oxide can be used;

the thickness of the firstetch stop layer 34 ranges from

Preferably, it is

The thickness of the secondetch stop layer 45 ranges from

Preferably, it is

The firstetching barrier layer 34 and the secondetching barrier layer 45 are made of the same material, and S can be selectediOx, SiNx, titanium oxide, aluminum oxide, and the like;

the thickness range of the source/drain metal layer 47 is

Preferably, it is

The source/drain metal layer 47 may be made of one or more metals with good conductivity, such as aluminum, molybdenum, titanium, nickel, copper, silver, chromium, and alloys;

the thickness of thefirst passivation layer 36 ranges from

Preferably, it is

The thickness of thesecond passivation layer 48 ranges from

Preferably, it is

Thefirst passivation layer 36 and thesecond passivation layer 48 are made of the same material, and may be made of SiOx, SiNx, titanium oxide, aluminum oxide, or the like;

the second transparentconductive layer 46 is made of indium tin oxide, and the source layer and the source drainmetal layer 47 are connected in a bridging manner by using the indium tin oxide, so that ohmic contact resistance can be reduced, and the electrical performance of the TFT can be improved;

in the actual process, thefirst electrode layer 31 and the firstactive layer 41 are the same film layer distributed in different regions, and are formed simultaneously during the evaporation process;

the first insulatinglayer 32 and thegate insulating layer 42 are the same film layer distributed in different areas, and are formed simultaneously during the evaporation process;

thesecond electrode layer 33 and the first transparentconductive layer 43 are the same film layer distributed in different areas, and are formed simultaneously during the evaporation process;

the firstetching barrier layer 34 and the secondetching barrier layer 45 are the same film layer distributed in different areas, and are formed simultaneously during the evaporation process;

thethird electrode layer 35 and the second transparentconductive layer 46 are the same film layer distributed in different areas, and are formed simultaneously during the evaporation process;

thefirst passivation layer 36 and thesecond passivation layer 48 are the same film layer distributed in different regions, and are formed simultaneously during the evaporation process;

according to the array substrate with the high-capacity capacitor structure, under the condition that the capacity is kept equal, the actually occupied area of the three-dimensional grid-shaped capacitor is smaller than that of a flat capacitor, and the theoretical capacitor area can be further reduced by 50%.

To sum up, the utility model provides a pair of oxide thin film transistor array substrate, through the buffer layer keep away from the regional recess of seting up at least one of electric capacity of a side of glass substrate, it has first electrode layer to fill in the recess, first electrode layer keeps away from and is overlapped in proper order on a side of buffer layer and is covered with first insulating layer, the second electrode layer, first etching barrier layer, third electrode layer and first passivation layer, first electrode layer, second electrode layer and third electrode layer are regarded as the electrode layer of electric capacity respectively, first electrode layer, first insulating layer and second electrode layer constitute a electric capacity, second electrode layer, first etching barrier layer and third electrode layer constitute a electric capacity, in order to form two electric capacities that connect in parallel, thereby further increased the electric capacity; the TFT area of one side of the buffer layer far away from the glass substrate is sequentially laminated and covered with a first active layer, a grid electrode insulating layer, a first transparent conducting layer, a grid electrode metal layer, a second etching barrier layer, a second transparent conducting layer, a source drain electrode metal layer and a second passivation layer, the material of the first electrode layer is the same as that of the first active layer, the material of the second electrode layer is the same as that of the first transparent conducting layer, and the material of the third electrode layer is the same as that of the second transparent conducting layer, so that the capacitance capacity can be further improved, meanwhile, the occupied area of the capacitor can be reduced, and the PPI of the panel is improved, and the frame size of the panel is reduced.

The above mentioned is only the embodiment of the present invention, and not the limitation of the patent scope of the present invention, all the equivalent transformations made by the contents of the specification and the drawings, or the direct or indirect application in the related technical field, are included in the patent protection scope of the present invention.

Claims (5)

1. The oxide thin film transistor array substrate is characterized by comprising a glass substrate and a buffer layer arranged on one side face of the glass substrate, wherein at least one groove is formed in a capacitance area on one side face, away from the glass substrate, of the buffer layer, a first electrode layer is filled in the groove, and a first insulating layer, a second electrode layer, a first etching barrier layer, a third electrode layer and a first passivation layer are sequentially laminated and covered on one side face, away from the buffer layer, of the first electrode layer;

a first active layer, a grid electrode insulating layer, a first transparent conducting layer, a grid electrode metal layer, a second etching barrier layer, a second transparent conducting layer, a source drain electrode metal layer and a second passivation layer are sequentially laminated and covered on a TFT region on one side face, away from the glass substrate, of the buffer layer, a first through hole is formed in the second etching barrier layer, the second transparent conducting layer is filled in the first through hole, a second through hole is formed in the second transparent conducting layer, a third through hole is formed in the source drain electrode metal layer, the third through hole and the second through hole are oppositely arranged and communicated, and the second passivation layer is filled in the second through hole and the third through hole;

the material of the first electrode layer is the same as that of the first active layer;

the material of the second electrode layer is the same as that of the first transparent conducting layer;

the material of the third electrode layer is the same as that of the second transparent conducting layer.

2. The oxide thin film transistor array substrate of claim 1, wherein the first electrode is formed of a metal oxide materialThe electrode layer is made of indium tin oxide, and the thickness range of the first electrode layer is

。

3. The oxide thin film transistor array substrate of claim 1, wherein the first electrode layer in the groove is in contact with a glass substrate.

4. The oxide thin film transistor array substrate of claim 1, wherein the vertical cross-sectional shape of the groove is square.

5. The oxide thin film transistor array substrate of claim 1, wherein the number of the first vias is two, and the second and third vias are located between the two first vias.

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