CN214313183U - Frameless ultrathin front lead-out TVS chip packaging structure - Google Patents

Abstract

The utility model provides a TVS chip packaging structure is drawn forth to ultra-thin front of frameless, including chip, lead wire, conductive adhesive layer, frame and packaging body, the chip is horizontal structure, and its extraction electrode is located the front of chip, and the lead wire is equipped with a pair ofly to bond respectively on the extraction electrode of chip, and the inner of conductive adhesive layer bonds in the copper line end, and the frame is equipped with a pair ofly, and each frame bonds with the outer end of conductive adhesive layer, and the packaging body wraps up in chip, lead wire, conductive adhesive layer and frame outside, and the frame end exposes from the packaging body; the lead wire is used as a copper wire and is bonded on the lead-out electrode of the chip through thermoacoustic welding; the conductive adhesive layer is formed by conductive silver adhesive; the packaging body is molded by epoxy resin molding compound. The chip packaged by the packaging structure is not a longitudinal structure any more, but a transverse structure, and the electric connection is on the front side of the wafer, so that the packaging structure has the effects of simplifying the process flow, improving the production effect and reducing the cost, and can exert the performance of the chip to the maximum.

Description

Frameless ultrathin front lead-out TVS chip packaging structure

Technical Field

The utility model relates to a transient voltage suppressor especially relates to a TVS chip packaging structure is drawn forth to ultra-thin front of frameless frame.

Background

The package is to lead the circuit pins on the silicon chip to the external joints by wires for connection with other devices, which not only plays the roles of mounting, fixing, sealing, protecting the chip and enhancing the electric heating performance, but also is connected to the pins of the package shell by wires through the joints on the chip, and the pins are connected with other devices by wires on the printed circuit board, thereby realizing the connection of the internal chip and the external circuit. The chip of present encapsulation Transient Voltage Suppressor (TVS) product is vertical structure from top to bottom, need carry out electric connection simultaneously to the front and the back of chip, and packaging technology is comparatively complicated, and for example the attenuate back of the body gold is the link that a technology is more difficult to control, causes the piece easily and the back of the body gold drops, and the routing needs professional routing equipment, because the routing requires the precision very high, so equipment is very expensive, and overall efficiency is also not high for low in production efficiency, with high costs. Therefore, it is necessary to optimize the structure of the TVS chip to overcome the above-mentioned drawbacks.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a TVS chip package structure is drawn forth to ultra-thin front of frameless frame to reduction in production cost improves production efficiency.

The utility model discloses a solve the technical scheme that its technical problem adopted and be:

a frameless ultra-thin front lead-out TVS chip packaging structure comprises:

the chip is of a transverse structure, and the extraction electrode of the chip is positioned on the front surface of the chip;

a pair of leads bonded to the lead electrodes of the chip, respectively;

the inner end of the conductive adhesive layer is bonded to the tail end of the copper wire;

the frames are provided with a pair, and each frame is bonded with the outer end of the conductive adhesive layer;

and the packaging body is wrapped outside the chip, the lead, the conductive adhesive layer and the frame, and the tail end of the frame is exposed out of the packaging body.

Specifically, the lead wire is a copper wire and bonded to the lead-out electrode of the chip by thermosonic bonding.

Furthermore, the conductive adhesive layer is formed by conductive silver adhesive.

Furthermore, the packaging body is molded by adopting epoxy resin molding compound.

The utility model has the advantages that:

the chip packaged by the packaging structure is not a longitudinal structure any more, but a transverse structure, and the electric connection is on the front side of the wafer, so that the packaging structure has the effects of simplifying the process flow, improving the production effect and reducing the cost, and can exert the performance of the chip to the maximum.

Drawings

Fig. 1 is a schematic structural diagram of a frameless ultra-thin front led TVS chip package structure provided by the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the drawings in the embodiments of the present invention are combined below to clearly and completely describe the technical solutions in the embodiments of the present invention. It is to be understood that the embodiments described are only some of the embodiments of the present invention, and not all of them. The components of embodiments of the present invention, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

As shown in fig. 1, the utility model provides a TVS chip package structure is drawn forth to ultra-thin front of frameless frame includeschip 100,lead wire 200, conductiveadhesive layer 300,frame 400 andpackaging body 500, the chip is horizontal structure, it draws forth the positive that the electrode is located the chip, the lead wire is equipped with a pair ofly, and bond respectively on the electrode of drawing forth of chip, conductive adhesive layer's the inner bonds in copper line end, the frame is equipped with a pair ofly, each frame bonds with conductive adhesive layer's outer end, the packaging body parcel is in the chip, the lead wire, conductive adhesive layer and frame are outside, the frame is terminal to expose from the packaging body. In this embodiment, the lead is a copper wire and is bonded to the lead electrode of the chip by thermosonic bonding. In this embodiment, the conductive adhesive layer is formed by conductive silver adhesive. In this embodiment, the package is molded by using an epoxy resin molding compound.

At present, the main of influence encapsulation efficiency and cost is on the attenuate back of the body gold of chip, routing and test package, and the optimal design has been done at attenuate back of the body gold and routing process to this scheme, does not need to carry out attenuate back of the body gold to the wafer earlier stage, and the attenuate back of the body gold is the link that a technology is more difficult to control, causes the piece easily and the back of the body gold drops, and the routing needs the routing equipment of specialty, because the routing requires the precision very high, so equipment is very expensive, and overall efficiency is also not high. The scheme adopts the process of a wafer factory, thick sheet processing is carried out, a metal layer with the thickness of 20-30 microns is directly subjected to photoetching expansion on the thick sheet, then plastic packaging is carried out, a grinding sheet is carried out, a second electroplating connection layer is carried out, and a bonding pad is electroplated for the third time; and finally, cutting the test package to finish packaging. The method specifically comprises the following steps: wafer metal expanding layer → cutting → first plastic package → grinding plate → metal layer for electroplating → second plastic package → grinding plate → pin layer for electroplating → cutting → silk screen → test package.

By adopting the method, the production efficiency can be improved, the period for normally thinning the back gold is about 2 weeks, routing is predicted to be 1 week, the time is predicted to be saved by 2 weeks, the packaging period of the whole product is optimized to 4 weeks in 6 weeks, and the effect is better and obvious when the productivity is short; the cost is reduced, and the product cost is expected to be reduced by 20% by the technical process of thinning the back gold and routing which is cancelled by the scheme; the yield is improved, the thinning back gold and the upper core routing are production links which are easy to scrap, the process precision of the wafer is better, and the yield can reach more than 99.5%.

In the description of the present invention, it should be noted that the terms "upper", "lower", "inner", "outer", "left", "right", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, or orientations or positional relationships that are conventionally placed when the products of the present invention are used, or orientations or positional relationships that are conventionally understood by those skilled in the art, and are only for convenience of description of the present invention and simplification of description, but do not indicate or imply that the designated devices or elements must have a specific orientation, be configured and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance. In the description of the present invention, it should be further noted that, unless explicitly stated or limited otherwise, the terms "disposed" and "connected" are to be interpreted broadly, and for example, "connected" may be a fixed connection, a detachable connection, or an integral connection; can be mechanically or electrically connected; the connection may be direct or indirect via an intermediate medium, and may be a communication between the two elements. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

Claims (4)

1. The utility model provides a TVS chip package structure is drawn forth to ultra-thin front of frameless, its characterized in that includes:

the chip is of a transverse structure, and the extraction electrode of the chip is positioned on the front surface of the chip;

a pair of leads bonded to the lead electrodes of the chip, respectively;

the inner end of the conductive adhesive layer is bonded to the tail end of the copper wire;

the frames are provided with a pair, and each frame is bonded with the outer end of the conductive adhesive layer;

and the packaging body is wrapped outside the chip, the lead, the conductive adhesive layer and the frame, and the tail end of the frame is exposed out of the packaging body.

2. The frameless ultra-thin front-lead TVS chip package structure of claim 1, wherein:

the lead wire is used as a copper wire and is bonded on the lead-out electrode of the chip through thermoacoustic welding.

3. The frameless ultra-thin front-lead TVS chip package structure of claim 1, wherein:

the conductive adhesive layer is formed by conductive silver adhesive.

4. The frameless ultra-thin front-lead TVS chip package structure of claim 1, wherein:

the packaging body is molded by epoxy resin molding compound.

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