CN213276628U - CPU network interface adaptability test board card and test system - Google Patents
CPU network interface adaptability test board card and test systemDownload PDFInfo
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- CN213276628U CN213276628UCN202021836529.4UCN202021836529UCN213276628UCN 213276628 UCN213276628 UCN 213276628UCN 202021836529 UCN202021836529 UCN 202021836529UCN 213276628 UCN213276628 UCN 213276628U
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Abstract
Translated fromChinese
Description
Technical Field
The application relates to the technical field of CPU testing, in particular to a CPU network interface adaptability testing board card and a testing system.
Background
With the technical development of the CPU chip design, the high-speed interface of the CPU can be configured into different protocol types through software, and different interface functions are realized, that is, the same interface can be configured into a PCIE interface, a network interface, a SATA storage interface, and the like.
In order to make the CPU accurately receive and transmit network data, the adaptation between the CPU network interface and the physical layer network chip plays an important role therein. In the prior art, a physical layer network chip needs to be integrated on a mainboard for relevant testing. When testing physical layer network chips of different manufacturers and different models, the mainboard needs to be redesigned, and the cost for redesigning the mainboard is high, so that the cost for testing the adaptability of the CPU network interface and the physical layer network chips is high.
SUMMERY OF THE UTILITY MODEL
In view of this, embodiments of the present application provide a board for testing the adaptability of a CPU network interface and a test system, which are convenient for reducing the test cost of the adaptability of the CPU network interface and a physical layer network chip.
The embodiment of the application provides a CPU network interface suitability test board card, including: the system comprises a printed circuit board, a first physical layer network chip, a first golden finger and a first group of network interfaces, wherein the printed circuit board is provided with the first physical layer network chip, the first golden finger and the first group of network interfaces; the first gold finger is connected with the first physical layer network chip, and the first physical layer network chip is connected with the first group of network interfaces.
According to a specific implementation manner of the embodiment of the application, the printed circuit board is further provided with a first system management bus, and the first physical layer network chip is connected with the first system management bus; the first system management bus is also connected with a first conversion chip, and the first conversion chip is correspondingly connected with each network interface in the first group of network interfaces respectively after dividing the first system management bus into N paths.
According to a specific implementation manner of the embodiment of the application, the first system management bus is further connected with a first conversion I/O interface chip and a second conversion I/O interface chip; the I/O interface of the first conversion I/O interface chip is connected with an in-place signal end, a transmission enabling control signal end, a transmission failure indication signal end and/or a reception loss indication signal end of the first group of network interfaces; and the I/O interface of the second conversion I/O interface chip is connected with the LED indicator lamp.
According to a specific implementation manner of the embodiment of the present application, the first physical layer network chip is connected to the in-place signal end, the transmission enable control signal end, the transmission failure indication signal end, and/or the reception loss indication signal end of the first group of network interfaces.
According to a specific implementation manner of the embodiment of the application, a first physical layer network chip configuration unit is further arranged on the printed circuit board, and the physical layer network chip configuration unit is respectively connected with the first system management bus and the physical layer network chip.
According to a specific implementation manner of the embodiment of the application, one end of the first system management bus, which is close to the first golden finger, is connected with a first jump cap selectable connector; a second jump cap selectable connector and a third jump cap selectable connector are arranged on the printed circuit board and adjacent to the first jump cap selectable connector; the second jump cap selectable connector is connected with a first pin of the first golden finger, the third jump cap selectable connector is connected with a second pin of the first golden finger, the first pin of the first golden finger is used for being connected to a substrate management controller on a mainboard, and the second pin of the first golden finger is used for being connected to a CPU on the mainboard.
According to a specific implementation manner of the embodiment of the application, a second physical layer network chip, a second golden finger and a second group of network interfaces are arranged on the printed circuit board; the second golden finger is connected with the second physical layer network chip, and the second physical layer network chip is connected with the second group of network interfaces.
According to a specific implementation manner of the embodiment of the application, the printed circuit board is further provided with a second system management bus, and the second physical layer network chip is connected with the second system management bus; and the second system management bus is also connected with a second conversion chip, and the second conversion chip is correspondingly connected with each network interface in the second group of network interfaces respectively after dividing the second system management bus into N paths.
According to a specific implementation manner of the embodiment of the application, a third-to-I/O interface chip and a fourth-to-I/O interface chip are further connected to the second system management bus; the I/O interface of the third conversion I/O interface chip is connected with the on-site signal end, the transmission enabling control signal end, the transmission failure indication signal end and/or the reception loss indication signal end of the second group of network interfaces; and the I/O interface of the fourth conversion I/O interface chip is connected with the LED indicator lamp.
According to a specific implementation manner of the embodiment of the application, one end of the second system management bus, which is close to the second gold finger, is connected to the fourth hop-cap optional connector; a fifth jump cap selectable connector and a sixth jump cap selectable connector are arranged on the printed circuit board and adjacent to the fourth jump cap selectable connector; the fifth jump cap selectable connector is connected with the first pin of the second golden finger, the sixth jump cap selectable connector is connected with the second pin of the second golden finger, the first pin of the second golden finger is used for being connected to a substrate management controller on a mainboard, and the second pin of the second golden finger is used for being connected to a CPU on the mainboard.
According to a specific implementation manner of the embodiment of the present application, the first group of network interfaces and the second group of network interfaces are respectively a plurality of SFP + optical module connectors arranged side by side.
The present application further provides a CPU network interface adaptability test system, including: the system comprises a mainboard and a CPU network interface adaptability test board card, wherein the mainboard is provided with a CPU chip and a PCIE slot connected with the CPU chip, and the CPU network interface adaptability test board card is inserted into the PCIE slot, wherein the CPU network interface adaptability test board card is the CPU network interface adaptability test board card in any one of the above implementation modes.
The application also provides a method for testing the adaptability of the CPU network interface, which comprises the following steps: a CPU network interface on a mainboard sends network test data to a test board card inserted in a PCIE slot on the mainboard; the test board card is the CPU network interface adaptability test board card in any one of the above implementation modes; the first physical layer network chip or the second physical layer network chip on the test board receives the network test data, converts the network test data to obtain first converted network test data, and sends the first converted network test data to the first group of network interfaces or the second network interface; the first physical layer network chip or the second physical layer network chip receives network test data returned from the first group of network interfaces or the second group of network interfaces and converts the returned network test data to obtain second converted network test data; the physical layer network chip sends the second conversion network test data to the CPU network interface; and the CPU network interface receives second conversion network test data and determines the adaptability of the CPU network interface and the first physical layer network chip or the second physical layer network chip according to the transmitted network test data and the second conversion network test data.
According to a specific implementation manner of the embodiment of the application, the method further includes: monitoring status information of the first set of network interfaces or the second network interface.
According to the CPU network interface adaptability test board card and the test system provided by the embodiment of the application, a first physical layer network chip, a first golden finger and a first group of network interfaces are arranged on the printed circuit board; wherein, the first golden finger is connected with the first physical layer network chip, the first physical layer network chip is connected with the first group of network interfaces, the testing board card of the embodiment is connected with the corresponding pins on the mainboard, the test of the adaptability of the CPU and the physical layer network chip can be realized, for different physical layer network chips, the board card can be redesigned and manufactured according to the structure of the embodiment, the test of the physical layer network chips with different types can be realized, the mainboard does not need to be redesigned, the problem that the cost of redesigning the mainboard is much higher than that of the redesigning the testing board card of the embodiment when testing the adaptability of the CPU network port and the physical layer network chip in the prior art is avoided, and the problem of higher cost caused by the test of the adaptability of the CPU network port and the physical layer network chip is solved, through the application of the testing board card of the embodiment, the testing cost of the adaptability of the CPU network interface and the physical layer network chip is reduced conveniently.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a CPU network interface adaptability test board according to an embodiment of the present application;
fig. 2 is an SMBus link topology diagram in a test board according to an embodiment of the present application;
fig. 3 is an SMBus link topology diagram in a test board according to another embodiment of the present application;
fig. 4 is a flowchart illustrating a method for testing the suitability of the CPU network interface according to an embodiment of the present application.
Detailed Description
The embodiments of the present application will be described in detail below with reference to the accompanying drawings.
It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 2 and fig. 3, the CPU network interface adaptability test board of this embodiment may include: the system comprises a printedcircuit board 1, wherein a first physicallayer network chip 2, a firstgolden finger 3 and a first group ofnetwork interfaces 4 are arranged on the printedcircuit board 1; the firstgolden finger 3 is connected with the first physicallayer network chip 2, and the first physicallayer network chip 2 is connected with the first group ofnetwork interfaces 4.
Printed circuit boards 1(PCB boards), also known as Printed circuit boards, are providers of electrical connections for electronic components. A printed circuit board in general may refer to a bare board, i.e. a circuit board without mounted components.
A first Physicallayer network chip 2, which is a Physical layer network chip (PHY chip) and can connect a data link layer device (MAC) to a Physical medium, such as an optical fiber or copper cable; thePHY chip 2 may convert data conforming to one protocol into data conforming to another protocol.
Thefirst gold Finger 3, which may be composed of a plurality of gold-plated conductive contacts, is called "gold Finger" or Finger because the surface is plated with gold and the conductive contacts are arranged like fingers, wherein the conductive contacts may also be called pins. The size and shape of the gold Finger can be determined according to actual conditions, and in one example, thegold Finger 3 is in a standard PCIE Finger form.
The conductive contact on thefirst gold finger 3 may also be configured as a network pin to transmit high-speed network data, and in one example, the network pin on thegold finger 3 may be an XGBE pin. The number of thenetwork pins 4 may be 1, or 2, 4, 7, and the like, and may be determined according to actual needs.
The first group of network interfaces is used to transmit the data converted by thefirst PHY chip 2 to an external device, or receive data sent by the external device, and may also be used to transmit the data converted by thePHY chip 2 to the test board card of this embodiment. The first set of network interfaces may include one or more than two network interfaces.
The CPU network interface can be configured into corresponding network protocols, such as KR and SFI protocols; the suitability of the CPU network interface to the PHY chip may be determined by network performance. The method can be carried out in the following specific situations: 1. the adaptability test can be carried out when a network interface of a CPU receives and transmits data; 2. the test board card of the embodiment is provided with at least two network interfaces which are respectively connected with two network ports of the CPU correspondingly; 3. the adaptability test can also be carried out when one network interface of one CPU sends data and one network interface of the other CPU receives data.
In this embodiment, a first PHY chip, a first gold finger, and a first group of network interfaces are disposed on the printed circuit board; wherein, the first golden finger is connected with the first PHY chip, the first PHY chip is connected with the first group of network interfaces, and is connected with the corresponding pin on the mainboard through the test board card of the embodiment, the adaptability test of the CPU and the PHY chip can be realized, for different PHY chips, the board card can be redesigned and manufactured according to the structure of the embodiment, the test of PHY chips with different models can be realized without redesigning the mainboard, thereby avoiding the need of redesigning the mainboard when testing different PHY chips and CPUs in the prior art, the cost of redesigning the motherboard is much higher than the cost of redesigning the test board of this embodiment, thereby causing the problem of higher cost when testing the adaptability of the CPU network port and the PHY chip, through the application of the test board card of the embodiment, the test cost of the adaptability of the CPU network interface and the PHY chip is reduced conveniently.
In order to conveniently and flexibly configure the first PHY chip, another embodiment of the present application is basically the same as the above embodiment, except that the printedcircuit board 1 of the test board of the present embodiment is further provided with a first system management bus, and thefirst PHY chip 2 is connected to the first system management bus; the first system management bus is further connected with a first conversion chip 5, and the first conversion chip 5 is correspondingly connected with each network interface in the first group ofnetwork interfaces 4 after dividing the first system management bus into N paths.
The first System Management Bus (SMBus) provides a control Bus for System and power Management tasks, and with the SMBus System, messages sent and received between devices are all through the SMBus, rather than using separate control lines, which can save the pin count of the devices. Further, using the SMBus, the device may also provide its production information, tell the system its model, part number, etc., save its status for a pending event, report a different class of errors, receive control parameters, and return its status, etc.
In this embodiment, thefirst PHY chip 2 is connected to the first system management bus, which can facilitate configuration of thefirst PHY chip 2 through the first system management bus.
The first conversion chip 5 can divide the first system management bus into N paths, wherein N is more than or equal to 2; after being divided into N paths, the N paths of the network interfaces are correspondingly connected with each network interface in the first group ofnetwork interfaces 4 respectively, so that internal data of each network interface, such as information of the working temperature of the network interface and the like, can be conveniently obtained when the network interface is used.
In one example, the first conversion chip may be a system management bus expansion chip, and the specific model may be 9546.
In order to facilitate monitoring of the state of the first network interface and facilitate intuitive understanding of the state of the test board, another embodiment of the present application is basically the same as the above embodiments, except that in the test board of the present embodiment, the first system management bus is further connected with a first transfer I/O interface chip 6 and a second transfer I/O interface chip 7; the I/O interface of the first conversion I/O interface chip 6 is connected with the on-site signal end, the transmission enabling control signal end, the transmission failure indication signal end and/or the reception loss indication signal end of the first group ofnetwork interfaces 4; the I/O interface of the second conversion I/O interface chip 7 is connected with an LED indicator light 8.
The first I/O interface chip 6 may be a chip with an input/output expansion function, and specifically may be a 9555 chip, and may connect an IO interface of the first I/O interface chip to in-place (MODABS), transmission enable control (TXDIS), transmission failure indication (TXFAULT), and reception loss indication (RXLOS) signal pins of the first set ofnetwork interfaces 4, so as to monitor states of the first set ofnetwork interfaces 4.
The second conversion I/O interface chip 7 may be a chip with an input/output expansion function, and specifically may be a 9555 chip; the I/O interface of the second conversion I/O interface chip 7 is connected with the LED indicator light 8, the working state of the test board can be represented by the on-off state of one LED indicator light, the color or the on-off state of more than two LED indicator lights, the color and different combination states thereof, such as whether the board card works normally and what faults occur when faults occur, the states can be associated with the states of the indicator lights, such as green can be displayed when the board card works normally, red can be displayed when the board card works abnormally, or normal can be represented by a flashing mode, and abnormal can be represented when the board card does not flash.
In order to facilitate the first PHY chip to obtain the status of the first group of network interfaces, in another embodiment of the present application, thefirst PHY chip 2 is connected to the in-place signal end, the transmission enable control signal end, the transmission failure indication signal end, and/or the reception loss indication signal end of the first group ofnetwork interfaces 4.
In order to conveniently and flexibly configure the first PHY chip, another embodiment of the present application is basically the same as the above embodiment, except that the test board of the present embodiment is further provided with a PHY chip configuration unit 9 on the printedcircuit board 1, and the PHY chip configuration unit 9 is connected to the first system management bus and the first PHY chip, respectively.
The PHY chip configuration Unit 9 may be a Micro Control Unit (MCU), or may also be an Electrically Erasable Programmable Read Only Memory (EEPROM), where the EEPROM is a memory chip whose data is not lost after power failure, and can store test data in the EEPROM so as to read test information; the PHY chip configuration unit 9 may configure the operation mode of thefirst PHY chip 2 to implement conversion between different protocol data, such as converting data of KR protocol into data of SFI protocol. When the MCU is used for configuration, the MCU can be connected with the first PHY chip through the MDC/MDIO interface so as to configure the first PHY chip. When the EEPROM is used for configuring the first PHY chip, the configuration information of the first PHY is stored in the EEPROM, and the first PHY chip is automatically configured after the test board card is electrified.
In order to flexibly select the CPU or the baseboard management controller to carry out configuration management on the equipment connected on the first system management bus, one end of the first system management bus close to the firstgolden finger 3 is connected with the first jump capselectable connector 10; a second jump-cap selectable connector 11 and a third jump-cap selectable connector 12 are arranged on the printedcircuit board 1 and adjacent to the first jump-cap selectable connector 10; the second jump cap selectable connector 11 is connected with the first pin of the firstgolden finger 3, the third jump capselectable connector 12 is connected with the second pin of the firstgolden finger 3, thefirst pin 30 of the firstgolden finger 3 is used for being connected to a substrate management controller on a mainboard, and thesecond pin 32 of the firstgolden finger 3 is used for being connected to a CPU on the mainboard.
The PCIE Finger standard defines only one SMBUS signal, which can be connected to the CPU or BMC. There are also a plurality of Reserved (RSVD, Reserved) but undefined pins on the PCIE Finger, and some motherboards define part of the RSVD pins as SMBUS. In an example, the first pin and the second pin on the test board card of this embodiment define RSVD pins on a gold finger as SMBUS signal pins.
The firstjumper alternative connector 10, the second jumper alternative connector 11, and/or the secondjumper alternative connector 12 may be 3pin connectors.
A Baseboard Management Controller (BMC) has monitoring and control functions, and the operation objects are system hardware, for example, by monitoring the temperature, voltage, fan, power supply, etc. of the system and performing corresponding adjustment work, so as to ensure that the system is in a healthy state. The information and log records of various hardware can be recorded for prompting the user and positioning of subsequent problems; the BMC is an independent system, and does not depend on other hardware (such as a CPU, a memory, and the like) on the system, nor on the BIOS, the OS, and the like (but the BMC may interact with the BIOS and the OS, which may have a better platform management effect, and system management software under the OS may cooperate with the BMC to achieve a better management effect).
The test board card of this embodiment may be in a PCIE card form, and in order to be conveniently applied to the inside of the standard chassis, the test board card of this embodiment may be designed according to the size of the standard PCIE card, for example, the test board card has the same size as a full-height half-length card of the standard PCIE, and further, in order to save cost, an adaptability test of two PHY chips and a CPU network port may be performed on one test board card, see fig. 1, an embodiment of this application is basically the same as the above embodiment, but the difference is that asecond PHY chip 13, asecond gold finger 14, and a second group of network interfaces 15 are arranged on the printed circuit board; wherein thesecond gold finger 14 is connected to thesecond PHY chip 13, and thesecond PHY chip 13 is connected to the second group of network interfaces 15. The first group ofnetwork interfaces 4 and the second group of network interfaces 15 are a plurality of SFP + optical module connectors arranged side by side, respectively.
The SFP + optical module can be an enhanced small pluggable transceiver optical module, and is provided with an interface for plugging an optical cable, and the optical cable can be inserted into the interface to test the adaptability of the CPU port and the PHY chip.
Thefirst gold finger 3 and thesecond gold finger 14 may be the same gold finger, in which case there are jumper cap option connectors between the gold finger and thefirst PHY chip 2, and between the gold finger and thesecond PHY chip 13.
In order to conveniently and flexibly configure thesecond PHY chip 13, another embodiment of the present application is basically the same as the above embodiment, except that the printedcircuit board 1 of the test board of the present embodiment is further provided with a second system management bus, and thesecond PHY chip 13 is connected to the second system management bus;
the second system management bus is further connected with asecond conversion chip 16, and thesecond conversion chip 16 is correspondingly connected with each network interface in the second group of network interfaces after dividing the second system management bus into N paths.
The second System Management Bus (SMBus) provides a control Bus for System and power Management tasks, and with the SMBus System, messages sent and received between devices are all through the SMBus, rather than using separate control lines, which can save the pin count of the devices. Further, using the SMBus, the device may also provide its production information, tell the system its model, part number, etc., save its status for a pending event, report a different class of errors, receive control parameters, and return its status, etc.
In this embodiment, thesecond PHY chip 13 is connected to the second system management bus, which can facilitate configuration of thefirst PHY chip 2 through the second system management bus.
Thesecond conversion chip 16 can divide the second system management bus into N paths, wherein N is greater than or equal to 2; the N paths of the data are correspondingly connected with each network interface in the second group of network interfaces 15, so that internal data of each network interface, such as working temperature and other information of the network interface, can be conveniently acquired during use.
In one example, thesecond conversion chip 16 may be a system management bus expansion chip, and the specific model may be 9546.
In order to facilitate monitoring of the state of the first network interface and facilitate intuitive understanding of the state of the test board, another embodiment of the present application is basically the same as the above embodiment, except that in the test board of the present embodiment, the second system management bus is further connected with a third-to-I/O interface chip 17 and a fourth-to-I/O interface chip 18; the I/O interface of the third conversion I/O interface chip 17 is connected with the on-site signal end, the transmission enable control signal end, the transmission failure indication signal end and/or the reception loss indication signal end of the second group of network interfaces 15; the I/O interface of the fourth rotary I/O interface chip 18 is connected with anLED indicator light 19.
The third transfer I/O interface chip 17 may be a chip with an input/output expansion function, and specifically may be a 9555 chip, and an IO interface of the third transfer I/O interface chip 17 may be connected to in-place (MODABS), transmission enable control (TXDIS), transmission failure indication (TXFAULT), and reception loss indication (RXLOS) signal pins of the second group of network interfaces 15, so as to monitor the status of the second group of network interfaces 15.
The fourth conversion I/O interface chip 18 may be a chip with an input/output expansion function, and specifically may be a 9555 chip; the I/O interface of the fourth I/O interface chip 18 is connected to theLED indicator 19, and the working status of the test board can be indicated by the on/off status of one LED indicator, the color of the LED indicator, the on/off status of two or more LED indicators, the color of the LED indicator, and different combinations thereof, such as whether the board card is working normally and what fault occurs when a fault occurs, and these statuses can be associated with the status of the indicator, such as green when working normally, red when abnormal occurs, or normal when flashing occurs, and abnormal when not flashing occurs.
In order to flexibly select the configuration management of the device connected on the second system management bus by the CPU or the baseboard management controller, one end of the second system management bus close to the secondgolden finger 14 is connected with the fourth jump capselectable connector 20; a fifth jumpcap option connector 21 and a sixth jumpcap option connector 22 are arranged on the printedcircuit board 1 adjacent to the fourth jumpcap option connector 20; the fifth jump capselectable connector 21 is connected to thefirst pin 140 of thesecond gold finger 14, the sixth jump capselectable connector 22 is connected to thesecond pin 142 of thesecond gold finger 14, thefirst pin 140 of thesecond gold finger 14 is used for being connected to a substrate management controller on a motherboard, and thesecond pin 142 of thesecond gold finger 14 is used for being connected to a CPU on the motherboard.
The fourth jumperalternative connector 20, the fifth jumperalternative connector 21, and/or the sixth jumperalternative connector 22 may be 3pin connectors.
Referring to fig. 1, an embodiment of the present application further provides a CPU network interface suitability test system, including: the system comprises a mainboard and a CPU network interface adaptability test board card, wherein the mainboard is provided with a CPU chip and a PCIE slot connected with the CPU chip, and the CPU network interface adaptability test board card is inserted into the PCIE slot, wherein the CPU network interface adaptability test board card is the CPU network interface adaptability test board card in the embodiment.
The main board is called main board (main board), system board (system board) or mother board (thermal board), the main board is generally rectangular circuit board, on which the main circuit system forming the computer is mounted, and generally there are elements of BIOS chip, I/O control chip, keyboard and panel control switch interface, indicator lamp plug-in unit, expansion slot, main board and direct current power supply plug-in unit of plug-in card and CPU chip socket, etc.; the CPU is mounted in a CPU chip socket.
In one example, a PCIE slot on a motherboard has a configurable XGBE network interface.
In this embodiment, a CPU chip and a PCIE slot connected to the CPU chip are disposed on a motherboard, and the CPU network interface adaptability test board is inserted into the PCIE slot, where the CPU network interface adaptability test board is the CPU network interface adaptability test board described in any of the foregoing embodiments, and can test the CPU network interface on the motherboard and the PHY chip on the test board, and an existing motherboard can be used, and when testing different PHY chips, the motherboard does not need to be redesigned, which avoids the problem that the cost for redesigning the motherboard is much higher than the cost for redesigning the test board in this embodiment when testing different PHY chips and CPUs in the prior art, thereby causing a higher cost for testing the adaptability of the CPU network port and the PHY chip, and through the application of the test board of this embodiment, the cost of the CPU network port and the PHY chip suitability test can be reduced.
Referring to fig. 4, an embodiment of the present application further provides a method for testing the suitability of a CPU network interface, including:
The CPU network interface can be a CPU port configured with a network protocol; network test data, which may include a plurality of data packets; the network test data sent by the CPU network interface of this embodiment may be data sent at a certain rate, such as XGBE, such as 1G, 10G, and so on.
102, receiving the network test data by a first physical layer network chip on the test board, converting the network test data to obtain first converted network test data, and sending the first converted network test data to the first group of network interfaces.
A first Physical layer network chip (PHY chip) that is a Port Physical layer (PHY chip) and is capable of connecting a data link layer device (MAC) to a Physical medium, such as an optical fiber or a copper cable; the PHY chip may convert data conforming to one protocol to data conforming to another protocol. For example, the CPU network interface sends data conforming to KR protocol, and the data can be converted into data conforming to another protocol by the PHY chip so as to transmit the data to an external device.
And step 104, the first PHY chip sends the second conversion network test data to the CPU network interface.
And 105, the CPU network interface receives second conversion network test data, and determines the adaptability of the CPU network interface and the first PHY chip according to the transmitted network test data and the second conversion network test data.
The network performance index, such as bit error rate, time delay and/or packet loss rate, can be determined according to the transmitted network test data and the second converted network test data, and then the adaptability of the CPU network interface and the first PHY chip can be determined according to the network performance index.
In an example, through the network test data and the second converted network test data sent by the CPU, the bit error rate and/or the packet loss rate may be calculated to determine the suitability of the CPU network interface with the first PHY chip, specifically, if the packet loss rate is smaller than a certain threshold, the CPU network interface is adapted with the first PHY chip, and if the packet loss rate is greater than a certain threshold, the suitability of the CPU network interface with the first PHY chip is poor, which may be caused by a low performance of the first PHY chip; or, if the error rate is less than a certain threshold, the CPU network interface is adapted to the first physical layer network chip; if the error rate is greater than a certain threshold, the adaptability between the CPU network interface and the first PHY chip is poor, possibly because the first PHY chip has a low performance.
Another embodiment of the present application is basically the same as the foregoing embodiments, except that, in the method of this embodiment, after the CPU network interface on the motherboard sends network test data to the test board card inserted in the PCIE slot on the motherboard, the method further includes: recording a first moment when a CPU network interface on the mainboard sends network test data to a test board card inserted in a PCIE slot on the mainboard;
after the CPU network interface receives the second converted network test data, the method further includes: and recording a second moment when the CPU network interface receives the second conversion network test data.
And determining the adaptability of the CPU network interface and the first PHY chip according to the first time and the second time.
In order to monitor the network interface when performing the suitability test of the CPU network interface and the PHY chip, the method of this embodiment further includes: monitoring status information of the first set of network interfaces or the second network interface.
The first PHY chip and the first group of network interfaces are taken as examples to describe the suitability test of the CPU network interface and the first PHY chip, and it can be understood that the above method is also applicable to the suitability test of the second PHY chip and the second group of network interfaces on the CPU network interface and the second PHY chip.
The method can monitor an in-place signal end, a transmission enabling control signal end, a transmission failure indication signal end and/or a reception loss indication signal end of a first group of network interfaces or a second network interface, and can also monitor the internal state of the first group of network interfaces or the second network interface; specifically, the monitoring may be performed by the first PHY chip or the second PHY chip, or may be performed by the first conversion chip or the second conversion chip.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (12)
1. A CPU network interface adaptability test board card is characterized by comprising: the system comprises a printed circuit board, a first physical layer network chip, a first golden finger and a first group of network interfaces, wherein the printed circuit board is provided with the first physical layer network chip, the first golden finger and the first group of network interfaces; the first gold finger is connected with the first physical layer network chip, and the first physical layer network chip is connected with the first group of network interfaces.
2. The test board card of claim 1, wherein a first system management bus is further disposed on the printed circuit board, and the first physical layer network chip is connected to the first system management bus;
the first system management bus is also connected with a first conversion chip, and the first conversion chip is correspondingly connected with each network interface in the first group of network interfaces respectively after dividing the first system management bus into N paths.
3. The test board of claim 2, wherein the first system management bus further has a first I/O interface conversion chip and a second I/O interface conversion chip connected thereto;
the I/O interface of the first conversion I/O interface chip is connected with an in-place signal end, a transmission enabling control signal end, a transmission failure indication signal end and/or a reception loss indication signal end of the first group of network interfaces;
and the I/O interface of the second conversion I/O interface chip is connected with the LED indicator lamp.
4. The test board of claim 2, wherein the first physical layer network chip is connected to an in-place signal port, a transmit enable control signal port, a transmit failure indication signal port, and/or a receive loss indication signal port of the first set of network interfaces.
5. The test board of claim 2, wherein a first physical layer network chip configuration unit is further disposed on the printed circuit board, and the physical layer network chip configuration unit is connected to the first system management bus and the physical layer network chip, respectively.
6. The test board of claim 2, wherein an end of the first system management bus proximate to the first gold finger is connected to a first jumper cap option connector;
a second jump cap selectable connector and a third jump cap selectable connector are arranged on the printed circuit board and adjacent to the first jump cap selectable connector; the second jump cap selectable connector is connected with a first pin of the first golden finger, the third jump cap selectable connector is connected with a second pin of the first golden finger, the first pin of the first golden finger is used for being connected to a substrate management controller on a mainboard, and the second pin of the first golden finger is used for being connected to a CPU on the mainboard.
7. The test board card of claim 1, wherein a second physical layer network chip, a second gold finger and a second group of network interfaces are arranged on the printed circuit board; the second golden finger is connected with the second physical layer network chip, and the second physical layer network chip is connected with the second group of network interfaces.
8. The test board card of claim 7, wherein a second system management bus is further disposed on the printed circuit board, and the second physical layer network chip is connected to the second system management bus;
and the second system management bus is also connected with a second conversion chip, and the second conversion chip is correspondingly connected with each network interface in the second group of network interfaces respectively after dividing the second system management bus into N paths.
9. The test board of claim 8, wherein a third-to-I/O interface chip and a fourth-to-I/O interface chip are further connected to the second system management bus;
the I/O interface of the third conversion I/O interface chip is connected with the on-site signal end, the transmission enabling control signal end, the transmission failure indication signal end and/or the reception loss indication signal end of the second group of network interfaces;
and the I/O interface of the fourth conversion I/O interface chip is connected with the LED indicator lamp.
10. The test board of claim 8, wherein an end of the second system management bus proximate to the second gold finger is connected to a fourth hop-cap option connector;
a fifth jump cap selectable connector and a sixth jump cap selectable connector are arranged on the printed circuit board and adjacent to the fourth jump cap selectable connector; the fifth jump cap selectable connector is connected with the first pin of the second golden finger, the sixth jump cap selectable connector is connected with the second pin of the second golden finger, the first pin of the second golden finger is used for being connected to a substrate management controller on a mainboard, and the second pin of the second golden finger is used for being connected to a CPU on the mainboard.
11. The test card of claim 7, wherein the first set of network interfaces and the second set of network interfaces are each a plurality of SFP + optical module connectors arranged side-by-side.
12. A CPU network interface suitability test system is characterized by comprising: the device comprises a mainboard and a CPU network interface adaptability test board card, wherein the mainboard is provided with a CPU chip and a PCIE slot connected with the CPU chip, and the CPU network interface adaptability test board card is inserted into the PCIE slot, wherein the CPU network interface adaptability test board card is the CPU network interface adaptability test board card of any one of the claims 1-11.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202021836529.4UCN213276628U (en) | 2020-08-28 | 2020-08-28 | CPU network interface adaptability test board card and test system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202021836529.4UCN213276628U (en) | 2020-08-28 | 2020-08-28 | CPU network interface adaptability test board card and test system |
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| CN213276628Utrue CN213276628U (en) | 2021-05-25 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111949464A (en)* | 2020-08-28 | 2020-11-17 | 海光信息技术有限公司 | CPU network interface adaptability test board card, test system and test method |
- 2020
- 2020-08-28CNCN202021836529.4Upatent/CN213276628U/enactiveActive
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111949464A (en)* | 2020-08-28 | 2020-11-17 | 海光信息技术有限公司 | CPU network interface adaptability test board card, test system and test method |
| CN111949464B (en)* | 2020-08-28 | 2025-01-28 | 海光信息技术股份有限公司 | A CPU network interface adaptability test board, test system and test method |
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