CN211017082U - Super junction type MOSFET device - Google Patents

Abstract

The utility model discloses a super junction type MOSFET device relates to semiconductor power device field. The method is used for solving the problem that the resistance of a JFET (junction field effect transistor) region is high due to the limitation of the width of a P-body region when the distance between the existing P columns is reduced. The device includes: a P-type column deep groove, a first epitaxial layer, a second epitaxial layer, a P-body region and N⁺A source region; the P-type column deep groove is located in the first epitaxial layer, and the second epitaxial layer is located in the P-type column deep groove and the first epitaxial layerAn upper layer of an epitaxial layer; the P-body region is positioned in the second epitaxial layer, the P-type column deep groove is positioned right below the P-body region, and the width of the P-body region is smaller than that of the P-type column deep groove; two of N⁺The source regions are respectively positioned at two sides of the P-body region.

Description

Super junction type MOSFET device

Technical Field

The utility model relates to a semiconductor power device technical field, more specifically relate to a super junction type MOSFET device.

Background

A Metal-Oxide-Semiconductor Field effect transistor (MOSFET), referred to as a MOSFET for short, is a Field effect transistor that can be widely used in analog circuits and digital circuits.

In order to reduce the power loss of power components used in a DC-DC (direct current to direct current) converter, in MOSFET power components, the power loss generated during the operation of MOS (metal oxide semiconductor) devices can be effectively reduced by reducing the on-resistance of the components. In practical applications, the breakdown voltage of the MOS device is inversely proportional to the on-resistance, so that when the on-resistance is reduced, the breakdown voltage is adversely affected. Due to the problem of thermal diffusion of a traditional super-junction device, the phenomenon of uneven charge distribution caused by mutual diffusion of a P-type column and an N-type column in a body region of a super-junction structure can be caused, and the problem of low breakdown voltage generated when the device works can be influenced. Meanwhile, with the continuous reduction of the design size of components, cost control is the largest bottleneck of each current process platform, so that on the premise of consistent device characteristics, the cost control becomes a key factor for improving the main competitiveness of the components in the market.

The manufacturing process of the conventional super junction type power device is shown in fig. 1A to 1D, and specifically comprises the following steps: 1) forming a P-type columnar junction by etching the deep trench and growing an epitaxial process; 2) forming a gate oxide layer and a polysilicon gate of the device, and finishing etching the polysilicon gate; 3) forming the P-body region of the device, and N⁺A source region; 4) and forming an insulating medium layer, a contact hole and a metal contact of the device.

In the above manufacturing process, since the concentration of the P-type pillar structure is high, the P-body region must be wider than the P-type pillar, such as L1 > L2 shown in fig. 1D, otherwise the channel concentration is too dense and the turn-on voltage is difficult to control, but as the feature size of the device is reduced, L1 cannot be reduced without limit because L2 in the JFET (field-effect transistor) region of the device must be secured with a certain width and the resistance of the JFET region is small, thereby achieving the reduction of the on-resistance of the whole device.

In summary, since the concentration of P + pillars is higher than the body region concentration in the conventional MOSFET process, the distance between P pillars is limited by the width of P-body region when the distance between P pillars is reduced, resulting in a problem of relatively high resistance of the JFET region.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides a super junction type MOSFET device for receive the restriction of P-body region width when solving the distance between the current P post and shrinking, lead to the higher problem of resistance ratio in JFET district.

The embodiment of the utility model provides a super junction type MOSFET device, include: a P-type column deep groove, a first epitaxial layer, a second epitaxial layer, a P-body region and N⁺A source region;

the P-type column deep groove is positioned in the first epitaxial layer, and the second epitaxial layer is positioned on the P-type column deep groove and the upper layer of the first epitaxial layer;

the P-body region is positioned in the second epitaxial layer, the P-type column deep groove is positioned right below the P-body region, and the width of the P-body region is smaller than that of the P-type column deep groove;

two of N⁺The source regions are respectively positioned at two sides of the P-body region.

Preferably, the device also comprises a polysilicon grid and a grid oxide layer;

the gate oxide layer and the polysilicon gate are sequentially arranged on the second epitaxial layer and extend to the P-body region and the N⁺An upper layer of the source region.

Preferably, the device further comprises an insulating oxide layer and a metal layer;

the insulation oxide layer is arranged on the upper layer of the polysilicon gate, and part of the insulation oxide layerThe edge oxide layer extends out of the polysilicon gate and is positioned on part of the N⁺An upper layer of the source region;

the metal layer is arranged on the upper layer of the insulating oxide layer, and part of the metal layer extends out of the insulating oxide layer and is arranged on part of the N⁺A source region and a portion of the upper layer of the P-body region.

Preferably, the epitaxial wafer further comprises a substrate layer, and the substrate layer is located right below the first epitaxial layer.

An embodiment of the utility model provides a super junction type MOSFET device, this device includes: a P-type column deep groove, a first epitaxial layer, a second epitaxial layer, a P-body region and N⁺A source region; the P-type column deep groove is positioned in the first epitaxial layer, and the second epitaxial layer is positioned on the P-type column deep groove and the upper layer of the first epitaxial layer; the P-body region is positioned in the second epitaxial layer, the P-type column deep groove is positioned right below the P-body region, and the width of the P-body region is smaller than that of the P-type column deep groove; two of N⁺The source regions are respectively positioned at two sides of the P-body region. In the super junction type MOSFET device, a first epitaxial layer and a second epitaxial layer are sequentially formed in a multi-epitaxial layer injection mode, a P-type column deep groove is formed in the first epitaxial layer, a P-body area is formed in the second epitaxial layer, the P-body area in the second epitaxial layer can be completely positioned on the upper layer of the P-type column deep groove, the width of the P-body area is smaller than that of the P-type column deep groove, the distance between every two adjacent P-body areas is larger than that between every two adjacent P-type column deep grooves, and the structure can effectively reduce the size of a unit cell; further, if the distance between the P-type pillar deep grooves in the first epitaxial layer can be small enough, the distance between the P-body regions in the second epitaxial layer can also be adjusted by the process, so that the JFET region with low enough resistance can be obtained. The embodiment of the utility model provides a super junction type MOSFET device has solved and has received the restriction of P-body region width when the distance between the current P type post deep groove reduces, leads to the higher problem of resistance ratio in JFET district.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1A is a schematic diagram illustrating an epitaxial layer and a P-type columnar junction prepared in the prior art;

FIG. 1B is a schematic diagram of a gate oxide and polysilicon gate fabrication provided in the prior art;

FIG. 1C shows a P-body region and N provided in the prior art⁺Preparing a schematic diagram of a source region;

FIG. 1D is a schematic diagram illustrating the fabrication of an insulating dielectric layer, a contact hole and a metal contact provided in the prior art;

fig. 2 is a schematic diagram of a super junction MOSFET device according to an embodiment of the present invention;

fig. 3 is a schematic view of a super junction MOSFET device manufacturing process according to an embodiment of the present invention;

fig. 4A is a schematic diagram illustrating the preparation of an epitaxial layer and a P-type columnar junction according to an embodiment of the present invention;

fig. 4B is a schematic diagram illustrating the preparation of a second epitaxial layer according to an embodiment of the present invention;

FIG. 4C is a schematic diagram of the gate oxide layer and the polysilicon gate according to an embodiment of the present invention

Fig. 4D is a schematic diagram of the preparation of the P-body region according to an embodiment of the present invention;

FIG. 4E shows N provided by an embodiment of the present invention⁺Preparing a schematic diagram of a source region;

fig. 4F is a schematic view illustrating a preparation of an insulating medium layer according to an embodiment of the present invention;

fig. 4G is a schematic diagram of a contact hole and a metal contact manufacturing process according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Fig. 1A to fig. 1D are schematic diagrams of a super junction type power device manufacturing structure provided in the prior art, and a manufacturing process of the super junction type power device mainly includes the following steps:

step 11, as shown in fig. 1A, forming an N-type lightly dopedepitaxial layer 102 on an N-type heavily dopedsubstrate 101 provided on the N-type heavily dopedsubstrate 101, etching the N-type lightly dopedepitaxial layer 102, and forming a P-type columnar junction 103 in the N-type lightly dopedepitaxial layer 102.

Step 12, as shown in fig. 1B, agate oxide layer 104 is formed on the surface of the N-type lightly dopedepitaxial layer 102 between the P-type columnar junctions 103, and apolysilicon gate 105 is formed on the surface of thegate oxide layer 104.

Step 13, As shown in fig. 1C, B implantation and diffusion are performed on the upper portion of the N-type lightly dopedepitaxial layer 102 to form a P-type body region 106, As implantation and diffusion are performed on the upper portion of the N-type lightly dopedepitaxial layer 102 to form an N-type body region 106⁺Asource region 107.

Step 14, as shown in fig. 1D, a growth thickening process is performed on the upper portion of the N-type lightly dopedepitaxial layer 102 and the upper portion of thepolysilicon gate 105 to form anoxide insulation layer 108.

As shown in fig. 1D, since the concentration of the P-type column junctions 103 is higher than that of the P-type body regions 106 in the conventional MOSFET process, the distance between the P-type column junctions 103 must not be too close to leave enough diffusion space for the P-type body regions 106 in consideration of the turn-on voltage of the device. Therefore, the width of the P-body 106 must be larger than that of the P-type pillar 103, otherwise the channel concentration is too dense and the turn-on voltage is difficult to control. In order to solve the above problem, the embodiment of the present invention provides a super junction MOSFET device, where the distance between P-type columnar junctions 103 in the super junction MOSFET device is smaller than the distance between P-body regions 106, which can effectively reduce the cell size and increase the resistance of the JFET region. The manufacturing cost of the device is not increased on the premise of ensuring that the performance of the device can be improved.

Fig. 2 exemplarily shows a schematic structural diagram of a super junction MOSFET device provided by an embodiment of the present invention, as shown in fig. 2, the super junction MOSFET device mainly includes a P-typedeep trench 203, afirst epitaxial layer 202, asecond epitaxial layer 204, a P-body region 207 and an N-body region⁺Asource region 208.

As shown in fig. 2, the epitaxial layer of the super junction MOSFET device provided by the embodiment of the present invention includes afirst epitaxial layer 202 and asecond epitaxial layer 204, wherein a P-type columndeep trench 203 is located in thefirst epitaxial layer 202, and a P-body region 207 is located in thesecond epitaxial layer 204.

Specifically, thefirst epitaxial layer 202 is located above thesubstrate layer 201, the P-type pillardeep groove 203 is located in thefirst epitaxial layer 202, a notch of the P-type pillardeep groove 203 is located on the upper surface of thefirst epitaxial layer 202, the P-type pillardeep groove 203 vertically extends downwards from the upper surface of thefirst epitaxial layer 202, and the depth of the P-type pillardeep groove 203 is smaller than the thickness of thefirst epitaxial layer 202. Accordingly, thesecond epitaxial layer 204 is located on the upper surfaces of the P-type pillardeep trench 203 and thefirst epitaxial layer 202, i.e., the upper surface of the P-type pillardeep trench 203 is in contact with the lower surface of thesecond epitaxial layer 204.

Further, P-body region 207 is located withinsecond epitaxial layer 204, the notch of P-body region 207 is located on the upper surface ofsecond epitaxial layer 204, the depth of P-body region 207 is consistent with the thickness ofsecond epitaxial layer 204, and P-body region 207 is located just above P-pillardeep trench 203. In the prior art, since the P-typedeep trenches 203 and the P-body regions 207 are both located in thefirst epitaxial layer 202, and since the concentration of the P-typedeep trenches 203 is higher than that of the P-body regions 207, the distance between the P-typedeep trenches 203 is relatively large, i.e., the width of the P-body regions 207 must be larger than that of the P-typedeep trenches 203, otherwise the channel concentration is too strong, and the turn-on voltage is difficult to control. And in the embodiment of the present invention, because the P-type columndeep trench 203 and the P-body region 207 are respectively located in two different epitaxial layers, therefore, after thesecond epitaxial layer 204 is subjected to the body region implantation and drive-in process, the width driven in the body region of thesecond epitaxial layer 204 is smaller than the width of the P-type columndeep trench 203, that is, the width of the P-body region 207 directly above the P-type columndeep trench 203 is smaller than the width of the P-type columndeep trench 203, and the distance between the two P-body regions 207 is greater than the distance between the two P-type columndeep trenches 203.

Further, N is distributed on two sides above the P-body region 207⁺Asource region 208.

As shown in fig. 2, agate oxide 205 and apolysilicon gate 206 are further included, which are disposed above thesecond epitaxial layer 204, and both ends of thegate oxide 205 and thepolysilicon gate 206 extend to the P-body 207 and the N-body 207⁺Above thesource region 208, further, an insulatingoxide layer 209 is disposed above and on the side of thegate oxide layer 205 and thepolysilicon gate 206, that is, thegate oxide layer 205 and thepolysilicon gate 206 are wrapped by the insulating oxide layer, and themetal layer 210 is disposed above the insulating oxide layer and thesecond epitaxial layer 204, where it should be noted that thesecond epitaxial layer 204 refers to a region not covered by thegate oxide layer 205, thepolysilicon gate 206 and the insulating oxide layer. As shown in fig. 2, the region of themetal layer 210 overlying thesecond epitaxial layer 204 is located just above the P-body region 207, i.e., themetal layer 210 is disposed on the oxide insulating layer and part of the P-body region 207 and part of the N⁺An upper layer ofsource region 208.

In order to more clearly introduce the super junction MOSFET device provided by the embodiments of the present invention, a method for manufacturing the super junction MOSFET device is described below.

Fig. 3 is a schematic flow chart of a method for manufacturing a super junction MOSFET device according to an embodiment of the present invention, and fig. 4A is a schematic diagram of an epitaxial layer and a P-type columnar junction according to an embodiment of the present invention;

fig. 4B is a schematic diagram illustrating the preparation of a second epitaxial layer according to an embodiment of the present invention; fig. 4C is a schematic diagram illustrating a gate oxide layer and a polysilicon gate according to an embodiment of the present invention; fig. 4D is a schematic diagram of the preparation of the P-body region according to an embodiment of the present invention; FIG. 4E shows N provided by an embodiment of the present invention⁺Preparing a schematic diagram of a source region; fig. 4F is a schematic view illustrating a preparation of an insulating medium layer according to an embodiment of the present invention; fig. 4G is a schematic diagram of a contact hole and a metal contact manufacturing process according to an embodiment of the present invention.

In the following, a schematic flow diagram of the manufacturing method provided by fig. 3 is combined with the schematic manufacturing diagrams provided by fig. 4A to 4G to describe in detail a method for manufacturing a super junction MOSFET device, specifically, as shown in fig. 3, the method mainly includes the following steps:

step 21, forming a P-type columndeep groove 203 in thefirst epitaxial layer 202 by an etching method, and forming asecond epitaxial layer 204 on the upper surface of the P-type columndeep groove 203 and above thefirst epitaxial layer 202;

step 22, forming agate oxide layer 205 and apolysilicon gate 206 above thesecond epitaxial layer 204;

step 23, forming a P-body region 207 in thesecond epitaxial layer 204 above the P-type pillardeep trench 203 by using an ion implantation method;

step 24, forming two N in the P-body region 207 by ion implantation⁺A source region 208;

instep 25, an insulatingoxide layer 209 and ametal layer 210 are sequentially formed on thepolysilicon gate 206.

Instep 21, as shown in fig. 4A, afirst epitaxial layer 202 of N type of the first conductivity type with low doping concentration is grown on the semiconductor substrate of N type of the first conductivity type with high doping concentration. Further, the first conductive typefirst epitaxial layer 202 is selectively masked and etched to obtain a desired P-type pillardeep trench 203 in the first conductive typefirst epitaxial layer 202, a notch of the P-type pillardeep trench 203 is located on an upper surface of the first conductive typefirst epitaxial layer 202, the P-type pillardeep trench 203 vertically extends downward from an upper end surface of the first conductive typefirst epitaxial layer 202, and a depth of the P-type pillardeep trench 203 is smaller than a thickness of the first conductive typefirst epitaxial layer 202. The material of the semiconductor substrate includes silicon.

Further, as shown in fig. 4B, an N-typesecond epitaxial layer 204 with a low doping concentration of the first conductivity type is grown on the first conductivity typefirst epitaxial layer 202 provided with the P-type pillardeep trench 203, wherein the thickness of the first conductivity typesecond epitaxial layer 204 is smaller than that of the first conductivity typefirst epitaxial layer 202.

Instep 22, as shown in fig. 4C, an oxide layer is grown on the surface of the first conductivity typesecond epitaxial layer 204 by an oxidation process, and a polysilicon layer is deposited on the oxide layer by L PCVD process, wherein the oxide layer may also be referred to as agate oxide layer 205.

Further, the polysilicon layer is exposed through a photolithography process, a region of the gate polycrystalline layer is defined, then the polysilicon layer and thegate oxide layer 205 on the top of the first conductive typesecond epitaxial layer 204 are removed through dry etching, the polysilicon layer and thegate oxide layer 205 which are not protected by the photoresist are removed, the first conductive typesecond epitaxial layer 204 corresponding to the source region is exposed, and then the photoresist is removed, so that the gate polycrystalline layer region is formed.

Instep 23 andstep 24, as shown in fig. 4D and 4E, a first P-type well implantation region is defined by a photolithography process, a first ion implantation of a dopant element is performed on the first conductivity typesecond epitaxial layer 204 to form a P-body region 207, and the dopant element is activated by an annealing process; defining N by photolithography⁺A source region 208 implantation region for forming a second conductivity type N on both sides of the P-body region 207 by performing a second ion implantation into the first conductivity typesecond epitaxial layer 204⁺Thesource region 208 is formed by an annealing process to activate the dopant elements.

It should be noted that the P-body region 207 formed by performing the first ion implantation is located right above the P-type pillardeep trench 203, and the width of the P-body region 207 is smaller than the width of the P-type pillardeep trench 203, that is, the distance between two adjacent P-body regions 207 is smaller than the distance between the P-type pillardeep trenches 203. Through the above process, the problem that in the prior art, the distance between the P-type pillardeep grooves 203 is relatively large due to the fact that the concentration of the P-type pillardeep grooves 203 is higher than that of the P-body region 207, namely the width of the P-body region 207 must be larger than that of the P-type pillardeep grooves 203, otherwise, the channel concentration is too high, and the starting voltage is difficult to control can be solved.

Instep 25, as shown in fig. 4F, an oxide layer is deposited over thepolysilicon gate 206 to form an insulating dielectric layer, wherein an insulatingoxide layer 209 extends from over thepolysilicon gate 206 to the top surface of the first conductivity typesecond epitaxial layer 204, wherein the first conductivity type second epitaxial layer is shownThe upper surface oflayer 204 represents portion N⁺A source region 208. And contact holes are formed in the regions of the upper surface of the first conductive-typesecond epitaxial layer 204 not covered by the insulatingoxide layer 209.

Further, as shown in fig. 4G, metal filling is performed over the contact hole and the insulatingoxide layer 209, forming ametal layer 210.

To sum up, the embodiment of the utility model provides a super junction type MOSFET device, this device includes: a P-type column deep groove, a first epitaxial layer, a second epitaxial layer, a P-body region and N⁺A source region; the P-type column deep groove is positioned in the first epitaxial layer, and the second epitaxial layer is positioned on the P-type column deep groove and the upper layer of the first epitaxial layer; the P-body region is positioned in the second epitaxial layer, the P-type column deep groove is positioned right below the P-body region, and the width of the P-body region is smaller than that of the P-type column deep groove; two of N⁺The source regions are respectively positioned at two sides of the P-body region. In the super junction type MOSFET device, a first epitaxial layer and a second epitaxial layer are sequentially formed in a multi-epitaxial layer injection mode, a P-type column deep groove is formed in the first epitaxial layer, a P-body area is formed in the second epitaxial layer, the P-body area in the second epitaxial layer can be completely positioned on the upper layer of the P-type column deep groove, the width of the P-body area is smaller than that of the P-type column deep groove, the distance between every two adjacent P-body areas is larger than that between every two adjacent P-type column deep grooves, and the structure can effectively reduce the size of a unit cell; further, if the distance between the P-type pillar deep grooves in the first epitaxial layer can be small enough, the distance between the P-body regions in the second epitaxial layer can also be adjusted by the process, so that the JFET region with low enough resistance can be obtained. The embodiment of the utility model provides a super junction type MOSFET device has solved and has received the restriction of P-body region width when the distance between the current P type post deep groove reduces, leads to the higher problem of resistance ratio in JFET district.

While the preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the appended claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (4)

1. A super junction type MOSFET device, comprising: a P-type column deep groove, a first epitaxial layer, a second epitaxial layer, a P-body region and N⁺A source region;

the P-type column deep groove is positioned in the first epitaxial layer, and the second epitaxial layer is positioned on the P-type column deep groove and the upper layer of the first epitaxial layer;

the P-body region is positioned in the second epitaxial layer, the P-type column deep groove is positioned right below the P-body region, and the width of the P-body region is smaller than that of the P-type column deep groove;

two of N⁺The source regions are respectively positioned at two sides of the P-body region.

2. The device of claim 1, further comprising a polysilicon gate and a gate oxide;

the gate oxide layer and the polysilicon gate are sequentially arranged on the second epitaxial layer and extend to the P-body region and the N⁺An upper layer of the source region.

3. The device of claim 2, further comprising an insulating oxide layer and a metal layer;

the insulation oxide layer is positioned on the upper layer of the polysilicon gate, and part of the insulation oxide layer extends out of the polysilicon gate and is positioned on part of the N⁺An upper layer of the source region;

the metal layer is arranged on the upper layer of the insulating oxide layer, and part of the metal layer extends out of the insulating oxide layerPart of said N⁺A source region and a portion of the upper layer of the P-body region.

4. The device of claim 1, further comprising a substrate layer directly below the first epitaxial layer.

Images