CN210518245U - Startup and shutdown circuit and startup and shutdown system - Google Patents

Abstract

The utility model relates to a switching on and shutting down circuit and switching on and shutting down system, the switching on and shutting down circuit includes: MOS pipe K1, resistor R1, resistor R2, resistor R3, resistor R4, capacitor C1, capacitor C2, capacitor C3, triode K2, diode D1 and diode D2; source electrode and resistance R1's of MOS pipe K1 one end, electric capacity C1's one end, power end VBAT all connect, MOS pipe K1's grid and resistance R1's the other end, electric capacity C1's the other end, resistance R2's one end is all connected, MOS pipe K1's drain electrode and load end SWBAT, electric capacity C2's one end is all connected, electric capacity C2's the other end is connected to ground, the utility model discloses an on-off circuit possesses the time delay control that falls down, makes the load parameter can be preserved when shutting down, and the risk of burning out the MOS pipe when can reducing the big current of start-up, simple structure, low cost, volume are less, can be extensive use on terminal and other load equipment.

Description

Startup and shutdown circuit and startup and shutdown system

Technical Field

The utility model belongs to the technical field of the switching on and shutting down of electron load, in particular to switching on and shutting down circuit and switching on and shutting down system.

Background

In terminal load and consumer electronic load applications, a switching on/off circuit for realizing the switching on/off function is indispensable. Some of the integrated ICs realize the functions of power-off and power-on through key-press time length. For example, the automatic start-up is carried out by pressing 3' for a long time; long press 6 "load auto-off, etc. The method needs to add the time delay of the integrated IC identification key, and increases the cost of the terminal and the volume of the PCB. Therefore, a circuit capable of realizing power-on and power-off through discrete components is a demand of the current cost difference strategy. In addition, in terminal load and consumer electronic load applications, unexpected shutdown conditions such as sudden power failure and misoperation may be encountered. Therefore, the power on/off circuit needs to have a time delay control so that the load parameter can be saved when the power off circuit is turned off. In the prior art, time delay, namely startup delay, is set by setting component parameters of an automatic startup circuit, and automatic startup delay control is mainly realized, but the control delay during shutdown is not available; or the power-on delay and the power-off delay can be realized, but the circuit design is more complex, the related devices are more, and the cost of the single board is increased.

In summary, there is a need in the industry to develop a discrete component circuit that has a simple structure, low cost, and a small size, and can implement on/off delay control.

SUMMERY OF THE UTILITY MODEL

In order to overcome the defects existing in the prior art, the utility model provides a startup and shutdown circuit and startup and shutdown system.

The utility model provides a technical scheme that its technical problem adopted is:

a power on/off circuit, comprising: MOS pipe K1, resistor R1, resistor R2, resistor R3, resistor R4, capacitor C1, capacitor C2, capacitor C3, triode K2, diode D1 and diode D2; the source of the MOS transistor K1 is connected with one end of a resistor R1, one end of a capacitor C1 and a power supply terminal VBAT, the gate of the MOS transistor K1 is connected with the other end of a resistor R1, the other end of the capacitor C1 and one end of a resistor R2, the drain of the MOS transistor K1 is connected with one end of a load terminal SWBAT and one end of a capacitor C2, the other end of the capacitor C2 is connected with the ground, the other end of the resistor R2 is connected with the ground through a capacitor C3, the base of a triode K2 is connected with the ground through a resistor R3, the base of a triode K2 is further connected with the PS _ ON/OFF signal terminal of the CPU, the emitter of a triode K2 is connected with the ground, the collector of a triode K2 is connected with the other end of the resistor R2 and the anode of a diode D2, the cathode of a diode D2 is connected with the PWR _ SW signal terminal, the PWR _ SW signal terminal is connected with the anode of a switching device, the anode of a diode D1 is connected with the, the cathode of the diode D1 is also connected to a power supply terminal VBAT through a resistor R4.

Preferably, the switching device is a key switch or a rotary switch.

A switching system based on the switching circuit comprises: the power supply comprises a switching circuit, a power supply, a load, a switching device and a CPU; the power supply outputs voltage to the switching circuit, the switching circuit is connected with the switching device and the CPU, and the switching circuit outputs voltage to the load after being switched on.

Preferably, the power supply is a battery.

Preferably, the model of the CPU is OMAPL 138.

The utility model has the advantages that:

the triode of the NPN type of this scheme is as switch circuit's power down time delay control component, combines the application of switch circuit, has not only improved the power down time delay control of switch circuit, makes load parameter can save when the shutdown, through at MOS pipe input end design resistance R1, electric capacity C1, and then just reduces the risk of burning out the MOS pipe when the heavy current of start, in addition the utility model discloses a switch circuit simple structure, low cost, volume are less, can extensive application on terminal load.

Drawings

The present invention will be further explained with reference to the drawings and examples.

Fig. 1 is a circuit diagram of the switching on/off circuit of the present invention.

Fig. 2 is a schematic block diagram of the power on/off system of the present invention;

Detailed Description

The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic drawings and illustrate the basic structure of the present invention only in a schematic manner, and thus show only the components related to the present invention.

Referring to fig. 1, a power on/off circuit includes: MOS pipe K1, resistor R1, resistor R2, resistor R3, resistor R4, capacitor C1, capacitor C2, capacitor C3, triode K2, diode D1 and diode D2; a source (terminal 2) of a MOS transistor K1 is connected with one end of a resistor R1, one end of a capacitor C1 and a power supply terminal VBAT, a gate of the MOS transistor K1 is connected with the other end of a resistor R1, the other end of the capacitor C1 and one end of a resistor R2, a drain (terminal 3) of the MOS transistor K1 is connected with one ends of a load terminal SWBAT and a capacitor C2, the other end of the capacitor C2 is connected with the ground, the other end of the resistor R2 is connected with the ground through a capacitor C3, a base of a transistor K2 is connected with the ground through a resistor R3, a base of the transistor K2 is further connected with a PS _ ON/OFF signal terminal of the CPU, an emitter of the transistor K2 is connected with the ground, a collector of the transistor K2 is connected with the other end of the resistor R2 and an anode of a diode D2, a cathode of a diode D2 is connected with a PWR _ SW signal terminal, a PWR _ SW signal terminal is connected with a switching device, an anode of a diode D1 is connected with a cathode of a signal terminal 686, the cathode of the diode D1 is also connected to a power supply terminal VBAT through a resistor R4.

Referring to fig. 2, a power on/off system based on the power on/off circuit includes: the power supply comprises a switching circuit, a power supply, a load, a switching device and a CPU; the power supply outputs voltage to the switching circuit, the switching circuit is connected with the switching device and the CPU, and the switching circuit outputs voltage to the load after being switched on. VBAT is an input terminal of a power supply, such as a battery, and SWBAT is a power supply terminal of a device (load), which is a power supply terminal after being turned on. The resistor R4 is pulled up to the VBAT end and keeps high level at the moment, so that the CPU detects the level.

In this embodiment, the power supply is a battery.

In this embodiment, the CPU is OMAPL 138.

When the MOS tube K1 is conducted, the power supply supplies power to the load, and the load is electrified and started. The resistor R1 and the capacitor C1 can effectively prevent the MOS transistor K1 from being burnt out due to a large current load when the MOS transistor K1 is turned on. And the transistor K2 controls the MOS transistor K1 to turn off and on. When the PS _ ON/OFF signal output by the CPU is in a high level, the NPN triode K2 is conducted, so that the MOS tube is conducted; conversely, when the PS _ ON/OFF signal is low, the NPN transistor K2 is turned OFF. The diodes D1 and D2 effectively realize the one-way conduction characteristic, when the voltage of the battery is far larger than the withstand voltage value of the CPU, on one hand, the high level of the CPU is realized through the one-way conduction performance of the diodes D1 and D2, on the other hand, the CPU can be protected from being damaged, and the PWE-S signal end of the GPIO pin of the CPU is configured as input and used for detecting the state of the external level (PWR _ SW signal end).

When the switch device is a knob switch, the startup and shutdown circuit of the scheme has the following startup principle:

when a user rotates the knob switch to a power-on gear, the PWR _ SW signal end is in a continuous low level, the PWR _ S signal end of the CPU detects that the PWR _ SW signal end is low, and the MOS tube K1 is switched on, the power supply supplies power to the load, and the load starts to work after being electrified, so that the power-on is successful.

When the switch device is a knob switch, the principle of the on-off circuit for realizing the shutdown is as follows:

when a user rotates the knob switch to a power-OFF gear, the voltage state of the PWR _ SW signal end is switched from low level to high level, and due to the unidirectional conduction characteristic of the diode D1, the PWR _ S signal end of the CPU detects that the low level of the PWR _ SW signal end disappears, the PS _ ON/OFF signal end of the CPU outputs low level, the triode K2 is switched ON, so that the MOS tube K1 is cut OFF, and the load is powered OFF. And (6) successfully shutting down. When the user rotates the knob switch to the shutdown gear, the load is not directly powered off, but is identified by the CPU. Therefore, in the action process of the CPU, the CPU can firstly save the parameters to achieve the function of shutdown delay. The knob switch can also have other functions concurrently, for example can control the volume size, and knob switch triggers MOS pipe KI and switches on, and equipment power supply is opened, and CPU starts. When the power-off device is turned off, the MOS tube is not immediately turned off by the software processing of the device through operating the knob switch, and the time delay is used for ensuring that the terminal device stores various parameters, so that the next power-on process is not required to be newly set, the user experience is increased, the MOS tube KI is turned off, and the power supply of the device is cut off. The switching circuit has a time delay function, an integrated IC is not needed, discrete components are low in cost, the structure size is small, and the switching circuit is the best choice for terminal equipment.

When the switch device is a key switch, the startup and shutdown circuit of the scheme has the following startup principle:

the user presses the key switch for a long time (for example, presses 3 ″) for a long time, the PWR _ SW signal end in the key is at a low level, after the key is pressed, the PWR _ SW signal end is at a high level, the PWR _ S signal end of the CPU detects that the low level of the PWR _ SW signal end reaches the preset time, the PS _ ON/OFF signal end of the CPU outputs the high level, the triode K2 is turned ON, so that when the MOS transistor K1 is turned ON, the power supply supplies power to the load, the load is turned ON to start working, and the power is turned ON successfully.

When the switching device is a key switch, the principle of the power-on and power-off circuit of the scheme for realizing power-off is as follows:

when the load is in a power-ON state, a user presses the key switch for a preset time (for example, presses 3 ") for a long time, the PWR _ SW signal end in the key is at a low level, after the key is pressed, the PWR _ SW signal end is at a high level, the PWR _ S signal end of the CPU detects that the low level of the PWR _ SW signal end reaches the preset time, the PS _ ON/OFF signal end of the CPU outputs a low level, the triode K2 is cut OFF, and the MOS transistor K1 is cut OFF, so that the load is powered OFF. And (6) successfully shutting down. After the user presses the key switch for a long time, the load is not directly powered off, but is recognized by the CPU. Therefore, in the action process of the CPU, the CPU can firstly save the parameters to achieve the function of shutdown delay.

To sum up, the startup and shutdown circuit of this scheme can the different switches of adaptation, and the hardware scheme need not to change, only needs to change software, and cost reduction relatively speaking satisfies different users' demand. And AND gate logic is realized through the diode D1 and the diode D2, so that the number of IO ports is saved on one hand, and detection is realized on the other hand to control the on-off state. In addition, when the power-off device is shut down, the power-down parameter storage function of the device (load) can be realized. The power-off state control method comprises the steps that the power-off state control method can be controlled through the GPIO of the CPU, the CPU starts to store data such as parameters after detecting a power-off command, and after the power-off command is finished, the state of the GPIO is controlled, so that the function of storing power-off parameters is achieved. When the power-on device is started, in order to prevent the MOS transistor K1 from being burnt out by large-current surge, the capacitor C1 and the resistor R1 are arranged between the source electrode and the grid electrode, surge current impact is reduced, and the risk of burning out the MOS transistor K1 is further reduced.

In light of the foregoing, it will be apparent to those skilled in the art from this disclosure that various changes and modifications can be made without departing from the spirit and scope of the invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.

Claims (5)

1. A power on/off circuit, comprising: MOS pipe K1, resistor R1, resistor R2, resistor R3, resistor R4, capacitor C1, capacitor C2, capacitor C3, triode K2, diode D1 and diode D2;

the source of the MOS transistor K1 is connected with one end of a resistor R1, one end of a capacitor C1 and a power supply terminal VBAT, the gate of the MOS transistor K1 is connected with the other end of a resistor R1, the other end of the capacitor C1 and one end of a resistor R2, the drain of the MOS transistor K1 is connected with one end of a load terminal SWBAT and one end of a capacitor C2, the other end of the capacitor C2 is connected with the ground, the other end of the resistor R2 is connected with the ground through a capacitor C3, the base of a triode K2 is connected with the ground through a resistor R3, the base of a triode K2 is further connected with the PS _ ON/OFF signal terminal of the CPU, the emitter of a triode K2 is connected with the ground, the collector of a triode K2 is connected with the other end of the resistor R2 and the anode of a diode D2, the cathode of a diode D2 is connected with the PWR _ SW signal terminal, the PWR _ SW signal terminal is connected with the anode of a switching device, the anode of a diode D1 is connected with the, the cathode of the diode D1 is also connected to a power supply terminal VBAT through a resistor R4.

2. The on-off circuit of claim 1, wherein the switching device is a key switch or a rotary switch.

3. A switching system based on the switching circuit according to any one of claims 1-2, comprising: the power supply comprises a switching circuit, a power supply, a load, a switching device and a CPU;

the power supply outputs voltage to the switching circuit, the switching circuit is connected with the switching device and the CPU, and the switching circuit outputs voltage to the load after being switched on.

4. The switching system of claim 3, wherein the power supply is a battery.

5. The on-off system of claim 3, wherein the CPU is of the OMAPL138 type.

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