SUMMERY OF THE UTILITY MODEL
In view of this, for solving the above problem, the utility model provides a high-voltage digital audio power amplifier system, technical scheme is as follows:
a high-voltage digital audio power amplifier system comprises: the system comprises a first subsystem, a second subsystem, a first feedback module, a second feedback module and a current source adjusting module;
the first subsystem includes: the output end of the first current source module is connected with the first input end of the first power amplifier loop, the input end of the first current source module is used as the signal input end of the first subsystem and used for receiving a PWMP signal, and the output end of the first power amplifier loop is used as the output end of the first subsystem;
the second subsystem comprises: the output end of the second current source module is connected with the first input end of the second power amplifier loop, the input end of the second current source module is used as the signal input end of the second subsystem and used for receiving PWMN signals, and the output end of the second power amplifier loop is used as the output end of the second subsystem;
one end of the first feedback module is connected with a first input end of the first power amplifier loop, and the other end of the first feedback module is connected with an output end of the first power amplifier loop;
one end of the second feedback module is connected with the first input end of the second power amplifier loop, and the other end of the second feedback module is connected with the output end of the second power amplifier loop;
the first end of the current source adjusting module is connected with the first input end of the first power amplifier loop, the second end of the current source adjusting module is connected with the first input end of the second power amplifier loop, the third end of the current source adjusting module is connected with the power supply voltage end, the fourth end of the current source adjusting module is connected with the voltage input end, the fifth end of the current source adjusting module is used for receiving a control signal, and the sixth end of the current source adjusting module is grounded;
the current source adjusting module is used for providing current for the first subsystem and the second subsystem so as to improve the output power of the high-voltage digital audio power amplifier system, and the control signal is used for controlling the current source adjusting module to be in different working states so as to enable the resistors of the first subsystem and the second subsystem to be matched;
the periods of the control signal, the PWMP signal and the PWMN signal are the same.
Preferably, in the high-voltage digital audio power amplifier system, the first feedback module includes: a first resistor;
one end of the first resistor is connected with a first input end of the first power amplifier loop, and the other end of the first resistor is connected with an output end of the first power amplifier loop;
the second feedback module comprises: a second resistor;
one end of the second resistor is connected with a first input end of the second power amplifier loop, and the other end of the second resistor is connected with an output end of the second power amplifier loop.
Preferably, in the high-voltage digital audio power amplifier system, the current source adjusting module includes: the first field effect transistor, the second field effect transistor, the third field effect transistor, the fourth field effect transistor, the fifth field effect transistor, the sixth field effect transistor, the seventh field effect transistor, the operational amplifier and the third resistor;
the inverting input end of the operational amplifier is connected with the power supply voltage end, the non-inverting input end of the operational amplifier is connected with the first end of the third resistor, and the second end of the third resistor is connected with the voltage input end;
the drain electrode of the first field effect transistor is connected with the first end of the third resistor;
the drain electrode of the second field effect transistor is respectively connected with the source electrodes of the fourth field effect transistor and the fifth field effect transistor;
the drain electrode of the third field effect transistor is respectively connected with the source electrodes of the sixth field effect transistor and the seventh field effect transistor;
the grid electrode of the first field effect tube, the grid electrode of the second field effect tube and the grid electrode of the third field effect tube are all connected with the output end of the operational amplifier;
the source electrode of the first field effect transistor, the source electrode of the second field effect transistor and the source electrode of the third field effect transistor are all connected with the ground;
the drain electrode of the fourth field effect transistor and the drain electrode of the seventh field effect transistor are both connected with the first input end of the first power amplifier loop;
the drain electrode of the fifth field effect transistor and the drain electrode of the sixth field effect transistor are both connected with the first input end of the second power amplifier loop;
and the grids of the fourth field effect transistor, the fifth field effect transistor, the sixth field effect transistor and the seventh field effect transistor receive the control signals.
Preferably, in the high-voltage digital audio power amplifier system, the resistance value of the third resistor is twice the resistance value of the first resistor.
Preferably, in the high-voltage digital audio power amplifier system, the first field-effect transistor, the second field-effect transistor and the third field-effect transistor are all N-type field-effect transistors.
Preferably, in the high-voltage digital audio power amplifier system, the width-to-length ratios of the first field-effect transistor, the second field-effect transistor and the third field-effect transistor are the same.
Preferably, in the above high-voltage digital audio power amplifier system, the high-voltage digital audio power amplifier system further includes: a common mode voltage generating module;
and the second input end of the first power amplifier loop and the second input end of the second power amplifier loop are both connected with the output end of the common-mode voltage generation module.
Preferably, in the high-voltage digital audio power amplifier system, the common-mode voltage generating module includes: a fourth resistor, a fifth resistor, a sixth resistor and a capacitor;
the first end of the fourth resistor is connected with the power supply voltage end, the second end of the fourth resistor is connected with the first end of the fifth resistor, and the second end of the fifth resistor is connected with the ground;
a first end of the sixth resistor is connected with a second end of the fourth resistor, a second end of the sixth resistor is connected with a first end of the capacitor, and a second end of the capacitor is connected with the ground;
and the connection node of the sixth resistor and the capacitor is used as the output end of the common-mode voltage generation module.
Preferably, in the high-voltage digital audio power amplifier system, a resistance value of the fourth resistor is the same as a resistance value of the fifth resistor.
Preferably, in the high-voltage digital audio power amplifier system, the voltage of the output end of the common-mode voltage generation module is half of the voltage supply end of the power supply.
Compared with the prior art, the utility model discloses the beneficial effect who realizes does:
the utility model provides a pair of high pressure digital audio power amplifier system is through setting up current source adjusting module, at first be used for doing first subsystem with the second subsystem provides the electric current, in order to improve high pressure digital audio power amplifier system's output, so that high pressure digital audio power amplifier system work is in higher voltage range, and then improves high pressure digital audio power amplifier system's output.
And secondly, the control signal is received to control the current source adjusting module to be in different working states so as to match the resistances of the first subsystem and the second subsystem, thereby improving the power supply rejection ratio of the digital audio power amplification system and eliminating the noise on the loudspeaker.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention is described in detail with reference to the accompanying drawings and the detailed description.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a high-voltage digital audio power amplifier system provided by an embodiment of the present invention, which is used to convert a PWM signal processed by a digital module into an analog signal, the high-voltage digital audio power amplifier system includes: the system comprises a first subsystem, a second subsystem, a first feedback module 13, a second feedback module 17 and a current source adjusting module 14;
the first subsystem includes: a first current source module 11 and a first power amplifier loop 12, where an output end of the first current source module 11 is connected to a first input end Vip of the first power amplifier loop 12, an input end of the first current source module 11 serves as a signal input end of the first subsystem, and is configured to receive a PWMP signal, and an output end of the first power amplifier loop 12 serves as an output end VOP of the first subsystem;
the second subsystem comprises: a second current source module 15 and a second power amplifier loop 16, where an output terminal of the second current source module 15 is connected to a first input terminal Vin of the second power amplifier loop 16, an input terminal of the second current source module 15 is used as a signal input terminal of the second subsystem and is configured to receive a PWMN signal, and an output terminal of the second power amplifier loop 16 is used as an output terminal VON of the second subsystem;
one end of the first feedback module 13 is connected to the first input end Vip of the first power amplifier loop 12, and the other end is connected to the output end of the first power amplifier loop 12;
one end of the second feedback module 17 is connected to the first input end Vin of the second power amplifier loop 16, and the other end is connected to the output end of the second power amplifier loop 16;
a first end of the current source adjusting module 14 is connected to a first input end Vip of the first power amplifier loop 12, a second end is connected to a first input end Vin of the second power amplifier loop 16, a third end is connected to a power supply voltage end VDD, a fourth end is connected to a voltage input end PVDD, a fifth end is configured to receive a control signal SW, and a sixth end is connected to ground;
the current source adjusting module 14 is configured to provide current for the first subsystem and the second subsystem to increase output power of the high-voltage digital audio power amplifier system, and the control signal SW is configured to control the current source adjusting module 14 to be in different working states, so that resistances of the first subsystem and the second subsystem are matched;
the periods of the control signal SW, the PWMP signal and the PWMN signal are the same.
According to the above description, the utility model provides a pair of high-pressure digital audio power amplifier system is through setting up current source adjusting module, at first be used for doing first subsystem with the second subsystem provides the electric current, in order to improve high-pressure digital audio power amplifier system's output, so that high-pressure digital audio power amplifier system work is in higher voltage range, and then improves high-pressure digital audio power amplifier system's output.
And secondly, the control signal is received to control the current source adjusting module to be in different working states so as to match the resistances of the first subsystem and the second subsystem, thereby improving the power supply rejection ratio of the digital audio power amplification system and eliminating the noise on the loudspeaker.
Further, as shown in fig. 1, the high-voltage digital audio power amplifier system further includes: a common mode voltage generating module 18;
a second input terminal of the first power amplifier loop 12 and a second input terminal of the second power amplifier loop 16 are both connected to an output terminal VREF of the common mode voltage generation module 18.
In this embodiment, the common mode voltage generating module 18 is configured to generate a common mode voltage signal for maintaining stability of the output signals of the first current source module 11 and the second current source module 12.
The voltage at the output end of the common mode voltage generating module 18 is half of the voltage at the power supply end VDD.
Further, referring to fig. 2, fig. 2 is another schematic structural diagram of the high-voltage digital audio power amplifier system according to an embodiment of the present invention, where the first current source module 11 includes a first current source IDAC1, a second current source IDAC2, a switch a, and a switch B.
The input end of the first current source IDAC1 is connected to the power supply voltage end VDD, the output end of the first current source IDAC1 is connected to the input end of the switch a, the output end of the switch a is connected to the input end of the switch B, the output end of the switch B is connected to ground through the second current source IDAC2, and the control ends of the switch a and the switch B are used as the input ends of the first current source module 11 and are used for receiving PWMP signals.
Further, as shown in fig. 2, the first power amplifier loop 12 includes a first operational amplifier 21, a power amplifier loop driving module 23, a first capacitor C1, a field effect transistor P1, and a field effect transistor N1;
the inverting input end of the first operational amplifier 21 is connected to the output end of the first current source module 11, the non-inverting input end of the first operational amplifier 21 is connected to the output end VREF of the common-mode voltage generation module 18, the output end of the first operational amplifier 21 is connected to the input end of the power amplifier loop driving module 23, the first output end of the power amplifier loop driving module 23 is connected to the gate of the fet P1, and the second output end of the power amplifier loop driving module 23 is connected to the gate of the fet N1.
The source electrode of the field effect transistor P1 is connected with a voltage input end PVDD, the drain electrode of the field effect transistor P1 is connected with the drain electrode of the field effect transistor N1, the source electrode of the field effect transistor N1 is connected with the ground, and the connection node of the field effect transistor P1 and the field effect transistor N1 serves as an output end VOP of the first power amplifier loop.
A first end of the first capacitor C1 is connected to the output end of the first operational amplifier 21, and a second end is connected to the inverting input end of the first operational amplifier 21.
Further, as shown in fig. 2, the second current source module 15 includes a third current source IDAC3, a fourth current source IDAC4, a switch C and a switch D.
The input end of the third current source IDAC3 is connected to the power supply voltage end VDD, the output end of the third current source IDAC3 is connected to the input end of the switch C, the output end of the switch C is connected to the input end of the switch D, the output end of the switch D is connected to ground through the fourth current source IDAC4, and the control ends of the switch C and the switch D are used as the input ends of the second current source module 15 and are used for receiving PWMN signals.
Further, as shown in fig. 2, the second power amplifier loop 16 includes a second operational amplifier 22, a power amplifier loop driving module 24, a second capacitor C2, a field effect transistor P2, and a field effect transistor N2;
the inverting input end of the second operational amplifier 22 is connected to the output end of the second current source module 16, the non-inverting input end of the second operational amplifier 22 is connected to the output end VREF of the common-mode voltage generation module 18, the output end of the second operational amplifier 22 is connected to the input end of the power amplifier loop driving module 24, the first output end of the power amplifier loop driving module 24 is connected to the gate of the fet P2, and the second output end of the power amplifier loop driving module 24 is connected to the gate of the fet N2.
The source electrode of the field effect transistor P2 is connected with a voltage input end PVDD, the drain electrode of the field effect transistor P2 is connected with the drain electrode of the field effect transistor N2, the source electrode of the field effect transistor N2 is connected with ground, and the connection node of the field effect transistor P2 and the field effect transistor N2 serves as the output end VON of the second power amplifier loop.
A first end of the second capacitor C2 is connected to the output end of the second operational amplifier 22, and a second end is connected to the inverting input end of the second operational amplifier 22.
Further, as shown in fig. 2, the first feedback module 13 includes: a first resistor Rfb 1;
one end of the first resistor Rfb1 is connected to the first input end of the first power amplifier loop 12, and the other end of the first resistor Rfb1 is connected to the output end of the first power amplifier loop 12;
the second feedback module 16 includes: a second resistor Rfb 2;
one end of the second resistor Rfb2 is connected to the first input end of the second power amplifier loop 16, and the other end is connected to the output end of the second power amplifier loop 16.
Further, referring to fig. 3, fig. 3 is a schematic structural diagram of a current source adjusting module provided in an embodiment of the present invention, where the current source adjusting module 14 includes: a first field-effect tube M1, a second field-effect tube M2, a third field-effect tube M3, a fourth field-effect tube M4, a fifth field-effect tube M5, a sixth field-effect tube M6, a seventh field-effect tube M7, an operational amplifier 31 and a third resistor R3;
an inverting input terminal of the operational amplifier 31 is connected to the power supply voltage terminal VDD, a non-inverting input terminal of the operational amplifier 31 is connected to a first terminal of the third resistor R3, and a second terminal of the third resistor R3 is connected to the voltage input terminal PVDD;
the drain electrode of the first field effect transistor M1 is connected with the first end of the third resistor R3;
the drain electrode of the second field effect transistor M2 is respectively connected with the source electrodes of the fourth field effect transistor M4 and the fifth field effect transistor M5;
the drain electrode of the third field effect transistor M3 is respectively connected with the source electrodes of the sixth field effect transistor M6 and the seventh field effect transistor M7;
the grid electrode of the first field effect transistor M1, the grid electrode of the second field effect transistor M2 and the grid electrode of the third field effect transistor M3 are all connected with the output end of the operational amplifier 31;
the source electrode of the first field effect transistor M1, the source electrode of the second field effect transistor M2 and the source electrode of the third field effect transistor M3 are all connected to ground;
the drain electrode of the fourth field effect transistor M4 and the drain electrode of the seventh field effect transistor M7 are both connected with the first input end Vip of the first power amplifier loop 12;
the drain electrode of the fifth field effect transistor M5 and the drain electrode of the sixth field effect transistor M6 are both connected to the first input terminal Vin of the second power amplifier loop 16;
the gates of the fourth fet M4, the fifth fet M5, the sixth fet M6, and the seventh fet M7 all receive the control signal SW.
In this embodiment, the control signal SW includes: a first control signal SW1 and a second control signal SW 2;
the gate of the fourth field effect transistor M4 and the gate of the sixth field effect transistor M6 are used for receiving the first control signal SW 1;
the gate of the fifth field effect transistor M5 and the gate of the sixth field effect transistor M6 are used for receiving the second control signal SW 2;
it should be noted that, when the first control signal SW1 is at a high level, the second control signal SW2 is at a low level; when the first control signal SW1 is low, the second control signal SW2 is high.
That is, when the fourth fet M4 and the sixth fet M6 are in the on state, the fifth fet M5 and the seventh fet M7 are in the off state;
when the fifth fet M5 and the seventh fet M7 are in the on state, the fourth fet M4 and the sixth fet M6 are in the off state.
Further, the resistance value of the third resistor R3 is twice the resistance value of the first resistor Rfb 1.
The first field effect transistor M1, the second field effect transistor M2 and the third field effect transistor M3 are all N-type field effect transistors.
The width-to-length ratios of the first field effect transistor M1, the second field effect transistor M2 and the third field effect transistor M3 are the same.
Further, referring to fig. 4, fig. 4 is a schematic structural diagram of a common mode voltage generating module according to an embodiment of the present invention, where the common mode voltage generating module 18 includes: a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a capacitor C;
a first end of the fourth resistor R4 is connected to the power supply voltage terminal PVDD, a second end of the fourth resistor R4 is connected to a first end of the fifth resistor R5, and a second end of the fifth resistor R5 is connected to ground;
a first end of the sixth resistor R6 is connected to a second end of the fourth resistor R4, a second end of the sixth resistor R6 is connected to a first end of the capacitor C, and a second end of the capacitor C is connected to ground;
the connection node of the sixth resistor R6 and the capacitor C serves as the output terminal VREF of the common mode voltage generation module 18.
Further, the resistance of the fourth resistor R4 is the same as the resistance of the fifth resistor R5.
Based on the high-voltage digital audio power amplifier system, when the voltage VREF at the output end of the common-mode voltage generation module 18 is half of the voltage VDD at the power supply end, the high-voltage digital audio power amplifier system can normally work.
Since the operation principle of the first subsystem and the second subsystem is the same, the operation principle of the first subsystem will be explained below.
Since the width-to-length ratios of the first FET M1, the second FET M2 and the third FET M3 are the same, the second FET has a high breakdown voltageCurrent of (I)_M2And current I of the third field effect transistor_M3The same is true.
If the fourth fet M4, the fifth fet M5, the sixth fet M6 and the seventh fet M7 are not provided, the second fet M2 draws or sinks current from the first input terminal Vip of the first power amplifier loop 12, the third fet M3 draws or sinks current from the first input terminal Vin of the second power amplifier loop 16,
the second fet M2 will be described as drawing a current.
That is, when VOP is equal to "1", the output VOP of the first subsystem charges the first capacitor C1 through the first resistor Rfb1 and the current source adjusting module 14, and the current charged by the first capacitor is labeled as IRfb1_1；
Further, as can be seen from FIGS. 2 and 3,
wherein, ISNK1Representing the current drawn by the current source regulation module 14 from the first input Vip of the first power amplifier loop 12.
Further, since the output voltage VREF of the common mode voltage generating module 18 is half of the voltage supply terminal VDD, it follows that:
so as to obtain the product with the advantages of,
however, in the actual manufacturing process, the second fet M2 and the third fet M3 inevitably exist due to the manufacturing processIn the case of deviation, the current I of the second field effect transistor M2 is also caused_M2And current I of the third field effect transistor M3_M3If the currents are not identical, the current extracted from the first power amplifier loop 12 through the path of the second fet M2 and the current extracted from the second power amplifier loop 16 through the path of the third fet M3 are not identical, and therefore the gains of the first subsystem and the second subsystem are not identical, which results in poor suppression capability for power supply fluctuation interference and the like, i.e., the power supply rejection ratio PSRR of the high-voltage digital audio power amplifier system is degraded.
Wherein, since the resistance value of the third resistor R3 is twice as large as that of the first resistor Rfb1, that is,
R3＝2Rfb1
further, as can be seen from the circuit diagram shown in fig. 3,
wherein,representing the error factor of the second fet,representing the error factor of the third fet.
In order to solve the above problem, the embodiment of the present invention provides a current source adjusting module 14 that uses the second fet M2 and the third fet M3 by switching in different PWM periods.
For example, when the first control signal SW1 is at a high level and the second control signal SW2 is at a low level, the second fet M2 is connected to the first input terminal Vip of the first power amplifier loop 12 through the fourth fet M4, and the third fet M3 is connected to the first input terminal Vin of the second power amplifier loop 16 through the sixth fet M6;
when the first control signal SW1 is at a low level and the second control signal SW2 is at a high level, the second fet M2 is connected to the first input terminal Vin of the second power amplifier loop 16 through the fifth fet M5, and the third fet M3 is connected to the first input terminal Vip of the first power amplifier loop 12 through the seventh fet M7.
That is, the current source adjusting module 14 draws the current I from the first input terminal Vip of the first power amplifier loop 12 and the first input terminal Vin of the second power amplifier loop 16SNK1And ISNK2Are all (I)_M2+IM_)/3And 2, the currents are further the same, and the problem of PSRR performance reduction caused by non-rational factors such as manufacturing process mismatch is solved.
Wherein,
since the output end VOP of the first subsystem charges and discharges the first capacitor C1 through the first resistor Rfb1 and the current source adjusting module at the same current value, which is designated as IRfb1Therefore, it can be seen that,
the finishing agent can be obtained by finishing,
furthermore, by analyzing the relationship between the input duty ratio and the output signal, it can be found that, referring to fig. 5, fig. 5 is a schematic waveform diagram of the charging and discharging of the first capacitor provided by the embodiment of the present invention, the charging and discharging of the first capacitor C1 in one PWMP period is divided into 4 stages.
At stage T1: PWMP is "1", and VOP is "1", and is high, the first current source IDAC1 charges the first capacitor C1, the output VOP of the first subsystem charges the first capacitor C1 through the first resistor Rfb1 and the current source adjusting module 14, and the current of the first capacitor C1 is:
IC1_T1＝IDAC+IRfb1
at stage T2: PWMP is "1", and VOP is "0", and is low, the first current source IDAC1 charges the first capacitor C1, the output VOP of the first subsystem discharges the first capacitor C1 through the first resistor Rfb1 and the current source adjusting module 14, and the current of the first capacitor C1 is:
IC1_T2＝IDAC-IRfb1
at stage T3: PWMP is "0", and VOP is "0", and is low, the second current source IDAC2 discharges the first capacitor C1, the output VOP of the first subsystem discharges the first capacitor C1 through the first resistor Rfb1 and the current source adjusting module 14, and the current of the first capacitor C1 is:
IC1_T3＝-IDAC-IRfb1
at stage T4: PWMP is "0", and is low, VOP is "1", and is high, the second current source IDAC2 discharges the first capacitor C1, the output VOP of the first subsystem charges the first capacitor C1 through the first resistor Rfb1 and the current source adjusting module 14, and the current of the first capacitor C1 is:
IC1_T4＝-IDAC+IRfb1
since the charge and discharge of the first capacitor C1 are balanced during normal operation of the first subsystem, i.e.,
IC1_T1×t1+IC1_T2×t2＝-IC1_T3×t3-IC1_T4×t4
wherein t1, t2, t3 and t4 are respectively the time in each stage, IDACIs the current of the first current source IDAC1 and the second current source IDAC 2.
By working out the above formula, it can be obtained,
IDAC×(t1+t2)-IDAC×(t3+t4)＝IRfb1×(t2+t3)-IRfb1×(t1+t4)
wherein, t1+ t2 ═ DIN×T，t3+t4＝(1-DIN)×T，t1+t4＝DOUT×T，t2+t3＝(1-DOUT)×T。
Wherein D isINDuty cycle of PWMP, DOUTFor the duty cycle of VOP, T is the period of PWMP and VOP.
The finishing agent can be obtained by finishing,
in this way, it can be seen that,
then the output voltage VOP of the first subsystem is:
VOP＝DOUT×PVDD
that is to say that the first and second electrodes,
from the above formula, the VOP is one or moreIs a common mode point, 50% input duty cycle DINA central signal.
Similarly, the output voltage VON of the second subsystem is known, and is not described herein again.
Then, the total output voltage V of the digital audio power amplifier systemOUTIn order to realize the purpose,
VOUT＝VOP-VON
that is to say that the first and second electrodes,
therefore, the gain of the high-voltage digital audio power amplification system is as follows
The utility model provides a pair of high pressure digital audio power amplifier system is through setting up current source adjusting module, at first be used for doing first subsystem with the second subsystem provides the electric current, in order to improve high pressure digital audio power amplifier system's output, so that high pressure digital audio power amplifier system work is in higher voltage range, and then improves high pressure digital audio power amplifier system's output.
And secondly, the control signal is received to control the current source adjusting module to be in different working states so as to match the resistances of the first subsystem and the second subsystem, so that the gains of the first subsystem and the second subsystem are equal, and further the power supply rejection ratio of the digital audio power amplification system is improved so as to eliminate the noise on the loudspeaker.
The above detailed description is made on the high-voltage digital audio power amplifier system provided by the present invention, and the specific examples are applied herein to explain the principles and embodiments of the present invention, and the description of the above embodiments is only used to help understanding the method and core ideas of the present invention; meanwhile, for the general technical personnel in the field, according to the idea of the present invention, there are changes in the specific implementation and application scope, to sum up, the content of the present specification should not be understood as the limitation of the present invention.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include or include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.