Utility model content
The purpose of this utility model is to provide a kind of array substrate and display panels.
One side according to the present utility model provides a kind of array substrate, comprising: viewing area, including a plurality of signal lead；Non-display area, including multiple groups are fanned out to cabling, and it includes being superposed and the first metal routing insulated from each other, that every group, which is fanned out to cabling,Two metal routings, third metal routing, every group of the first metal routing, the second metal routing, third metal being fanned out in cabling are walkedLine is least partially overlapped.
Preferably, the array substrate further includes underlay substrate；
Every group be fanned out to cabling the underlay substrate upright projection by default aligned transfer.
Preferably, multiple groups are fanned out to cabling and are isolated from each other in the upright projection of the underlay substrate.
Preferably, the non-display area is provided with the first metal layer, second metal layer, third metal layer；
The first metal layer includes at least one the first metal routings；
The second metal layer includes at least one the second metal routings；
The third metal layer includes at least one third metal routing.
Preferably, the non-display area is provided with the first insulating layer and second insulating layer；
First insulating layer is between the first metal layer and the second metal layer；
The second insulating layer is between the second metal layer and the third metal layer.
Preferably, first metal routing, the second metal routing, third metal routing include first part andTwo parts, wherein the direction that first part extends is parallel with the direction that the signal lead extends, the direction that second part extendsIntersect in the direction extended with the signal lead.
Preferably, the second part of every group of first metal routing being fanned out in cabling, the second metal routing second part,The second part of third metal routing is completely overlapped.
Preferably, the second part of every group of first metal routing being fanned out in cabling, the second metal routing second part,The second part of third metal routing partly overlaps.
Preferably, the second part of the first metal routing in cabling, the second part of the second metal routing, are fanned out to for every groupOverlapping area and the area that is staggered between the second part of three metal routings meet following relationship:
S1=S2*d1/ (d1+d2), wherein S1 is every group and is fanned out to the second part of the first metal routing, second in cablingOverlapping area between the second part of metal routing, the second part of third metal routing, S2 are every group and are fanned out in cabling theThe second part of one metal routing, the second part of the second metal routing, third metal routing second part between be staggeredArea, vertical range of the d1 between the first metal routing and the second metal routing；D2 is the second metal routing and third metalVertical range between cabling.
Preferably, the array substrate further includes the driving chip that the non-display area is arranged in；
One end of each metal routing is connect with the signal lead, the other end of each metal routing and the driveDynamic chip connection.
Another aspect according to the present utility model provides a kind of display panel, including array substrate described above.
Array substrate provided by the utility model and display panel pass through the first metal routing of superposition distribution, the second gold medalBelong to cabling, third metal routing, reduce layout area, realizes narrow frame；Further, every group of first metal for being fanned out to cabling is walkedLine, the second metal routing, third metal routing partly overlap, and can reduce the first metal routing, the second metal routing andRC Loading between three metal routings improves the display quality of display panel.
Specific embodiment
Hereinafter reference will be made to the drawings is more fully described the various embodiments of the utility model.In various figures, identicalElement is indicated using same or similar appended drawing reference.For the sake of clarity, the various pieces in attached drawing are not drawn to drawSystem.
The utility model can be presented in a variety of manners, some of them example explained below.
Fig. 2 shows the structural schematic diagrams according to the array substrate of the utility model embodiment；Fig. 3 shows edge in Fig. 2The sectional view in the direction A-A '.As shown in Figures 2 and 3, the array substrate includes viewing area 10 and non-display area 20,
Wherein, viewing area 10 includes a plurality of signal lead 11, and a plurality of signal lead may include for providing gate driving letterNumber multi-strip scanning line, the multiple data lines for providing display data signal and the touch-control for providing touching signals driving letterNumber line etc..
Non-display area 20 includes that multiple groups are fanned out to cabling 21, and it includes being superposed and insulated from each other that every group, which is fanned out to cabling 21,One metal routing 211, the second metal routing 212, third metal routing 213, first metal routing 211, the second metal are walkedLine 212, third metal routing 213 include first part and second part, wherein first part extend direction with it is describedThe direction that signal lead 11 extends is parallel, and the direction that second part extends is intersected with the direction that the signal lead 11 extends.OftenThe second part of the first metal routing 211 that group is fanned out in cabling, the second part of the second metal routing 212, third metal are walkedThe second part of line 213 is completely overlapped.
As shown in figure 3, the array substrate further includes underlay substrate 201, multiple groups are fanned out to cabling 21 and are located at the substrate baseOn plate 201.Specifically, it is formed with the first metal layer M1 on the underlay substrate 201, is formed at least on the first metal layer M1One the first metal routing 211；The first insulating layer 202 and second metal layer M2 are sequentially formed on the first metal layer M1,At least one the second metal routings 212 are formed on second metal layer M2；Second is sequentially formed on second metal layer M2 absolutelyEdge layer 203 and third metal layer M3, form at least one third metal routing 213 on third metal layer M3.In third goldBelong to and is also formed with third insulating layer 204 on layer M3.
In the present embodiment, the first metal routing 211, the second metal routing 212, third metal routing 213 can be by goldBelong to material (such as silver, copper) to be made, and its constituent material can be the same or different from each other.
First insulating layer 202 is gate insulation layer, and material can be Si oxide, silicon nitride or silicon nitrogen oxides, butIt is without being limited thereto, general gate insulator layer material；Second insulating layer 203 and third insulating layer 204 are protective layer, and material canTo be silica, silicon nitride or organic material.
In the present embodiment, in array substrate every group be fanned out to cabling 21 the underlay substrate upright projection by default ruleRule arrangement, and each group is fanned out between cabling 21 and is isolated from each other that (i.e. multiple groups are fanned out to cabling 21 in the upright projection of the underlay substrateIt does not overlap each other).Such as Fig. 2 middle fan goes out bottom edge direction symmetry arrangement of the cabling 21 along array substrate.
Array substrate provided by the embodiment of the utility model, it includes be superposed that every group, which is fanned out to cabling, in array substrateOne metal routing, the second metal routing, third metal routing, the first metal routing, the second metal routing, third metal routing makeWith the three-layer metal layer cabling being superposed, adjacent two groups are fanned out to cabling and are isolated from each other, and are fanned out to cabling using single with every groupMetal layer cabling is compared, and the area for being fanned out to non-display area shared by cabling can be reduced, and realizes narrow frame.
Array substrate provided by the embodiment of the utility model, may also include positioned at viewing area a plurality of signal lead and be located atThe driving chip of non-display area.Such as one end of the first metal routing of each, the second metal routing and third metal routing withSignal lead connection, the other end and driving chip of the first metal routing of each, the second metal routing and third metal routingConnection, can specifically connect with the pad electrode of driving chip.Illustratively, referring to fig. 2, which further includes being set toThe multiple data lines 11 of viewing area 10 and the driving chip 22 of setting and non-display area 20；The first metal lead wire of each 211One end is connect with data line 11, and the other end of the first metal routing of each 211 is connect with driving chip 22.The second gold medal of eachThe one end for belonging to lead 212 is connect with data line 11, and the other end of the second metal routing of each 212 is connect with driving chip 22.One end of each third metal lead wire 213 is connect with data line 11, the other end of each third metal lead wire 213 and drivingChip 22 connects.
Fig. 4 shows the structural schematic diagram of the array substrate according to another embodiment of the utility model；
Fig. 5 is shown in Fig. 4 along the sectional view in the direction A-A '.As shown in Figure 4 and Figure 5, the array substrate includes displayArea 10 and non-display area 20,
Wherein, viewing area 10 includes a plurality of signal lead 11, and a plurality of signal lead may include for providing gate driving letterNumber multi-strip scanning line, the multiple data lines for providing display data signal and the touch-control for providing touching signals driving letterNumber line etc..
Non-display area 20 includes that multiple groups are fanned out to cabling 21, and it includes being superposed and insulated from each other that every group, which is fanned out to cabling 21,One metal routing 211, the second metal routing 212, third metal routing 213, first metal routing 211, the second metal are walkedLine 212, third metal routing 213 include first part and second part, wherein first part extend direction with it is describedThe direction that signal lead 11 extends is parallel, and the direction that second part extends is intersected with the direction that the signal lead 11 extends.OftenThe second part of the first metal routing 211 that group is fanned out in cabling, the second part of the second metal routing 212, third metal are walkedThe second part of line 213 partly overlaps.
As shown in figure 5, the array substrate further includes underlay substrate 201, multiple groups are fanned out to cabling 21 and are located at the substrate baseOn plate 201.Specifically, it is formed with the first metal layer M1 on the underlay substrate 201, is formed at least on the first metal layer M1One the first metal routing 211；The first insulating layer 202 and second metal layer M2 are sequentially formed on the first metal layer M1,At least one the second metal routings 212 are formed on second metal layer M2；Second is sequentially formed on second metal layer M2 absolutelyEdge layer 203 and third metal layer M3, form at least one third metal routing 213 on third metal layer M3.In third goldBelong to and is also formed with third insulating layer 204 on layer M3.
The second part of every group of first metal routing 211 being fanned out in cabling, the second metal routing 212 second part,Overlapping area and the area that is staggered between the second part of third metal routing 213 meet following relationship:
S1=S2*d1/ (d1+d2), wherein S1 be every group of first metal routing 211 being fanned out in cabling second part,Overlapping area between the second part of second metal routing 212, the second part of third metal routing 213, S2 are every group of fanThe second part of the first metal routing 211 in cabling, the second part of the second metal routing 212, third metal routing 213 outSecond part between the area that is staggered, vertical range of the d1 between the first metal routing 211 and the second metal routing 212,That is the thickness of the first insulating layer；Vertical range of the d2 between the second metal routing 212 and third metal routing 213, i.e., secondThe thickness of insulating layer.
At this point, the capacitor C between the first metal routing 211 and the second metal routing 21212=ε S1/d1, the first metal are walkedCapacitor C between line 211 and third metal routing 21313=ε S2/ (d1+d2), i.e. the first metal routing 211 are walked with the second metalCapacitor C12, the first metal routing 211 between line 212 and the capacitor C13 between third metal routing 213, the second metal routingCapacitor C23 between 212 and third metal routing 213 is equal.It may therefore be assured that the first metal routing 211, the second metalCabling 212, the RCloading of third metal routing 213 are of substantially equal.
In the present embodiment, the first metal routing 211, the second metal routing 212, third metal routing 213 can be by goldBelong to material (such as silver, copper etc.) to be made, and its constituent material can be the same or different from each other.
First insulating layer 202 is gate insulation layer, and material can be Si oxide, silicon nitride or silicon nitrogen oxides, butIt is without being limited thereto, general gate insulator layer material；Second insulating layer 203 and third insulating layer 204 are protective layer, and material canTo be silica, silicon nitride or organic material.
In the present embodiment, in array substrate multiple groups be fanned out to cabling 21 the underlay substrate upright projection by default ruleRule arrangement, and it is isolated from each other (i.e. every group is fanned out to cabling 21 and does not overlap each other in the upright projection of the underlay substrate).Such as Fig. 4In 21 along array substrate bottom edge direction symmetry arrangement.
Array substrate provided by the embodiment of the utility model, it includes being staggered to be superposed that every group, which is fanned out to cabling, in array substrateThe first metal routing, the second metal routing, third metal routing, the first metal routing, the second metal routing, third metal are walkedUsing the three-layer metal layer cabling being superposed, adjacent two groups are fanned out to cabling and are isolated from each other line, are fanned out to cabling with every group and useSingle metal layer cabling is compared, and the area for being fanned out to non-display area shared by cabling can be reduced, and realizes narrow frame, while can reduceRC Loading between first metal routing, the second metal routing and third metal routing, improves the display of display panelQuality.
Array substrate provided by the embodiment of the utility model, may also include positioned at viewing area a plurality of signal lead and be located atThe driving chip of non-display area.Such as a plurality of signal lead may include for providing the multi-strip scanning line of gate drive signal, usingIn the multiple data lines and touch drive signal line etc. for providing touching signals that provide display data signal, each firstOne end of metal routing, the second metal routing and third metal routing is connect with signal lead, the first metal routing of each,The other end of two metal routings and third metal routing is connect with driving chip, can specifically be connected with the pad electrode of driving chipIt connects.Illustratively, referring to fig. 2, which further includes that the multiple data lines 11 for being set to viewing area 10 and setting are shown with non-Show the driving chip 22 in area 20；One end of the first metal lead wire of each 211 is connect with data line 11, and the first metal of each is walkedThe other end of line 211 is connect with driving chip.One end of the second metal lead wire of each 212 is connect with data line 11, eachThe other end of second metal routing 212 is connect with driving chip.One end of each third metal lead wire 213 and data line 11 connectIt connects, the other end of each third metal lead wire 213 is connect with driving chip.
In addition, it includes the array base that the utility model any embodiment provides that the utility model, which also provides a kind of display panel,Plate.
It is for example above according to the embodiments of the present invention, these embodiments details all there is no detailed descriptionthe, also notLimit the specific embodiment that the utility model is only.Obviously, as described above, can make many modifications and variations.This explanationThese embodiments are chosen and specifically described to book, is in order to preferably explain the principles of the present invention and practical application, to makeSkilled artisan can be used using the utility model and modification on the basis of the utility model well.ThisThe protection scope of utility model should be subject to the range that the utility model claims are defined.