技术领域technical field
本实用新型涉及一种基于SPI模式的SD卡驱动器。The utility model relates to an SD card driver based on an SPI mode.
背景技术Background technique
目前，SD卡驱动器实现方法主要有用SOPC架构，依靠封装在FPGA器件中的嵌入式软核处理器（例如Altera的FPGA器件中Nios II处理器）实现SD卡驱动器，但无法直接应用在VLSI设计中。At present, the SD card driver implementation method mainly uses the SOPC architecture, relying on the embedded soft-core processor packaged in the FPGA device (such as the Nios II processor in Altera's FPGA device) to implement the SD card driver, but it cannot be directly applied to the VLSI design. .
采用C语言开发SD卡驱动器由于得到众多嵌入式芯片厂商的技术支持所以应用起来非常简单方便，主要用于嵌入式系统中，在目前的ARM系列处理器中都有很广泛的应用，甚至在FPGA的嵌入式软核Nios II也使用较多，但是其技术实现通常是黑盒，无法根据实际需求移植和修改以应用在VLSI设计中，同时速度也受到了处理器性能的限制不易调节，而且需要购买相应的嵌入式处理器和配套的调试软件导致外围电路复杂且成本较高。Using C language to develop SD card driver is very simple and convenient due to the technical support of many embedded chip manufacturers. It is mainly used in embedded systems. It is widely used in the current ARM series processors, even in FPGA. Embedded soft core Nios II is also widely used, but its technical implementation is usually a black box, which cannot be transplanted and modified according to actual needs to be applied in VLSI design. Purchasing the corresponding embedded processor and supporting debugging software leads to complex peripheral circuits and high cost.
4位SD总线通讯模式相对于SPI通讯模式的SD卡驱动器数据传输速率高，但是传输协议复杂，用硬件描述语言实现时逻辑资源消耗大。基于SPI模式的SD卡驱动器采用模块化功能划分优化系统架构，使得SPI模式的SD卡驱动器性能大幅度提高的同时减小逻辑资源消耗，能够满足使SD卡作为数据存储器直接应用于音频、视频、图像处理等VLSI设计中，发挥SD卡体型小、数据存储量大、数据传输速率快等优秀特点，为高性能数字IC设计和验证领域中急需的更贴近设计应用环境、可直观演示、高传输速率、易刷新等实验数据存储需求提供新的解决方案。The 4-bit SD bus communication mode has a higher data transmission rate than the SD card driver in the SPI communication mode, but the transmission protocol is complex, and the logic resource consumption is large when implemented in a hardware description language. The SD card driver based on the SPI mode adopts modular function division to optimize the system architecture, which greatly improves the performance of the SD card driver in the SPI mode and reduces the consumption of logic resources. In the VLSI design such as image processing, the excellent characteristics of SD card, such as small size, large data storage capacity, and fast data transmission rate, are used for the urgently needed design and application environment in the field of high-performance digital IC design and verification. Visual demonstration, high transmission Provide new solutions for experimental data storage requirements such as speed and easy refresh.
发明内容Contents of the invention
本实用新型的目的在于提供一种基于SPI模式的SD卡驱动器，该SD卡驱动器数据传输速度可调节、硬件资源消耗小和可热插拔的优点，输入输出数据经过同步Fifo缓存，使得本SD卡驱动器可以兼容不同数据吞吐速率的音视频等数据处理器，采用模块化功能划分，提高了设计的可移植性和可维护性，挂载FAT32文件系统可以实现在装有Windows 操作系统的上位机中对待处理数据文件的修改和拷贝。The purpose of the utility model is to provide a SD card driver based on SPI mode, the SD card driver has the advantages of adjustable data transmission speed, small hardware resource consumption and hot-swappable, and the input and output data are cached by synchronous Fifo, so that the SD The card driver can be compatible with data processors such as audio and video with different data throughput rates, and adopts modular function division to improve the portability and maintainability of the design. The FAT32 file system can be mounted on the upper computer with Windows operating system Modify and copy the data files to be processed.
为实现上述目的，本实用新型的技术方案是：一种基于SPI模式的SD卡驱动器，包括SD卡控制器模块、Fifo缓存模块、FAT32文件系统模块，所述SD卡控制器模块通过SPI总线与SD卡连接，SD卡控制器模块还通过Wishbone总线与FAT32文件系统模块连接，FAT32文件系统模块还与所述Fifo缓存模块连接。For achieving the above object, the technical scheme of the utility model is: a kind of SD card driver based on SPI mode, comprises SD card controller module, Fifo cache module, FAT32 file system module, described SD card controller module communicates with by SPI bus The SD card is connected, and the SD card controller module is also connected with the FAT32 file system module through the Wishbone bus, and the FAT32 file system module is also connected with the Fifo cache module.
在本实用新型一实施例中，所述SD卡控制器模块包括Wishbone总线从机、SPI主机控制器、SD初始化控制器、命令发送响应控制器、读写数据控制器、数据传输控制器、读写数据缓存器、SPI主机接口，Wishbone总线从机与SPI主机控制器、读写数据缓存器连接，SPI主机控制器还与读写数据控制器、SD初始化控制器、数据传输控制器连接，SD初始化控制器经命令发送响应控制器与读写数据控制器连接，数据传输控制器经SPI主机接口与读写数据缓存器连接，SPI主机接口还与SD卡连接。In an embodiment of the present invention, the SD card controller module includes a Wishbone bus slave, an SPI host controller, an SD initialization controller, a command sending response controller, a read-write data controller, a data transmission controller, a read-write Write data buffer, SPI host interface, Wishbone bus slave is connected with SPI host controller, read and write data buffer, SPI host controller is also connected with read and write data controller, SD initialization controller, data transmission controller, SD The initialization controller is connected with the read-write data controller through the command sending response controller, the data transmission controller is connected with the read-write data buffer through the SPI host interface, and the SPI host interface is also connected with the SD card.
在本实用新型一实施例中，所述Wishbone总线从机包括Wishbone从机控制器、Wishbone从机接口，Wishbone从机控制器与SPI主机控制器连接，Wishbone从机接口与读写数据缓存器连接，Wishbone从机控制器、Wishbone从机接口经Wishbone总线主机与FAT32文件系统模块连接。In an embodiment of the present invention, the Wishbone bus slave includes a Wishbone slave controller and a Wishbone slave interface, the Wishbone slave controller is connected to the SPI master controller, and the Wishbone slave interface is connected to the read-write data buffer , the Wishbone slave controller and the Wishbone slave interface are connected to the FAT32 file system module via the Wishbone bus master.
相较于现有技术，本实用新型具有以下有益效果：本实用新型具有数据传输速度可调节、硬件资源消耗小和可热插拔的优点，输入输出数据经过同步Fifo缓存，使得本SD卡驱动器可以兼容不同数据吞吐速率的音视频等数据处理器，采用模块化功能划分，提高了设计的可移植性和可维护性，挂载FAT32文件系统可以实现在装有Windows 操作系统的上位机中对待处理数据文件的修改和拷贝。Compared with the prior art, the utility model has the following beneficial effects: the utility model has the advantages of adjustable data transmission speed, low consumption of hardware resources and hot-swappable advantages, and the input and output data are cached through synchronous Fifo, so that the SD card driver It can be compatible with data processors such as audio and video with different data throughput rates. It adopts modular function division, which improves the portability and maintainability of the design. Mounting the FAT32 file system can realize the processing in the host computer equipped with Windows operating system. Handle modification and copying of data files.
附图说明Description of drawings
图1是本实用新型SD卡驱动器系统框图。Fig. 1 is a block diagram of the utility model SD card driver system.
图2是本实用新型读、写入控制逻辑下Fifo缓存内数据量变化趋势图。Fig. 2 is the change trend diagram of the amount of data in the Fifo cache under the read and write control logic of the utility model.
图3是本实用新型FAT32文件系统和Wishbone总线模块示意图。Fig. 3 is the schematic diagram of FAT32 file system and Wishbone bus module of the utility model.
图4是本实用新型SD卡控制器示意图。Fig. 4 is a schematic diagram of the SD card controller of the present invention.
具体实施方式Detailed ways
下面结合附图，对本实用新型的技术方案进行具体说明。Below in conjunction with accompanying drawing, the technical solution of the utility model is described in detail.
本实用新型的一种基于SPI模式的SD卡驱动器，包括SD卡控制器模块、Fifo缓存模块、FAT32文件系统模块，所述SD卡控制器模块通过SPI总线与SD卡连接，SD卡控制器模块还通过Wishbone总线与FAT32文件系统模块连接，FAT32文件系统模块还与所述Fifo缓存模块连接。所述SD卡控制器模块包括Wishbone总线从机、SPI主机控制器、SD初始化控制器、命令发送响应控制器、读写数据控制器、数据传输控制器、读写数据缓存器、SPI主机接口，Wishbone总线从机与SPI主机控制器、读写数据缓存器连接，SPI主机控制器还与读写数据控制器、SD初始化控制器、数据传输控制器连接，SD初始化控制器经命令发送响应控制器与读写数据控制器连接，数据传输控制器经SPI主机接口与读写数据缓存器连接，SPI主机接口还与SD卡连接。所述Wishbone总线从机包括Wishbone从机控制器、Wishbone从机接口，Wishbone从机控制器与SPI主机控制器连接，Wishbone从机接口与读写数据缓存器连接，Wishbone从机控制器、Wishbone从机接口经Wishbone总线主机与FAT32文件系统模块连接。A kind of SD card driver based on SPI mode of the present utility model comprises SD card controller module, Fifo cache module, FAT32 file system module, described SD card controller module is connected with SD card by SPI bus, SD card controller module It is also connected with the FAT32 file system module through the Wishbone bus, and the FAT32 file system module is also connected with the Fifo cache module. The SD card controller module includes a Wishbone bus slave, an SPI host controller, an SD initialization controller, a command sending response controller, a read-write data controller, a data transmission controller, a read-write data buffer, an SPI host interface, The Wishbone bus slave is connected to the SPI master controller and the read-write data buffer. The SPI master controller is also connected to the read-write data controller, the SD initialization controller, and the data transmission controller. The SD initialization controller sends the response controller through the command. It is connected with the read-write data controller, the data transmission controller is connected with the read-write data buffer through the SPI host interface, and the SPI host interface is also connected with the SD card. Described Wishbone bus slave comprises Wishbone slave controller, Wishbone slave interface, Wishbone slave controller is connected with SPI host controller, Wishbone slave interface is connected with read-write data buffer, Wishbone slave controller, Wishbone slave The computer interface is connected with the FAT32 file system module via the Wishbone bus host.
以下为本实用新型的具体实施过程。Below is the concrete implementation process of the present utility model.
本实用新型应用于高性能数字IC设计和验证领域，当从SD卡中读取数据时，输出数据经过同步Fifo缓存，使得本SD卡驱动器设计可以兼容不同数据吞吐速率的音视频等数据处理器。本文设计的SD卡驱动器采用技术方案如下所述：The utility model is applied to the field of high-performance digital IC design and verification. When data is read from the SD card, the output data is buffered through a synchronous Fifo, so that the SD card driver design can be compatible with data processors such as audio and video with different data throughput rates. . The SD card driver designed in this paper adopts the technical scheme as follows:
本SD卡驱动器由SD卡控制器挂载FAT32文件系统构成；使用Wishbone总线作为片上总线，其中FAT32文件系统模块作为Wishbone总线上的主机设备，SD卡控制器模块作为Wishbone总线上的从机设备；SD卡驱动器输入和输出数据经过宽度为8位，深度为2048的Fifo缓存。SD卡驱动器系统框图如图1所示。由三个部分构成，分别为Fifo缓存，FAT32文件系统和Wishbone总线，SD卡控制器。The SD card driver consists of an SD card controller mounted with a FAT32 file system; the Wishbone bus is used as the on-chip bus, and the FAT32 file system module is used as the host device on the Wishbone bus, and the SD card controller module is used as a slave device on the Wishbone bus; The SD card drive input and output data go through a Fifo cache with a width of 8 bits and a depth of 2048. The block diagram of the SD card driver system is shown in Figure 1. It consists of three parts, namely Fifo cache, FAT32 file system and Wishbone bus, and SD card controller.
SD卡驱动器中各模块之间连接关系如下所述：The connection relationship between the modules in the SD card driver is as follows:
SD卡驱动器输出的数据经过宽度为8位，深度为2048的Fifo缓存，使得本SD卡驱动器可以兼容不同数据吞吐速率的音视频等数据处理器；FAT32文件系统模块通过Wishbone总线访问SD卡控制器模块，SD卡控制器模块将FAT32文件系统模块经由Wishbone总线主机发出的扇区读、写等指令转换为地址信号与SD卡进行数据块交互的命令；SD卡控制器模块通过SPI总线连接SD卡，在SPI通信模式下完成对符合SD卡3.0版本规范的不同存储容量的SD卡进行初始化和SD卡中文件读写等操作。The data output by the SD card driver passes through a Fifo cache with a width of 8 bits and a depth of 2048, making the SD card driver compatible with data processors such as audio and video with different data throughput rates; the FAT32 file system module accesses the SD card controller through the Wishbone bus Module, the SD card controller module converts the sector read and write commands issued by the FAT32 file system module via the Wishbone bus host into address signals and commands for data block interaction with the SD card; the SD card controller module connects to the SD card through the SPI bus In the SPI communication mode, the initialization of SD cards with different storage capacities conforming to the SD card version 3.0 specification and the operations of reading and writing files in the SD card are completed.
SD卡驱动器中各模块功能如下所述：The functions of each module in the SD card driver are as follows:
1、Fifo缓存1. Fifo cache
SD卡驱动器中Fifo缓存为SCFIFO（读、写使用同一个时钟）；存储器宽度为8位，深度为2048；rst下降沿复位清空Fifo缓存；使用Normal mode的Rdreq读请求信号作为读取Fifo的请求信号(高有效)，读取数据在Rdreq置位后的第二个时钟周期有效；Wrreq写请求信号作为写入Fifo的请求信号(高有效)；usedw数据数量寄存器显示Fifo缓存中存储数据的数量。Fifo缓存的读、写入控制逻辑采用两段式摩尔状态机实现，状态在IDLE（空闲，state置0），FILL（填充，state置1）之间跳转。在读、写入控制逻辑下Fifo缓存内数据量变化趋势图如图2所示。The Fifo cache in the SD card drive is SCFIFO (the same clock is used for reading and writing); the memory width is 8 bits, and the depth is 2048; the rst falling edge reset clears the Fifo cache; the Rdreq read request signal of Normal mode is used as the request for reading Fifo Signal (high effective), the read data is valid in the second clock cycle after Rdreq is set; the Wrreq write request signal is used as a request signal for writing to Fifo (high effective); the usedw data quantity register displays the quantity of data stored in the Fifo cache . The read and write control logic of the Fifo cache is implemented by a two-stage Moore state machine, and the state jumps between IDLE (idle, state is set to 0) and FILL (filling, state is set to 1). Under the read and write control logic, the trend diagram of the data volume change in the Fifo cache is shown in Figure 2.
Fifo缓存的读、写入控制逻辑功能如下所述：The read and write control logic functions of Fifo cache are as follows:
FAT32文件系统从SD卡控制器模块取出1024+512个字节的数据并同时写入到Fifo缓存中，此时Fifo中无数据读出；停止写入数据到Fifo缓存，开始从Fifo缓存中读出512个字节的数据；FAT32文件系统在从SD卡控制器模块取出512个字节的数据同时写入到Fifo缓存中，此时Fifo中有数据读出。The FAT32 file system takes out 1024+512 bytes of data from the SD card controller module and writes them into the Fifo cache at the same time. At this time, there is no data read from the Fifo; stop writing data to the Fifo cache, and start reading from the Fifo cache. Output 512 bytes of data; the FAT32 file system writes 512 bytes of data from the SD card controller module to the Fifo cache at the same time, and at this time there is data read out of the Fifo.
2、FAT32文件系统和Wishbone总线2. FAT32 file system and Wishbone bus
为在装有Windows 操作系统的上位机中方便的创建、读取和修改SD 卡中数据，数据通常以文件的形式存储在SD 卡中，因此在使用SD卡作为数据存储设备的数字集成电路设计和验证中配以文件系统可以方便地读取装有Windows 操作系统的上位机传入的文件中数据。本SD 卡驱动器设计中采用FAT32 文件系统以适应较大容量的SD 卡。Wishbone总线由Wishbone总线主机模块和Wishbone总线从机模块，FAT32文件系统和Wishbone总线模块设计如图3所示。In order to create, read and modify the data in the SD card conveniently in the host computer equipped with the Windows operating system, the data is usually stored in the SD card in the form of a file, so in the digital integrated circuit design using the SD card as a data storage device It is equipped with a file system in the verification and verification, which can easily read the data in the file imported from the upper computer equipped with the Windows operating system. The FAT32 file system is adopted in the design of this SD card driver to adapt to SD cards with larger capacity. Wishbone bus consists of Wishbone bus master module and Wishbone bus slave module, FAT32 file system and Wishbone bus module design as shown in Figure 3.
以SD卡中仅存有一个文件，读取这个文件中数据为例说明FAT32文件系统和Wishbone总线功能如下所述：Taking only one file stored in the SD card, read the data in this file as an example to illustrate the functions of the FAT32 file system and the Wishbone bus as follows:
FAT32文件系统根据SD卡驱动器当前执行的功能（读取、写入等功能）和SD卡反馈的卡片信息（从根目录数据中解析出当前文件占用的字节数；用启动区中的数据计算出根目录和FAT1的起始地址，用根目录起始地址对应的内容得到第一个簇在数据区的地址；用FAT1起始地址对应的内容得到第二个簇在数据区的地址和第三个簇在FAT1中的地址）向Wishbone总线主机发送命令参数。（注：FAT1每一个地址对应的内容是当前簇号在数据区的地址和下一个簇号在FAT1中的地址）；发送到Wishbone总线主机模块，Wishbone总线主机模块将命令参数拆分成4个字节，Wishbone总线主机模块将命令字的第1个字节通过address地址接口发送到Wishbone总线从机模块，命令字的第2、3、4、5 字节为命令参数通过data_o数据接口发送到Wishbone总线从机模块；Wishbone总线从机模块根据address地址接口接收到的信息判断当前由Wishbone总线从机通过data_o数据接口发送到Wishbone总线主机的数据是SD卡控制器传输过来的SD卡反馈的卡片信息或者是SD卡各个扇区读出的存储数据，例如当地址译码为读单块数据时，则Wishbone总线从机连续发送读单块数据命令给SD卡控制器，并记录文件数据当前读出的字节数，直到读出的字节数大于等于文件占用的字节数。The FAT32 file system is based on the current functions of the SD card driver (reading, writing, etc.) Get the root directory and the starting address of FAT1, use the content corresponding to the starting address of the root directory to get the address of the first cluster in the data area; use the content corresponding to the starting address of FAT1 to get the address of the second cluster in the data area and the The addresses of the three clusters in FAT1) send command parameters to the Wishbone bus master. (Note: Each address of FAT1 corresponds to the address of the current cluster number in the data area and the address of the next cluster number in FAT1); it is sent to the Wishbone bus host module, and the Wishbone bus host module splits the command parameters into 4 byte, the Wishbone bus master module sends the first byte of the command word to the Wishbone bus slave module through the address address interface, and the second, third, fourth, and fifth bytes of the command word are command parameters and are sent to the Wishbone bus slave module; the Wishbone bus slave module judges the data currently sent by the Wishbone bus slave to the Wishbone bus master through the data_o data interface according to the information received by the address address interface, which is the card fed back by the SD card transmitted by the SD card controller Information or stored data read from each sector of the SD card, for example, when the address is decoded to read a single block of data, the Wishbone bus slave will continuously send the command to read a single block of data to the SD card controller, and record the file data currently read The number of bytes read until the number of bytes read is greater than or equal to the number of bytes occupied by the file.
Wishbone主机接口通过操作结束方式信号来了解SD卡控制器中的Wishbone从机接口的工作状态。操作结束方式信号为高电平时表示SD卡控制器中的Wishbone从机接口向Wishbone主机接口数据传输正常，反之则表示数据传输不正常。The Wishbone host interface understands the working status of the Wishbone slave interface in the SD card controller through the operation end signal. When the operation end mode signal is high level, it means that the data transmission from the Wishbone slave interface in the SD card controller to the Wishbone host interface is normal, otherwise it means that the data transmission is abnormal.
Wishbone主机通过Wishbone总线接口信号中的地址信号控制Wishbone从机接口的数据传输状态和类型（接收数据或者发送数据状态），通过Wishbone总线接口信号中的选通信号和写使能信号控制Wishbone从机接口数据传输的起始和终止。The Wishbone master controls the data transmission status and type of the Wishbone slave interface (receiving data or sending data status) through the address signal in the Wishbone bus interface signal, and controls the Wishbone slave through the strobe signal and write enable signal in the Wishbone bus interface signal Initiation and termination of interface data transmission.
3、SD卡控制器3. SD card controller
SD卡控制器由8个模块组成，Wishbone总线从机、SPI主机控制器、SD初始化控制器、命令发送响应控制器、读写数据控制器、数据传输控制器、读写数据缓存器、SPI主机接口。各部分之间通过控制寄存器、状态寄存器和数据线协调工作和传输数据。SD card controller consists of 8 modules, Wishbone bus slave, SPI host controller, SD initialization controller, command sending response controller, read and write data controller, data transmission controller, read and write data buffer, SPI host interface. Coordinate work and transmit data between various parts through control registers, status registers and data lines.
本系统设计中的SD卡控制器模块为SD卡提供运行时钟并且支持基于SPI通讯模式下的SD卡、Micro SD卡、MMC卡、TF卡等的复位、初始化、读单块、写单块、读多块、写多块操作。SD卡控制器如图4所示。The SD card controller module in this system design provides a running clock for the SD card and supports reset, initialization, single-block read, single-block write, etc. Read multi-block, write multi-block operation. The SD card controller is shown in Figure 4.
1）Wishbone总线从机1) Wishbone bus slave
Wishbone从机接口负责与SD卡控制器中各个模块进行数据和命令交互，并将SD卡主机模块的状态（是否应答及传输状态）作为响应传递回Wishbone主机。The Wishbone slave interface is responsible for data and command interaction with each module in the SD card controller, and sends the status of the SD card host module (response and transmission status) back to the Wishbone host as a response.
当处于数据读取状态时，Wishbone从机控制器通过判断主机地址类型，选择从SPI主机控制器读取数据并传输给wishbone主机接口或者将数据从读写数据Fifo缓存器中取出并传输给wishbone主机接口；当处于数据写入状态时，Wishbone从机将数据从Wishbone主机接口中取出并传输给读写数据缓存器。When in the data reading state, the Wishbone slave controller judges the host address type, chooses to read data from the SPI host controller and transmit it to the wishbone host interface or take the data out of the read and write data Fifo buffer and transmit it to the wishbone Host interface; when in the data writing state, the Wishbone slave takes the data from the Wishbone host interface and transmits it to the read-write data buffer.
Wishbone总线从机由Wishbone从机接口、Wishbone从机控制器构成，从机接口负责地址和数据的读取和写入，从机控制器负责通过地址判断传输给主机数据来源（SD卡反馈的卡片信息或者SD卡各个扇区读出的存储数据）。本设计中Wishbone总线采用“点到点”连接方式。因为CYC_O信号用于多主设备的仲裁请求，所以在 “点到点”连接方式中缺省。由于每次操作中数据全部有效，所以本设计中不设置SEL_O信号。The Wishbone bus slave consists of a Wishbone slave interface and a Wishbone slave controller. The slave interface is responsible for reading and writing addresses and data, and the slave controller is responsible for judging the source of data transmitted to the host through the address (SD card feedback card information or stored data read from each sector of the SD card). In this design, the Wishbone bus adopts the "point-to-point" connection mode. Because the CYC_O signal is used for the arbitration request of multi-master devices, it is defaulted in the "point-to-point" connection mode. Because all the data are valid in each operation, the SEL_O signal is not set in this design.
2）SPI主机控制器2) SPI host controller
SPI主机控制器的控制逻辑由有限状态机实现。SPI主机控制器根据地址类型和传输模式将SD卡响应经Wishbone总线从机发送到Wishbone总线主机。每个模块都设计了使能信号和反馈信号，SPI主机控制器通过检测其余模块的反馈信号决定下一步状态，通过控制其余模块的使能信号决定其工作状态。系统上电复位后首先由SPI主机控制器通过控制寄存器和状态寄存器向SD卡初始化控制器模块发送使能信号，使SD卡完成初始化。SPI主机在接收到SD卡完成初始化的反馈信号后，向读写数据控制器发送读或写请求。The control logic of the SPI host controller is implemented by a finite state machine. The SPI host controller sends the SD card response to the Wishbone bus master via the Wishbone bus slave according to the address type and transmission mode. Each module is designed with an enable signal and a feedback signal. The SPI host controller determines the next state by detecting the feedback signals of other modules, and determines its working state by controlling the enable signals of the other modules. After the system is powered on and reset, the SPI host controller sends an enabling signal to the SD card initialization controller module through the control register and the status register, so that the SD card is initialized. After receiving the feedback signal that the SD card completes initialization, the SPI host sends a read or write request to the read-write data controller.
3）SD初始化控制器3) SD initialization controller
SD初始化控制器在接收到SPI主机发送的使能信号后开始工作，产生复位命令CMD0，通过命令发送响应控制器发送给SD卡，在有效时间内收到正确的响应01h，复位完成。然后产生初始化命令CMD1，通过命令发送响应控制器发送给SD卡，在有效时间内收到正确的响应00h，初始化完成，SD卡进入SPI模式。The SD initialization controller starts to work after receiving the enable signal sent by the SPI host, generates a reset command CMD0, sends the response controller to the SD card through the command sending, and receives the correct response 01h within the valid time, and the reset is completed. Then generate the initialization command CMD1, send the response controller to the SD card through the command, and receive the correct response 00h within the valid time, the initialization is completed, and the SD card enters the SPI mode.
4）命令发送响应控制器4) Command Send Response Controller
命令发送响应控制器在接收到SPI主机控制器发送的使能信号后开始工作。将命令拼接成SD卡协议中规定的6字节格式，发送给SD卡。对于收到的反馈，判断是否是SD卡的响应以及是否响应超时。The command sends the response controller to start working after receiving the enable signal sent by the SPI host controller. Concatenate the command into the 6-byte format specified in the SD card protocol and send it to the SD card. For the received feedback, judge whether it is the response of the SD card and whether the response times out.
5）读写数据控制器5) Read and write data controller
读写数据控制器在接收到SPI主机发送的读或写使能信号后开始进入相应的状态。若收到写使能信号，产生单块写命令CMD24，通过命令发送响应控制器发送给SD卡。若在有效时间内收到正确的响应00h，则产生数据起始令牌FEh，与512字节数据、2字节的CRC一起写入读写数据缓存器。若在有效时间内收到的响应最后五位为00101，则SD卡成功接收数据。在SD卡忙状态时判断SD卡是否写超时，超过250ms仍处于忙状态则写错误。若收到读使能信号，产生单块读命令CMD17（第1个字节的最高位始终为0——起始位；次高位为1——表示命令是由主机向SD 卡发送的命令，后六位是命令索引；命令字的第2、3、4、5 字节为命令参数，若是读单块命令，则命令参数是扇区地址；最后一个字节是CRC校验字节），通过命令发送响应控制器发送给SD卡。若在有效时间内收到正确的响应00h，则开始接收数据起始令牌FEh。若在100ms内未收到数据起始令牌，则读超时，读SD卡错误。若接收到数据起始令牌，则将之后接收到的512字节数据写入读写数据缓存器。The read-write data controller starts to enter the corresponding state after receiving the read or write enable signal sent by the SPI master. If the write enable signal is received, a single block write command CMD24 is generated, which is sent to the SD card by the command sending response controller. If the correct response 00h is received within the effective time, the data start token FEh will be generated, which will be written into the read-write data register together with 512 bytes of data and 2 bytes of CRC. If the last five digits of the response received within the valid time are 00101, the SD card receives data successfully. When the SD card is busy, it is judged whether the SD card write timeout, and if the SD card is still busy for more than 250ms, the write error occurs. If the read enable signal is received, a single-block read command CMD17 is generated (the highest bit of the first byte is always 0—the start bit; the second highest bit is 1—indicates that the command is sent by the host to the SD card, The last six bits are the command index; the 2nd, 3rd, 4th, and 5th bytes of the command word are the command parameters, if it is a single block command, the command parameter is the sector address; the last byte is the CRC check byte), The controller sends the response to the SD card through the command. If the correct response 00h is received within the valid time, start receiving the data start token FEh. If the data start token is not received within 100ms, the read timeout occurs and the SD card read error occurs. If the data start token is received, the 512 bytes of data received later are written into the read-write data buffer.
6）数据传输控制器6) Data transmission controller
数据传输控制器是控制读写数据缓存器的模块。若收到命令发送响应控制器的使能信号时，接收命令发送响应控制器发送的6字节命令，并逐一发送给SPI主机接口。若收到读写数据控制器的写使能信号，则读取写数据Fifo缓存器Tx_FIFO中的512字节数据并将其发送给SPI主机接口。在数据传输的开始之前以及结束之后，发送8位高电平信号给SPI主机接口，维持时钟并且保持MOSI为高。在接收数据及响应时，通过Fifo内数据状态标志位信号来控制数据的接收过程。The data transfer controller is a module that controls reading and writing data buffers. If the enable signal of the command sending response controller is received, the receiving command sending responds to the 6-byte commands sent by the controller and sent to the SPI host interface one by one. If the write enable signal of the read-write data controller is received, the 512-byte data in the write data Fifo buffer Tx_FIFO is read and sent to the SPI host interface. Before the start of the data transfer and after the end, send an 8-bit high level signal to the SPI master interface, maintain the clock and keep MOSI high. When receiving data and responding, the data receiving process is controlled by the data status flag signal in Fifo.
7）读写数据Fifo缓存器7) Read and write data Fifo buffer
读写数据缓存器是缓存读写数据的存储器，负责存储要写入SD卡的512字节数据以及从SD卡读出的512字节数据。本设计中设计了一个一次可以存储64个8位数据，即128字节的异步FIFO。并且还设计了Wishbone从机与FIFO之间的控制器，实现了将要写入SD卡的数据直接从Wishbone从机存入FIFO，以及将SD卡读出的数据直接传递给Wishbone从机。The read-write data buffer is a memory for caching read-write data, responsible for storing 512-byte data to be written into the SD card and 512-byte data to be read from the SD card. In this design, one can store 64 8-bit data at a time, that is, an asynchronous FIFO of 128 bytes. In addition, the controller between the Wishbone slave and FIFO is designed, so that the data to be written into the SD card can be directly stored in the FIFO from the Wishbone slave, and the data read from the SD card can be directly transmitted to the Wishbone slave.
8）SPI主机接口8) SPI host interface
SPI主机接口是与SD卡直接通信的模块。由于SPI通信是串行通信，所以需要进行串并转换。通过两个移位寄存器，将写数据缓存器输出的并行数据转换为串行数据传输给SD卡，将SD卡输出的串行数据转换为并行数据存入读数据缓存器。同时给SD卡提供时钟信号。基于SPI模式的SD卡驱动器，SD卡命令字发送后会跟随对应的SD卡响应，用于指示命令或数据传输是否成功，有效地弥补了普通SPI总线缺乏应答机制以确认是否接收到数据的原理缺陷。The SPI host interface is the module that communicates directly with the SD card. Since SPI communication is serial communication, serial-to-parallel conversion is required. Through two shift registers, the parallel data output by the write data buffer is converted into serial data and transmitted to the SD card, and the serial data output by the SD card is converted into parallel data and stored in the read data buffer. At the same time, it provides a clock signal to the SD card. Based on the SD card driver in SPI mode, after the SD card command word is sent, it will follow the corresponding SD card response, which is used to indicate whether the command or data transmission is successful, which effectively makes up for the lack of response mechanism of the ordinary SPI bus to confirm whether the data is received. defect.
以上是本实用新型的较佳实施例，凡依本实用新型技术方案所作的改变，所产生的功能作用未超出本实用新型技术方案的范围时，均属于本实用新型的保护范围。The above are the preferred embodiments of the utility model, and all changes made according to the technical solution of the utility model, when the functional effect produced does not exceed the scope of the technical solution of the utility model, all belong to the protection scope of the utility model.
| Application Number | Priority Date | Filing Date | Title |
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| CN201820408063.4UCN208077160U (en) | 2018-03-26 | 2018-03-26 | SD card driver based on SPI mode |
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| CN201820408063.4UCN208077160U (en) | 2018-03-26 | 2018-03-26 | SD card driver based on SPI mode |
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