技术领域technical field
本实用新型涉及显示技术领域，具体地，涉及一种移位寄存单元、栅极驱动电路和显示面板。The utility model relates to the field of display technology, in particular to a shift register unit, a gate drive circuit and a display panel.
背景技术Background technique
随着液晶显示技术的发展，智能手表、健康监测器等可穿戴显示设备越来越普及，故，用于可穿戴设备的显示面板的设计逐渐兴起。由于可穿戴显示设备的显示面板的尺寸较小，故，用芯片驱动栅极的方式，不仅会增加显示面板的生产工序和成本，而且还不能实现窄边框设计，因此，在现有的产品中，常用的设计为基于LTPSCMOS工艺，在基板上分别制作P型TFT管和N型 TFT管，然后用两种不同类型的管子组建各种不同结构的逻辑电路，实现不同的功能，最后将各种逻辑电路组合到一起，构建栅极驱动电路，这样可以充分利用不同类型管子的特点，相互弥补，简便快捷地传递数字信号，相比使用单一类型TFT管构建栅极驱动电路(如a-Si产品)有很大优势。With the development of liquid crystal display technology, wearable display devices such as smart watches and health monitors are becoming more and more popular. Therefore, the design of display panels for wearable devices is gradually emerging. Due to the small size of the display panel of the wearable display device, the way of driving the gate with the chip will not only increase the production process and cost of the display panel, but also cannot realize the narrow frame design. Therefore, in the existing products , the commonly used design is based on the LTPSCMOS process, making P-type TFT tubes and N-type TFT tubes on the substrate, and then using two different types of tubes to form logic circuits with different structures to achieve different functions. Logic circuits are combined to build a gate drive circuit, which can make full use of the characteristics of different types of tubes, complement each other, and transmit digital signals easily and quickly. Compared with using a single type of TFT tube to build a gate drive circuit (such as a-Si products ) have great advantages.
然而，现有的移位寄存单元的电路结构单一且结构复杂。However, the circuit structure of the existing shift register unit is single and complex.
实用新型内容Utility model content
本实用新型针对现有技术中存在的上述技术问题之一，提供一种移位寄存单元、栅极驱动电路和显示面板，结构简单。The utility model aims at one of the above-mentioned technical problems existing in the prior art, and provides a shift register unit, a gate drive circuit and a display panel, which have a simple structure.
本实用新型提供一种移位寄存单元，包括移位寄存器；所述移位寄存器包括：两个传输门电路电路和三个反相器；其中第一个传输门电路的输入端作为移位寄存单元的输入端；第一个反相器的输入端和第一个传输门电路的输出端相连；第二个反相器的输入端和第一个反相器的输出端相连；第二个传输门电路的输入端和第二个反相器的输出端相连；第三个反相器的输入端和第二个传输门电路的输出端相连；第三个反相器的输出端与第二个反相器的输入端相连；第二个反相器的输出端作为移位寄存单元的输出端；两个所述传输门电路均与两个时钟信号端相连，用以在两个时钟信号端输入的时钟信号控制下一个打开另一个关闭。The utility model provides a shift register unit, which includes a shift register; the shift register includes: two transmission gate circuits and three inverters; wherein the input end of the first transmission gate circuit is used as a shift register The input of the unit; the input of the first inverter is connected to the output of the first transmission gate; the input of the second inverter is connected to the output of the first inverter; the second The input of the transmission gate is connected to the output of the second inverter; the input of the third inverter is connected to the output of the second transmission gate; the output of the third inverter is connected to the output of the second inverter The input ends of the two inverters are connected; the output end of the second inverter is used as the output end of the shift register unit; the two transmission gate circuits are connected with the two clock signal ends for switching between the two clocks The clock signal input by the signal terminal controls one to turn on and the other to turn off.
优选地，还包括：整形电路；所述整形电路的第一输入端和所述第二个反相器的输出端相连；所述整形电路的第二输入端与时序控制端相连；所述整形电路的输出端作为移位寄存单元的输出端；所述整形电路用于在时序控制端输入的时序控制信号下调整第二个反相器输出的脉冲宽度。Preferably, it also includes: a shaping circuit; the first input end of the shaping circuit is connected to the output end of the second inverter; the second input end of the shaping circuit is connected to the timing control end; the shaping circuit The output terminal of the circuit is used as the output terminal of the shift register unit; the shaping circuit is used to adjust the pulse width output by the second inverter under the timing control signal input from the timing control terminal.
优选地，还包括：缓冲过滤电路；所述缓冲过滤电路的输入端与所述整形电路的输出端相连；所述缓冲过滤电路的输出端作为移位寄存单元的输出端；所述缓冲过滤电路用于缓冲且滤掉毛刺信号。Preferably, it also includes: a buffer filter circuit; the input end of the buffer filter circuit is connected to the output end of the shaping circuit; the output end of the buffer filter circuit is used as the output end of the shift register unit; the buffer filter circuit Used for buffering and filtering glitch signals.
优选地，所述缓冲过滤电路包括两个串接的反相器。Preferably, the buffer filter circuit includes two serially connected inverters.
优选地，所述传输门电路包括：P型晶体管和N型晶体管； P型晶体管的控制端和N型晶体管的控制端与两个时钟信号端一一对应相连；P型晶体管的第一极和N型晶体管的第一极相连，且作为传输门电路的输入端；P型晶体管的第二极和N型晶体管的第二极相连，且作为传输门电路的输出端。Preferably, the transmission gate circuit includes: a P-type transistor and an N-type transistor; the control terminal of the P-type transistor and the control terminal of the N-type transistor are connected to the two clock signal terminals in one-to-one correspondence; the first pole of the P-type transistor and the The first poles of the N-type transistors are connected and serve as the input terminals of the transmission gate circuit; the second poles of the P-type transistors are connected with the second poles of the N-type transistors and are used as the output terminals of the transmission gate circuit.
优选地，所述反相器包括：P型晶体管和N型晶体管，P型晶体管的控制端和N型晶体管的控制端相连，作为反相器的输入端；P型晶体管的第一极和N型晶体管的第一极相连，且作为反相器的输出端；P型晶体管的第二极和N型晶体管的第二极与两个电平信号端一一对应相连。Preferably, the inverter includes: a P-type transistor and an N-type transistor, the control terminal of the P-type transistor is connected to the control terminal of the N-type transistor as the input terminal of the inverter; the first pole of the P-type transistor is connected to the N-type transistor. The first poles of the P-type transistors are connected and serve as the output terminals of the inverter; the second poles of the P-type transistors and the N-type transistors are connected to the two level signal terminals in a one-to-one correspondence.
优选地，所述整形电路为与门电路；所述与门电路包括：三对P型晶体管和N型晶体管；第一对P型晶体管和N型晶体管，二者的控制极相连，作为与门电路的第一输入端，二者的第一极与两个电平信号端一一对应相连；P型晶体管的第二极与第二对中的P型晶体管的第二极相连；N型晶体管的第二极与第二对中的N型晶体管的第一极相连；第二对P型晶体管和N型晶体管，二者的控制极相连，作为与门电路的第二输入端；P型晶体管的第一极与一个电平信号端相连；二者的第二极相连；第三对P 型晶体管和N型晶体管，二者的控制极相连且与第二对中P型晶体管的第二极相连；二者的第二极相连，作为与门电路的输出端；二者的第一极与两个电平信号端一一对应相连。Preferably, the shaping circuit is an AND gate circuit; the AND gate circuit includes: three pairs of P-type transistors and N-type transistors; the first pair of P-type transistors and N-type transistors, the control electrodes of the two are connected as an AND gate The first input terminal of the circuit, the first poles of the two are connected to the two level signal terminals in one-to-one correspondence; the second pole of the P-type transistor is connected to the second pole of the P-type transistor in the second pair; the N-type transistor The second pole of the second pair is connected to the first pole of the N-type transistor in the second pair; the control poles of the second pair of P-type transistor and N-type transistor are connected as the second input terminal of the AND gate circuit; the P-type transistor The first pole of the first pole is connected to a level signal terminal; the second poles of the two are connected; the third pair of P-type transistors and N-type transistors, the control poles of the two are connected and connected to the second pole of the P-type transistor in the second pair connected; the second poles of the two are connected as the output terminal of the AND gate circuit; the first poles of the two are connected to the two level signal terminals in one-to-one correspondence.
本实用新型还提供一种栅极驱动电路，包括多个上述提供的移位寄存单元，用于一一对应驱动多行像素；上一行的所述移位寄存单元的第二个反相器的输出端与下一行的所述移位寄存单元的输入端相连。The utility model also provides a gate drive circuit, which includes a plurality of shift register units provided above, for driving multiple rows of pixels in one-to-one correspondence; The output end is connected to the input end of the shift register unit in the next row.
本实用新型还提供一种显示面板，包括上述栅极驱动电路。The utility model also provides a display panel, including the above gate drive circuit.
优选地，还包括驱动芯片；所述驱动芯片用于直接向所述栅极驱动电路中移位寄存单元的两个时钟信号端提供时钟信号。Preferably, a driving chip is also included; the driving chip is used to directly provide clock signals to the two clock signal terminals of the shift register unit in the gate driving circuit.
本实用新型具有以下有益效果：The utility model has the following beneficial effects:
本实用新型提供一种新型且结构简单的移位寄存单元，包括移位寄存器，移位寄存器包括：两个传输门电路电路和三个反相器；第一个传输门电路的输入端作为移位寄存单元的输入端；第一个反相器的输入端和第一个传输门电路的输出端相连；第二个反相器的输入端和第一个反相器的输出端相连；第二个传输门电路的输入端和第二个反相器的输出端相连；第三个反相器的输入端和第二个传输门电路的输出端相连；第三个反相器的输出端与第二个反相器的输入端相连；第二个反相器的输出端作为移位寄存单元的输出端；两个传输门电路均与两个时钟信号端相连，用以在两个时钟信号端输入的时钟信号控制下一个打开另一个关闭。The utility model provides a novel shift register unit with a simple structure, which includes a shift register, and the shift register includes: two transmission gate circuits and three inverters; the input end of the first transmission gate circuit serves as a shift register The input terminal of the bit register unit; the input terminal of the first inverter is connected with the output terminal of the first transmission gate circuit; the input terminal of the second inverter is connected with the output terminal of the first inverter; The input of the two transmission gates is connected to the output of the second inverter; the input of the third inverter is connected to the output of the second transmission gate; the output of the third inverter It is connected to the input terminal of the second inverter; the output terminal of the second inverter is used as the output terminal of the shift register unit; the two transmission gate circuits are connected to the two clock signal terminals for The clock signal input by the signal terminal controls one to turn on and the other to turn off.
附图说明Description of drawings
图1a为本实用新型实施例一提供的第一种移位寄存单元的示意图；Fig. 1a is a schematic diagram of the first shift register unit provided by Embodiment 1 of the present utility model;
图1b为图1a所示的移位寄存单元的具体电路图；Fig. 1b is a specific circuit diagram of the shift register unit shown in Fig. 1a;
图1c为图1a所示的移位寄存单元的工作时序图；Fig. 1c is a working sequence diagram of the shift register unit shown in Fig. 1a;
图2a为本实用新型实施例二提供的第二种移位寄存单元的示意图；Fig. 2a is a schematic diagram of the second shift register unit provided by Embodiment 2 of the present invention;
图2b为图2a所示的移位寄存单元的具体电路图；Fig. 2b is a specific circuit diagram of the shift register unit shown in Fig. 2a;
图3为图1和图2中传输门电路电路的具体电路和符号；Fig. 3 is the specific circuit and symbol of transmission gate circuit among Fig. 1 and Fig. 2;
图4为图1和图2中反相器的具体电路和符号；Fig. 4 is the specific circuit and symbol of the inverter in Fig. 1 and Fig. 2;
图5为图2中与门电路的具体电路和符号；Fig. 5 is the concrete circuit and symbol of AND gate circuit in Fig. 2;
图6为图2中缓冲过滤电路的具体电路和符号；Fig. 6 is the specific circuit and symbol of the buffer filter circuit in Fig. 2;
图7为图2a和图2b所示移位寄存单元的工作时序图；Fig. 7 is a working timing diagram of the shift register unit shown in Fig. 2a and Fig. 2b;
图8a为本实用新型提供的栅极驱动电路相邻两行像素的移位寄存单元的示意图；Fig. 8a is a schematic diagram of the shift register unit of two adjacent rows of pixels in the gate drive circuit provided by the present invention;
图8b为图8a所示的具体的电路图；Figure 8b is a specific circuit diagram shown in Figure 8a;
图8c为图8a所示的工作时序图。Fig. 8c is a working sequence diagram shown in Fig. 8a.
具体实施方式Detailed ways
为使本领域的技术人员更好地理解本实用新型的技术方案，下面结合附图和具体实施方式对本实用新型所提供的移位寄存单元、栅极驱动电路和显示面板作进一步详细描述。In order for those skilled in the art to better understand the technical solution of the utility model, the shift register unit, the gate drive circuit and the display panel provided by the utility model will be further described in detail below with reference to the drawings and specific embodiments.
实施例1：Example 1:
图1a为本实用新型实施例一提供的第一种移位寄存单元的示意图；图1b为图1a所示的移位寄存单元的具体电路图；请参阅图1a和图1b，本实用新型提供的移位寄存单元，包括：移位寄存器，移位寄存器包括两个传输门电路1、2和三个反相器3-5；其中，第一个传输门电路1的输入端作为移位寄存单元的输入端；第一个反相器3的输入端和第一个传输门电路1的输出端相连；第二个反相器4的输入端和第一个反相器3的输出端相连；第二个传输门电路2的输入端和第二个反相器4的输出端相连；第三个反相器5的输入端和第二个传输门电路2的输出端相连；第三个反相器5的输出端与第二个反相器4的输入端相连；第二个反相器4的输出端作为移位寄存单元的输出端；两个传输门电路1和2均与两个时钟信号端CLK、CLKB相连，用以在两个时钟信号端输入的时钟信号控制下一个打开另一个关闭。Figure 1a is a schematic diagram of the first shift register unit provided by Embodiment 1 of the utility model; Figure 1b is a specific circuit diagram of the shift register unit shown in Figure 1a; please refer to Figure 1a and Figure 1b, which are provided by the utility model The shift register unit includes: a shift register, and the shift register includes two transfer gate circuits 1, 2 and three inverters 3-5; wherein, the input terminal of the first transfer gate circuit 1 is used as a shift register unit The input end of the first inverter 3 is connected to the output end of the first transmission gate circuit 1; the input end of the second inverter 4 is connected to the output end of the first inverter 3; The input terminal of the second transmission gate circuit 2 is connected with the output terminal of the second inverter 4; the input terminal of the third inverter 5 is connected with the output terminal of the second transmission gate circuit 2; the third inverter The output end of the phaser 5 is connected with the input end of the second inverter 4; the output end of the second inverter 4 is used as the output end of the shift register unit; two transmission gate circuits 1 and 2 are connected with two The clock signal terminals CLK and CLKB are connected to control one to turn on and the other to turn off under the control of the clock signal input from the two clock signal terminals.
其中，当传输门电路在打开时，传输门电路的输入端的信号可传输过去自输出端输出，逻辑表达式为Y(输出)＝A(输入)；当传输门电路在关闭时，传输门电路的输入端的信号不能够传输过去。Wherein, when the transmission gate circuit is on, the signal at the input terminal of the transmission gate circuit can be transmitted to output from the output terminal, and the logic expression is Y (output)=A (input); when the transmission gate circuit is closed, the transmission gate circuit The signal at the input terminal cannot be transmitted to the past.
反相器的功能是：逻辑表达式为例如，当反相器的输入信号为高电平时，则输出信号为低电平；当反相器的输入信号为低电平时，则输出信号为高电平。The function of the inverter is: the logical expression is For example, when the input signal of the inverter is high level, the output signal is low level; when the input signal of the inverter is low level, the output signal is high level.
在本实施例中，传输门电路1的具体电路优选为如图3所示，传输门电路1包括：P型晶体管M1和N型晶体管M2；P型晶体管M1的控制端与时钟信号端CLK相连，N型晶体管M2的控制端与时钟信号端CLKB相连；P型晶体管M1的第一极和N型晶体管 M2的第一极相连，且作为传输门电路的输入端A；P型晶体管M1 的第二极和N型晶体管M2的第二极相连，且作为传输门电路的输出端Y。In this embodiment, the specific circuit of the transmission gate circuit 1 is preferably as shown in Figure 3, the transmission gate circuit 1 includes: a P-type transistor M1 and an N-type transistor M2; the control terminal of the P-type transistor M1 is connected to the clock signal terminal CLK , the control terminal of the N-type transistor M2 is connected to the clock signal terminal CLKB; the first pole of the P-type transistor M1 is connected to the first pole of the N-type transistor M2, and is used as the input terminal A of the transmission gate circuit; the first pole of the P-type transistor M1 The second pole is connected to the second pole of the N-type transistor M2, and serves as the output terminal Y of the transmission gate circuit.
传输门电路2的具体电路与传输门电路1的电路不同的是： P型晶体管M1的控制端与时钟信号端CLKB相连，N型晶体管M2 的控制端与时钟信号端CLK相连。The specific circuit of the transmission gate circuit 2 is different from that of the transmission gate circuit 1 in that: the control terminal of the P-type transistor M1 is connected to the clock signal terminal CLKB, and the control terminal of the N-type transistor M2 is connected to the clock signal terminal CLK.
上述时钟信号端CLK和CLKB互为反相时钟信号，如图7所示，在此情况下，若CLK输入为低电平，CLKB输入为高电平时，传输门电路1中的P型晶体管M1和N型晶体管M2均导通，传输门电路2中的P型晶体管M1和N型晶体管M2均关闭，最终传输门电路1打开、传输门电路2关闭；若CLK输入为高电平，CLKB 输入为低电平时，传输门电路1中的P型晶体管M1和N型晶体管M2均关闭，传输门电路2中的P型晶体管M1和N型晶体管 M2均打开，最终传输门电路1关闭、传输门电路2打开。The above-mentioned clock signal terminals CLK and CLKB are mutually inverse clock signals, as shown in FIG. 7 , in this case, if the CLK input is at a low level and the CLKB input is at a high level, the P-type transistor M1 in the transmission gate circuit 1 Both the P-type transistor M1 and the N-type transistor M2 in the transmission gate circuit 2 are turned on, and finally the transmission gate circuit 1 is opened, and the transmission gate circuit 2 is closed; if the CLK input is high, the CLKB input When the level is low, both the P-type transistor M1 and the N-type transistor M2 in the transmission gate circuit 1 are turned off, and the P-type transistor M1 and the N-type transistor M2 in the transmission gate circuit 2 are both turned on, and finally the transmission gate circuit 1 is closed, and the transmission gate Circuit 2 is open.
反相器3(或4或5)具体电路优选为如图4所示，包括：P 型晶体管M1和N型晶体管M2，其中，P型晶体管M1的控制端和 N型晶体管M2的控制端相连，作为反相器3的输入端；P型晶体管M1的第一极和N型晶体管M2的第一极相连，且作为反相器3 的输出端；P型晶体管M1的第二极和N型晶体管M2的第二极与两个电平信号端一一对应相连，电平信号端包括高电平端VDD 和低电平端VSS，P型晶体管M1的第二极与VDD相连；N型晶体管M2的第二极与VSS相连。该反相器3在输入端A输入高电平时，N型晶体管M2打开，P型晶体管M1关闭，输出端Y输出低电平；在输入端A输入低电平时，N型晶体管M2关闭，P型晶体管M1打开，输出端Y输出高电平。The specific circuit of the inverter 3 (or 4 or 5) is preferably as shown in Figure 4, including: a P-type transistor M1 and an N-type transistor M2, wherein the control terminal of the P-type transistor M1 is connected to the control terminal of the N-type transistor M2 , as the input terminal of the inverter 3; the first pole of the P-type transistor M1 is connected to the first pole of the N-type transistor M2, and is used as the output terminal of the inverter 3; the second pole of the P-type transistor M1 is connected to the N-type transistor M2 The second pole of the transistor M2 is connected to two level signal terminals one by one, the level signal terminal includes a high level terminal VDD and a low level terminal VSS, the second pole of the P-type transistor M1 is connected to VDD; the N-type transistor M2’s The second pole is connected to VSS. When the inverter 3 inputs a high level at the input terminal A, the N-type transistor M2 is turned on, the P-type transistor M1 is turned off, and the output terminal Y outputs a low level; when the input terminal A is input with a low level, the N-type transistor M2 is turned off, and the P The type transistor M1 is turned on, and the output terminal Y outputs a high level.
下面结合图1c和图1b详细描述本实施例提供的移位寄存单元的工作过程：The working process of the shift register unit provided by this embodiment is described in detail below in conjunction with FIG. 1c and FIG. 1b:
在第一阶段，INPUT为高电平信号，此时CLK为高电平，CLKB 为低电平，传输门1中的M1、M2均关闭，数据无法传输；OUTPUT 电位初始为低电平；传输门2中的M7、M8均打开，OUTPUT的数据可以传输到M9、M10组成的反相器5，将M9打开，M10关闭，此，反相器5输出高电平，然后传输到M5、M6组成的反相器4，将M5关闭，M6打开，此反相器4输出低电平，如此，数据便在两个反相器4和5与传输门2组成的环路中循环流转，使OUTPUT 的电位一直保持为低电平。In the first stage, INPUT is a high level signal, at this time CLK is high level, CLKB is low level, M1 and M2 in transmission gate 1 are closed, and data cannot be transmitted; OUTPUT potential is initially low level; transmission Both M7 and M8 in gate 2 are open, and the data of OUTPUT can be transmitted to the inverter 5 composed of M9 and M10. M9 is opened and M10 is closed. Therefore, the inverter 5 outputs a high level, and then transmitted to M5 and M6 Inverter 4 composed of M5 is turned off, M6 is turned on, and this inverter 4 outputs a low level, so that the data circulates in the loop formed by the two inverters 4 and 5 and the transmission gate 2, so that The potential of OUTPUT is kept at low level.
在第二阶段，INPUT为高电平信号，此时CLK为低电平，CLKB 为高电平，传输门1中的M1、M2均打开，数据可以传输，高电平传输到M3、M4组成的反相器3，将M3关闭M4打开，此反相器1输出低电平，然后传输到M5、M6组成的反相器4，将M5打开M6关闭，此反相器4输出高电平，故，即OUTPUT电位为高电平。In the second stage, INPUT is a high level signal, at this time CLK is low level, CLKB is high level, M1 and M2 in transmission gate 1 are both open, data can be transmitted, and high level is transmitted to M3 and M4 to form Inverter 3, turn M3 off and M4 on, this inverter 1 outputs a low level, and then transmits it to the inverter 4 composed of M5 and M6, turn M5 on and M6 off, this inverter 4 outputs a high level , Therefore, the OUTPUT potential is high.
在第三阶段，INPUT为低电平信号，此时CLK为高电平，CLKB 为低电平，传输门电路电路1中的M1、M2均关闭，数据无法传输；OUTPUT电位为第二阶段的高电平；传输门2中的M7、M8 均打开，OUTPUT的数据可以传输到M9、M10组成的反相器5，将 M9关闭，M10打开，反相器5输出低电平，然后传输到M5、M6 组成的反相器4，将M5打开M6关闭，此反相器4输出高电平，如此，数据便在两个反相器与传输门组成的环路中循环流转，使 OUTPUT电位一直保持为高电平。In the third stage, INPUT is a low level signal, at this time CLK is high level, CLKB is low level, M1 and M2 in transmission gate circuit 1 are closed, and data cannot be transmitted; OUTPUT potential is the second stage High level; M7 and M8 in the transmission gate 2 are both open, and the data of OUTPUT can be transmitted to the inverter 5 composed of M9 and M10, M9 is closed, M10 is open, the inverter 5 outputs low level, and then transmitted to The inverter 4 composed of M5 and M6 turns M5 on and M6 off, and the inverter 4 outputs a high level. In this way, the data circulates in the loop formed by the two inverters and the transmission gate, so that the OUTPUT potential has been kept high.
由上可知，本实用新型提供一种新型且结构简单的移位寄存单元。It can be seen from the above that the present invention provides a novel shift register unit with a simple structure.
实施例2Example 2
图2a为本实用新型实施例二提供的第二种移位寄存单元的示意图；图2b为图2a所示的移位寄存单元的具体电路图；请参阅图2a和图2b，本实用新型提供的移位寄存单元与上述实施例一相比，同样包括移位寄存器10，由于移位寄存器10在上述实施例1中已经进行了详细地描述，在此不再赘述。Fig. 2a is a schematic diagram of the second shift register unit provided by the second embodiment of the utility model; Fig. 2b is a specific circuit diagram of the shift register unit shown in Fig. 2a; please refer to Fig. 2a and Fig. 2b, which are provided by the utility model Compared with the first embodiment above, the shift register unit also includes a shift register 10 , since the shift register 10 has been described in detail in the first embodiment above, it will not be repeated here.
下面详细描述本实施例与上述实施例的不同点。具体地，移位寄存单元还包括：整形电路20；整形电路20的第一输入端和第二个反相器4的输出端相连；整形电路20的第二输入端与时序控制端ENB相连；整形电路20的输出端作为移位寄存单元的输出端；整形电路20用于在时序控制端ENB输入的时序控制信号下调整第二个反相器4输出的脉冲宽度，脉冲宽度是指脉冲最大值持续的时间。Differences between this embodiment and the above-mentioned embodiments will be described in detail below. Specifically, the shift register unit further includes: a shaping circuit 20; the first input end of the shaping circuit 20 is connected to the output end of the second inverter 4; the second input end of the shaping circuit 20 is connected to the timing control end ENB; The output end of the shaping circuit 20 is used as the output end of the shift register unit; the shaping circuit 20 is used to adjust the pulse width output by the second inverter 4 under the timing control signal input by the timing control terminal ENB, and the pulse width refers to the maximum pulse width The duration of the value.
进一步优选地，移位寄存单元还包括：缓冲过滤电路30；其中，缓冲过滤电路30的输入端与整形电路20的输出端相连；缓冲过滤电路30的输出端作为移位寄存单元的输出端；缓冲过滤电路30用于缓冲且滤掉毛刺信号。Further preferably, the shift register unit further includes: a buffer filter circuit 30; wherein, the input end of the buffer filter circuit 30 is connected to the output end of the shaping circuit 20; the output end of the buffer filter circuit 30 is used as the output end of the shift register unit; The buffering and filtering circuit 30 is used for buffering and filtering out glitch signals.
在本实施例中，整形电路为与门电路，与门电路1的具体电路优选为如图5所示，与门电路包括：三对P型晶体管和N型晶体管，分别为M1和M4、M2和M3、M5和M6；第一对P型晶体管 M1和N型晶体管M4，二者的控制极相连，作为与门电路的第一输入端A，二者的第一极与两个电平信号端一一对应相连，如图 4中，P型晶体管M1的第一极与高电平信号端VDD相连，N型晶体管M2的第一极与低电平信号端VSS相连；P型晶体管M1的第二极与第二对中的P型晶体管M2的第二极相连；N型晶体管M4 的第二极与第二对中的N型晶体管M3的第一极相连.In this embodiment, the shaping circuit is an AND gate circuit, and the specific circuit of the AND gate circuit 1 is preferably as shown in Figure 5, and the AND gate circuit includes: three pairs of P-type transistors and N-type transistors, respectively M1 and M4, M2 And M3, M5 and M6; the first pair of P-type transistors M1 and N-type transistors M4, the control poles of the two are connected as the first input terminal A of the AND gate circuit, and the first poles of the two are connected to two level signals The terminals are connected one by one, as shown in Figure 4, the first pole of the P-type transistor M1 is connected to the high-level signal terminal VDD, and the first pole of the N-type transistor M2 is connected to the low-level signal terminal VSS; The second pole is connected to the second pole of the P-type transistor M2 in the second pair; the second pole of the N-type transistor M4 is connected to the first pole of the N-type transistor M3 in the second pair.
第二对P型晶体管M2和N型晶体管M3，二者的控制极相连，作为与门电路的第二输入端B；P型晶体管M2的第一极与一个电平信号端相连；二者的第二极相连。The second pair of P-type transistor M2 and N-type transistor M3, the control poles of the two are connected as the second input terminal B of the AND gate circuit; the first pole of the P-type transistor M2 is connected with a level signal terminal; The second pole is connected.
第三对P型晶体管M5和N型晶体管M6，二者的控制极相连且与第二对中P型晶体管M2的第二极相连；二者的第二极相连，作为与门电路的输出端Y；二者的第一极与两个电平信号端一一对应相连,P型晶体管M5的第一极与高电平信号端VDD相连；N 型晶体管M6的第一极与低电平信号端VSS相连。The third pair of P-type transistor M5 and N-type transistor M6, the control poles of the two are connected and connected with the second pole of the P-type transistor M2 in the second pair; the second poles of the two are connected as the output terminal of the AND gate circuit Y; the first poles of the two are connected to the two level signal terminals one by one, the first pole of the P-type transistor M5 is connected to the high-level signal terminal VDD; the first pole of the N-type transistor M6 is connected to the low-level signal terminal Terminal VSS is connected.
上述与门电路的逻辑表达式为Y＝A·B：当两个输入信号A 和B均为低电平时，M1、M2打开，M3、M4关闭，M3输出为高电平；P型TFTM5与N型TFTM6组成反相器，将M3输出的高电平变为低电平，即，Y为低电平；当两个输入信号A和B均为高电平时，M3、M4、M5打开，M1、M2、M6关闭，Y输出为高电平；当输入信号A为高电平且B为低电平时，M4、M2打开，M1和M3 关闭，M3输出为高电平，Y输出为低电平；当输入信号A为低电平且 B为高电平时，M4、M2关闭，M1和M3打开，M3输出为高电平， Y输出为低电平。The logical expression of the AND gate circuit above is Y=A·B: when the two input signals A and B are both low level, M1 and M2 are turned on, M3 and M4 are turned off, and the output of M3 is high level; P-type TFTM5 and N-type TFTM6 forms an inverter to change the high level output by M3 to low level, that is, Y is low level; when the two input signals A and B are both high level, M3, M4, and M5 are turned on, M1, M2, M6 are closed, Y output is high level; when input signal A is high level and B is low level, M4, M2 is open, M1 and M3 are closed, M3 output is high level, Y output is low Level; when the input signal A is low level and B is high level, M4 and M2 are closed, M1 and M3 are open, M3 output is high level, and Y output is low level.
缓冲过滤电路30包括两个串接的反相器，具体电路优选如图6所示，其中，一个反相器由P型晶体管M1和N型晶体管组成M2组成，另一个反相器由P型晶体管M3和N型晶体管组成 M4，所谓串接是指一个输出端与另一个输入端相连。具体反相器的介绍请参见上述实施例1，在此不再详述。The buffer filter circuit 30 includes two series-connected inverters, the specific circuit is preferably as shown in Figure 6, wherein one inverter is composed of P-type transistor M1 and N-type transistor M2, and the other inverter is composed of P-type The transistor M3 and the N-type transistor form M4, and the so-called serial connection means that one output end is connected with another input end. For the introduction of the specific inverter, please refer to the above-mentioned Embodiment 1, which will not be described in detail here.
下面集合图2a、图2b和图7详细描述本实施例提供的移位寄存单元的工作过程：其中，移位寄存器10的工作过程请参见上述实施例1，在此不再描述。The working process of the shift register unit provided by this embodiment will be described in detail below with reference to FIG. 2a , FIG. 2b and FIG. 7 : for the working process of the shift register 10 , please refer to the above-mentioned embodiment 1, and will not be described here.
第一阶段，由于移位寄存器10的输出(即1点电位)为低电平，且ENB输入低电平，因此，将整形电路20中的M12、M11、 M16打开，M14、M13、M15关闭，使整形电路20输出低电平；整形电路20输出的低电平送入缓冲过滤电路30，将M17、M20打开，M18、M19关闭，使缓冲过滤电路输出低电平，即OUTPUT为低电平。In the first stage, since the output of shift register 10 (i.e. 1 point potential) is low level, and ENB inputs low level, therefore, M12, M11, M16 in the shaping circuit 20 are opened, and M14, M13, M15 are closed , so that the shaping circuit 20 outputs a low level; the low level output by the shaping circuit 20 is sent to the buffer filter circuit 30, M17 and M20 are turned on, and M18 and M19 are turned off, so that the buffer filter circuit outputs a low level, that is, OUTPUT is a low level flat.
第二阶段，由于1点电位高电平，ENB有高电平和低电平，当ENB信号为高电平时，将M11、M12、M16关闭，M13、M14、M15 打开，使整形电路20输出高电平；最后，整形电路20的输出信号送入缓冲过滤电路30中，将M18、M19打开，M17、M20关闭，使OUTPUT输出高电平；在ENB信号为低电平时，整形电路20 输出低电平，缓冲过滤电路30输出低电平，即OUTPUT输出低电平。In the second stage, because the potential at point 1 is high, ENB has high and low levels. When the ENB signal is high, M11, M12, and M16 are turned off, and M13, M14, and M15 are turned on, so that the output of the shaping circuit 20 is high. level; finally, the output signal of the shaping circuit 20 is sent into the buffer filter circuit 30, M18, M19 are opened, M17, M20 are closed, so that OUTPUT outputs a high level; when the ENB signal is a low level, the shaping circuit 20 outputs a low level level, the buffer filter circuit 30 outputs a low level, that is, the OUTPUT outputs a low level.
第三阶段，1点电位为高电平，ENB信号为低电平，整形电路20输出低电平，经过缓冲过滤电路30后，OUTPUT输出低电平。In the third stage, the potential at point 1 is at high level, the ENB signal is at low level, the shaping circuit 20 outputs low level, and after passing through the buffer filter circuit 30 , OUTPUT outputs low level.
第四阶段，1点电位为低电平，无论ENB为高电平还是低电平，整形电路20输出低电平，经过缓冲过滤电路30后，OUTPUT 输出低电平。In the fourth stage, the potential at point 1 is low level, regardless of whether ENB is high level or low level, the shaping circuit 20 outputs low level, and OUTPUT outputs low level after passing through the buffer filter circuit 30 .
本实施例提供的移位寄存单元通过整形电路20可以根据实际情况调节脉冲宽度，适用性较高；并且借助缓冲过滤电路30，可以滤除点一些小的毛刺信号。The shift register unit provided in this embodiment can adjust the pulse width according to the actual situation through the shaping circuit 20 , and has high applicability; and with the help of the buffer filter circuit 30 , some small glitch signals can be filtered out.
实施例3Example 3
图8a为本实用新型提供的栅极驱动电路相邻两行像素的移位寄存单元的示意图；图8b为图8a所示的具体的电路图；图 8c为图8a所示的工作时序图，请参阅图8a-8c，本实施例提供一种栅极驱动电路，包括多个上述实施例1或2提供的移位寄存单元，用于一一对应驱动多行像素；上一行的移位寄存单元的第二个反相器4的输出端与下一行的移位寄存单元的输入端相连。Figure 8a is a schematic diagram of the shift register unit of two adjacent rows of pixels in the gate drive circuit provided by the present invention; Figure 8b is the specific circuit diagram shown in Figure 8a; Figure 8c is the working timing diagram shown in Figure 8a, please Referring to Figures 8a-8c, this embodiment provides a gate drive circuit, including a plurality of shift register units provided in Embodiment 1 or 2 above, for driving multiple rows of pixels in one-to-one correspondence; the shift register unit of the upper row The output terminal of the second inverter 4 is connected to the input terminal of the shift register unit in the next row.
下面结合图8c详细描述该栅极驱动电路的工作过程：其中，移位寄存单元采用上述实施例2提供的移位寄存单元，INPUT(0) 为第N行移位寄存单元的输入信号，INPUT(E)即1点电位，也为第N+1行移位寄存单元的输入信号，OUTPUT(0)为第N行移位寄存单元的输出信号，OUTPUT(E)为第N+1行移位寄存单元的输出信号，EN为相对ENB延迟一定相位的信号。The working process of the gate drive circuit is described in detail below in conjunction with FIG. 8c: wherein, the shift register unit adopts the shift register unit provided in Embodiment 2 above, and INPUT (0) is the input signal of the Nth row shift register unit, and INPUT (E) is the potential of 1 point, which is also the input signal of the N+1 row shift register unit, OUTPUT (0) is the output signal of the N row shift register unit, OUTPUT (E) is the N+1 row shift register unit The output signal of the bit register unit, EN is a signal delayed by a certain phase relative to ENB.
每个移位寄存单元的移位寄存器10、整形电路20和缓冲过滤电路30的工作过程请参见上述实施例1，在此不再描述，仅描述两个移位寄存单元之间的相互关系。For the working process of the shift register 10 , the shaping circuit 20 and the buffer filter circuit 30 of each shift register unit, please refer to the above-mentioned embodiment 1, which will not be described here, and only the relationship between the two shift register units will be described.
第一阶段，INPUT(E)电位为低电平，CLK为高电平，CLKB 为低电平，则1’电位为低电平；由于EN为低电平，则OUTPUT(E) 为低电平。In the first stage, INPUT (E) potential is low level, CLK is high level, CLKB is low level, then 1' potential is low level; since EN is low level, OUTPUT (E) is low level flat.
在第二阶段，INPUT(E)电位为高电平，CLK为低电平，CLKB 为高电平，1’电位保持为低电平；由于EN为低电平，则OUTPUT(E) 为低电平。In the second stage, the INPUT (E) potential is high, CLK is low, CLKB is high, and 1' potential remains low; since EN is low, OUTPUT (E) is low level.
在第三阶段，INPUT(E)电位为高电平，CLK为高电平，CLKB 为低电平，1’电位为高电平；在EN为高电平时，OUTPUT(E)为高电平；在EN为低电平时，OUTPUT(E)为低电平。In the third stage, INPUT (E) potential is high level, CLK is high level, CLKB is low level, 1' potential is high level; when EN is high level, OUTPUT (E) is high level ; When EN is low level, OUTPUT (E) is low level.
在第四阶段，INPUT(E)电位为低电平，CLK为低电平，CLKB 为高电平，1’电位保持为高电平，由于EN为低电平时，因此 OUTPUT(E)为低电平。In the fourth stage, INPUT (E) potential is low level, CLK is low level, CLKB is high level, 1' potential remains high level, and OUTPUT (E) is low because EN is low level level.
实施例4Example 4
本实施例还提供一种显示面板，包括上述实施例3提供的栅极驱动电路。This embodiment also provides a display panel, including the gate driving circuit provided in Embodiment 3 above.
该显示面板为可穿戴显示设备的显示面板，例如，手表。The display panel is a display panel of a wearable display device, for example, a watch.
该显示面板还包括驱动芯片；驱动芯片用于直接向栅极驱动电路中移位寄存单元的两个时钟信号端提供时钟信号，这样可以减少晶体管的数量，有利于窄边框设计和低功耗的要求。The display panel also includes a driver chip; the driver chip is used to directly provide clock signals to the two clock signal terminals of the shift register unit in the gate drive circuit, which can reduce the number of transistors, and is conducive to narrow frame design and low power consumption. Require.
可以理解的是，以上实施方式仅仅是为了说明本实用新型的原理而采用的示例性实施方式，然而本实用新型并不局限于此。对于本领域内的普通技术人员而言，在不脱离本实用新型的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本实用新型的保护范围。It can be understood that, the above embodiments are only exemplary embodiments adopted to illustrate the principles of the present invention, but the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present utility model, and these variations and improvements are also regarded as the protection scope of the present utility model.
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|---|---|
| CN (1) | CN207867875U (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110517628A (en)* | 2019-08-30 | 2019-11-29 | 京东方科技集团股份有限公司 | Display device, gate driving circuit, shift register circuit and driving method thereof |
| CN113948125A (en)* | 2021-11-26 | 2022-01-18 | 厦门半导体工业技术研发有限公司 | Pulse signal generating circuit and resistive random access memory |
| WO2022022081A1 (en)* | 2020-07-30 | 2022-02-03 | 京东方科技集团股份有限公司 | Pixel circuit and driving method therefor, display substrate, and display apparatus |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110517628A (en)* | 2019-08-30 | 2019-11-29 | 京东方科技集团股份有限公司 | Display device, gate driving circuit, shift register circuit and driving method thereof |
| WO2022022081A1 (en)* | 2020-07-30 | 2022-02-03 | 京东方科技集团股份有限公司 | Pixel circuit and driving method therefor, display substrate, and display apparatus |
| US12272295B2 (en) | 2020-07-30 | 2025-04-08 | Beijing Boe Display Technology Co., Ltd. | Pixel circuit for controlling light-emitting duration of light emitting element and method for driving same, display substrate, and display apparatus |
| CN113948125A (en)* | 2021-11-26 | 2022-01-18 | 厦门半导体工业技术研发有限公司 | Pulse signal generating circuit and resistive random access memory |
| CN113948125B (en)* | 2021-11-26 | 2024-07-02 | 厦门半导体工业技术研发有限公司 | Pulse signal generating circuit and resistive random access memory |
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| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee | Granted publication date:20180914 |