技术领域technical field
本实用新型涉及半导体集成电路制造技术领域,具体涉及一种光刻工艺中的晶圆结构。The utility model relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a wafer structure in a photolithography process.
背景技术Background technique
如图1所示,其中1ˊ为硅晶圆,2ˊ为对准标记,光刻是将掩膜版(mask)上图形形式的电路结构通过对准、曝光、显影等步骤转印到涂有光刻胶的硅片表面的工艺过程。光刻工艺会在硅片表面形成一层光刻胶掩蔽图形,其后续工艺是刻蚀或离子注入。半导体集成电路制造中,通常需要经过多次光刻工序。其中形成硅片第一层(最下层)图形的光刻称为零层光刻。零层光刻与刻蚀所形成的硅片第一层图形称为对准标记,对准标记是供后续光刻时对准之用的。As shown in Figure 1, 1ˊ is the silicon wafer, 2ˊ is the alignment mark, and photolithography is to transfer the circuit structure in the form of a pattern on the mask plate (mask) to the layer coated with photoresist through steps such as alignment, exposure, and development. process on the surface of silicon wafers. The photolithography process will form a layer of photoresist mask pattern on the surface of the silicon wafer, and its subsequent process is etching or ion implantation. In the manufacture of semiconductor integrated circuits, multiple photolithography processes are usually required. The lithography in which the first layer (lowest layer) of the silicon wafer is formed is called zero-layer lithography. The first layer pattern of the silicon wafer formed by zero-layer lithography and etching is called an alignment mark, and the alignment mark is used for alignment during subsequent lithography.
套刻精度是光刻工艺的重要表征参数,实现从设计回路图形通过光刻胶转移到硅基板,光刻图形的转移过程要遵循精确和无偏差两大原则,而要实现无偏差就要保证光刻的对准可以进行并且有保证。Overlay accuracy is an important characterization parameter of the lithography process. To realize the transfer from the design circuit pattern to the silicon substrate through the photoresist, the transfer process of the lithography pattern must follow the two principles of accuracy and no deviation. To achieve no deviation, it is necessary to ensure Lithographic alignment can be performed and guaranteed.
参见图2所示,其中3ˊ为不透明外延层,在形成对准标记之后,往往跟随有外延工艺,即在硅片表面生长从几微米到十几微米甚至更厚的不透明外延层,对准标记直接刻蚀硅形成,不透明外延层覆盖在同质的对准标记上,常常产生薄雾、滑移线、层错、穿刺等缺陷。这些缺陷对光刻对准有很大的影响,尤其是新世代SJ MOSFET中20~40μm的外延层会使得光刻对准标记产生非常严重地畸变甚至消失而完全无法对准。See Figure 2, where 3' is an opaque epitaxial layer. After the alignment mark is formed, it is often followed by an epitaxial process, that is, an opaque epitaxial layer from a few microns to more than ten microns or even thicker is grown on the surface of the silicon wafer. The alignment mark It is formed by direct etching of silicon, and the opaque epitaxial layer covers the homogeneous alignment mark, which often produces defects such as mist, slip line, stacking fault, and puncture. These defects have a great impact on the lithography alignment, especially the 20-40μm epitaxial layer in the new generation SJ MOSFET will cause the lithography alignment marks to be very seriously distorted or even disappear, making it impossible to align at all.
发明内容Contents of the invention
为了解决上述提到的问题,本申请提供一种晶圆结构,使对准标记可以在外延过程得到保护,在外延工艺后,通过刻蚀工艺可以使对准标记恢复,结构简单,制造方便,其技术方案如下:In order to solve the problems mentioned above, the present application provides a wafer structure, so that the alignment marks can be protected during the epitaxy process, and after the epitaxy process, the alignment marks can be restored by etching, the structure is simple, and the manufacturing is convenient. Its technical scheme is as follows:
一种光刻工艺中的晶圆结构,包括一硅晶圆,所述硅晶圆上至少包括两个对准标记,每个对准标记上方覆盖有透明介质膜。A wafer structure in photolithography process includes a silicon wafer, on which there are at least two alignment marks, each alignment mark is covered with a transparent dielectric film.
进一步地,所述透明介质膜厚度为500埃到1微米。将透明介质膜厚度限制为500埃到 1微米之间,厚度适中,其仅需一层透明介质膜,便可为后续对准标记上方的不透明外延层刻蚀提供足够的阻挡层,同时由于其仅为简单的一层透明介质膜,相比于其他工艺形成的多层膜结构,该透明介质膜制造工艺简单、快速,大大提高了生产效率。Further, the thickness of the transparent dielectric film is 500 angstroms to 1 micron. The thickness of the transparent dielectric film is limited to between 500 angstroms and 1 micron, which is moderate, and only one layer of transparent dielectric film is required to provide a sufficient barrier layer for the subsequent etching of the opaque epitaxial layer above the alignment mark. At the same time, due to its It is only a simple layer of transparent dielectric film. Compared with the multi-layer film structure formed by other processes, the manufacturing process of the transparent dielectric film is simple and fast, which greatly improves the production efficiency.
进一步地,所述透明介质膜覆盖范围大于对准标记至少200微米。Further, the coverage of the transparent dielectric film is at least 200 microns larger than the alignment mark.
进一步地,所述透明介质膜为二氧化硅或硼磷硅玻璃。Further, the transparent dielectric film is silicon dioxide or borophosphosilicate glass.
依据上述技术方案,本实用新型利用透明介质膜覆盖对准标记后,再做外延工艺时,不透明外延层在对准标记区域生长在不同质的透明介质膜上;不透明外延完成后,可以做刻蚀工艺,将对准标记上方的不透明外延层刻蚀掉;刻蚀过程中对准标记因为有透明介质膜保护,不会被破坏;透明介质膜采用二氧化硅,或硼磷硅玻璃材质,透明可视,不会影响后续的对准标记的可见性。According to the above technical scheme, after the alignment mark is covered with a transparent dielectric film in the utility model, when the epitaxy process is performed, the opaque epitaxial layer grows on the non-homogeneous transparent dielectric film in the alignment mark area; after the opaque epitaxy is completed, engraving can be done. Etching process, etch away the opaque epitaxial layer above the alignment mark; during the etching process, the alignment mark will not be damaged because it is protected by a transparent dielectric film; the transparent dielectric film is made of silicon dioxide or borophosphosilicate glass, Transparent and visible, does not affect the visibility of subsequent alignment marks.
附图说明Description of drawings
图1为现有技术的常规晶圆结构;Fig. 1 is the conventional wafer structure of prior art;
图2为图1经外沿后的结构图;Fig. 2 is the structural diagram of Fig. 1 after going through the outer edge;
图3为本实用新型的结构示意图;Fig. 3 is the structural representation of the utility model;
图4为图3经生长完外延层并去除对准标记上部外延层后的晶圆结构示意图。FIG. 4 is a schematic diagram of the wafer structure in FIG. 3 after growing the epitaxial layer and removing the upper epitaxial layer of the alignment mark.
其中,1ˊ、硅晶圆;2ˊ、对准标记;3ˊ、不透明外延层;1、硅晶圆;2、透明介质膜;3、不透明外延层。Among them, 1ˊ, silicon wafer; 2ˊ, alignment mark; 3ˊ, opaque epitaxial layer; 1, silicon wafer; 2, transparent dielectric film; 3, opaque epitaxial layer.
具体实施方式Detailed ways
下面通过具体实施方式结合附图对本实用新型作进一步详细说明。The utility model will be described in further detail below through specific embodiments in conjunction with the accompanying drawings.
一种光刻工艺中的晶圆结构,包括一硅晶圆1,所述硅晶圆1上至少包括两个对准标记,每个对准标记上方覆盖有透明介质膜2;A wafer structure in a photolithography process, comprising a silicon wafer 1, the silicon wafer 1 includes at least two alignment marks, and each alignment mark is covered with a transparent dielectric film 2;
进一步地,所述透明介质膜2厚度为500埃到1微米;将透明介质膜2厚度限制为500埃到1微米之间,厚度适中,其仅需一层透明介质膜,便可为后续对准标记上方的不透明外延层3刻蚀提供足够的阻挡层,同时由于其仅为简单的一层透明介质膜,相比于其他工艺形成的多层膜结构,该透明介质膜制造工艺简单、快速,大大提高了生产效率;Further, the thickness of the transparent dielectric film 2 is 500 angstroms to 1 micron; the thickness of the transparent dielectric film 2 is limited to 500 angstroms to 1 micron, which is moderate in thickness, and only one layer of transparent dielectric film is needed for subsequent The etching of the opaque epitaxial layer 3 above the quasi-mark provides a sufficient barrier layer. At the same time, because it is only a simple layer of transparent dielectric film, compared with the multi-layer film structure formed by other processes, the transparent dielectric film manufacturing process is simple and fast. , greatly improving production efficiency;
进一步地,所述透明介质膜2覆盖范围大于对准标记至少200微米;Further, the coverage of the transparent dielectric film 2 is at least 200 microns larger than the alignment mark;
进一步地,所述透明介质膜2为二氧化硅或硼磷硅玻璃。Further, the transparent dielectric film 2 is silicon dioxide or borophosphosilicate glass.
具体实施时,如图3所示,晶圆采用8英寸,左右对称分布两个对准标记,对准标记图形为边长88微米大小;利用标准的光刻和等离子刻蚀形成,沉积2000埃厚度二氧化硅,做光刻,用光刻胶保护对准标记上方200微米范围,其它区光刻胶曝光显影去除;用BOE溶液去除暴露二氧化硅,再去除光刻胶,即形成本实用新型的结构。During specific implementation, as shown in Figure 3, the wafer is 8 inches, with two alignment marks symmetrically distributed left and right, and the alignment mark pattern is 88 microns in size; it is formed by standard photolithography and plasma etching, and deposited 2000 Angstroms Thick silicon dioxide, do photolithography, use photoresist to protect the range of 200 microns above the alignment mark, and remove the photoresist in other areas by exposure and development; remove the exposed silicon dioxide with BOE solution, and then remove the photoresist, which forms the utility model. new structure.
如图4所示,利用本实用新型结构的晶圆,完成外延工艺后,晶圆涂布光刻胶,可以用曝光机采用无需对准方式曝光,曝开光刻标记200微米区域;因为光刻机在不做标记对准的情况下对准能力也可以达到200μm范围;刻蚀去除200μm范围内外延层,即露出对准标记。As shown in Figure 4, after using the wafer with the structure of the utility model, after the epitaxy process is completed, the wafer is coated with photoresist, and the exposure machine can be used to expose the 200 micron area of the lithography mark without alignment; because the light The alignment ability of the engraving machine can also reach the range of 200 μm without marking alignment; the epitaxial layer in the range of 200 μm is removed by etching, that is, the alignment mark is exposed.
以上应用了具体个例对本实用新型进行阐述,只是用于帮助理解本实用新型,并不用以限制本实用新型。对于本实用新型所属技术领域的技术人员,依据本实用新型的思想,还可以做出若干简单推演、变形或替换。The above uses specific examples to illustrate the utility model, which is only used to help understand the utility model, and is not intended to limit the utility model. For those skilled in the technical field to which the utility model belongs, some simple deduction, deformation or replacement can also be made according to the idea of the utility model.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721304296.1UCN207765451U (en) | 2017-10-11 | 2017-10-11 | A wafer structure in a photolithography process |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721304296.1UCN207765451U (en) | 2017-10-11 | 2017-10-11 | A wafer structure in a photolithography process |
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| CN207765451Utrue CN207765451U (en) | 2018-08-24 |
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| CN201721304296.1UExpired - Fee RelatedCN207765451U (en) | 2017-10-11 | 2017-10-11 | A wafer structure in a photolithography process |
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| CN114397801A (en)* | 2022-01-25 | 2022-04-26 | 长春理工大学 | A kind of protection method of electron beam lithography overlay marking |
| CN116072519A (en)* | 2023-01-31 | 2023-05-05 | 上海积塔半导体有限公司 | Photolithography process method |
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| CN111916360A (en)* | 2019-05-10 | 2020-11-10 | 中芯长电半导体(江阴)有限公司 | Fan-out type packaging method |
| CN114397801A (en)* | 2022-01-25 | 2022-04-26 | 长春理工大学 | A kind of protection method of electron beam lithography overlay marking |
| CN116072519A (en)* | 2023-01-31 | 2023-05-05 | 上海积塔半导体有限公司 | Photolithography process method |
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