技术领域technical field
本实用新型涉及数据通信技术领域，特别涉及一种单线防冲突竞争式总线网络。The utility model relates to the technical field of data communication, in particular to a single-line anti-collision competition type bus network.
背景技术Background technique
现场总线是一种工业数据总线，是自动化领域中底层数据通信网络，被誉为自动化领域的计算机局域网，是安装在制造或过程区域的现场装置与控制室内的自动装置之间的数字式、串行、多点通信的数据总线。现场总线以数字通信替代了传统4-20mA模拟信号及普通开关量信号的传输，是连接智能现场设备和自动化系统的全数字、双向、多站的通信系统。主要解决工业现场的智能化仪器仪表、控制器、执行机构等现场设备间的数字通信以及这些现场控制设备和高级控制系统之间的信息传递问题。Fieldbus is an industrial data bus, which is the underlying data communication network in the field of automation. It is known as the computer local area network in the field of automation. Line, multipoint communication data bus. Fieldbus replaces the transmission of traditional 4-20mA analog signals and ordinary switch signals with digital communication. It is an all-digital, two-way, multi-station communication system that connects intelligent field devices and automation systems. It mainly solves the digital communication between intelligent instruments and meters, controllers, actuators and other field devices in the industrial field, as well as the information transmission between these field control devices and advanced control systems.
目前存在着大约四十余种现场总线，如：FF总线、Profibus总线、Interbus总线、CAN总线、HART总线等。目前，应用较多的RS485总线、CAN总线、工业以太网都属于现场总线范畴，用户根据不同的场合和应用需求而采用不同的现场总线方式，每种总线有不同的标准特性。At present, there are more than forty kinds of field buses, such as: FF bus, Profibus bus, Interbus bus, CAN bus, HART bus and so on. At present, RS485 bus, CAN bus, and industrial Ethernet, which are widely used, all belong to the field bus category. Users adopt different field bus methods according to different occasions and application requirements, and each bus has different standard characteristics.
RS485总线的电气特性以两线间的电压差为+(2-6)V表示逻辑“1”，以两线间的电压差为-(2-6)V表示逻辑“0”。接口信号电平与TTL电平兼容，可方便与TTL电路连接。RS485接口组成半双工网络，一般需二根连线，为满足RS485通信需求，必须使用线径0.75或者1.0的屏蔽双绞线，否则会容易导致通信失败。大多数MCU控制的RS485网络使用总线型的拓扑结构，并采用主从式多址轮询方式实现多址接入，即所有通信节点共享一条通信线路，主节点按照地址依次轮流查询每一从节点，被查询的从节点返回相应的数据或空操作。因此，RS485的轮询周期随从节点数量增大而延长，系统反应变慢，使数据传输效率低。同时，RS485总线存在自适应、自保护功能脆弱等缺点，如不注意一些细节的处理，常出现通信失败甚至系统瘫痪等故障。The electrical characteristics of the RS485 bus is that the voltage difference between the two lines is + (2-6) V to indicate logic "1", and the voltage difference between the two lines is - (2-6) V to indicate logic "0". The interface signal level is compatible with TTL level, which can be easily connected with TTL circuit. The RS485 interface forms a half-duplex network, and generally requires two connections. In order to meet the RS485 communication requirements, a shielded twisted pair with a wire diameter of 0.75 or 1.0 must be used, otherwise it will easily lead to communication failure. Most MCU-controlled RS485 networks use a bus-type topology, and adopt a master-slave multi-address polling method to achieve multiple access, that is, all communication nodes share a communication line, and the master node queries each slave node in turn according to the address. , the queried slave node returns the corresponding data or a null operation. Therefore, the polling cycle of RS485 is extended with the increase of the number of slave nodes, the system response becomes slow, and the data transmission efficiency is low. At the same time, the RS485 bus has shortcomings such as self-adaptation and weak self-protection functions. If some details are not paid attention to, failures such as communication failures and even system failures often occur.
CAN总线采用双线串行通信方式，以报文的形式发送数据，每组报文的前十一位字符为标识符，是对报文优先级的定义。CAN总线以广播的方式发送数据，当一个节点获得总线使用权时，该节点变为发送报文状态，网络中其他的节点都处于接收状态，所有节点根据报文的ID决定接收或屏蔽该报文。由于CAN总线具有优先权和仲裁功能，因此可在不修改软硬件的情况下向CAN总线中加入新节点，便于灵活地配置、构建CAN总线网络。CAN总线采用短帧结构，每帧有8个有效字节，一般用于不需大量数据传输的控制类领域，若要进行多字节数据传输，则要对报文进行大量重组实现。The CAN bus adopts a two-wire serial communication method and sends data in the form of messages. The first eleven characters of each group of messages are identifiers, which define the priority of the messages. The CAN bus sends data in the form of broadcast. When a node obtains the right to use the bus, the node becomes in the state of sending messages, and other nodes in the network are in the receiving state. All nodes decide to receive or block the message according to the ID of the message. . Because the CAN bus has priority and arbitration functions, new nodes can be added to the CAN bus without modifying the software and hardware, which is convenient for flexible configuration and construction of the CAN bus network. The CAN bus adopts a short frame structure, and each frame has 8 effective bytes. It is generally used in control fields that do not require a large amount of data transmission. If multi-byte data transmission is required, a large number of messages must be reorganized to achieve.
基于TCP/IP的工业以太网是一种标准开放式的网络，采用IEEE802参考模型，由其组成的系统兼容性和互操作性好，资源共享能力强，可以很容易的实现将控制现场的数据与信息系统上的资源共享，但存在单点成本高、系统成本高、后期维护成本高等问题。以太网采用带有冲突检测的载波侦听多路访问协议，很难满足工业网络通信的实时性和确定性的要求。以太网采用超时重发机制，在网络负载很重或单点出现故障的情况下，可能造成整个网络系统的瘫痪。The industrial Ethernet based on TCP/IP is a standard open network, which adopts the IEEE802 reference model, and the system composed of it has good compatibility and interoperability, strong resource sharing ability, and can easily realize the control of field data. It is shared with resources on the information system, but there are problems such as high single point cost, high system cost, and high post-maintenance cost. Ethernet adopts the carrier sense multiple access protocol with collision detection, which is difficult to meet the real-time and deterministic requirements of industrial network communication. Ethernet adopts a timeout retransmission mechanism, which may cause the paralysis of the entire network system when the network load is heavy or a single point of failure occurs.
实用新型内容Utility model content
为此，需要提供一种解决RS485的轮询周期随从节点数量增大而延长，系统反应变慢，使数据传输效率低，及自适应和自保护功能脆弱、工业以太网单点成本高、系统成本高、后期维护成本高等问题并且CAN总线数据包大小不足的单线防冲突竞争式总线网络。For this reason, it is necessary to provide a solution to the problem that the polling cycle of RS485 is extended as the number of slave nodes increases, the system response becomes slow, the data transmission efficiency is low, and the self-adaptation and self-protection functions are fragile, the industrial Ethernet single-point cost is high, and the system Single-line anti-collision competitive bus network with high cost, high maintenance cost and insufficient CAN bus data packet size.
为实现上述目的，发明人提供了一种单线防冲突竞争式总线网络，包括节点、总线、中继器及主机；In order to achieve the above object, the inventor provides a single-line anti-collision competition type bus network, including nodes, buses, repeaters and hosts;
所述节点包括主控芯片及总线接口，所述总线接口一端与主控芯片的数据接收IO口连接；所述总线接口另一端连接于总线，所述总线接口另一端与主控芯片的数据发送IO口连接；所述总线连接于中继器的一端；所述中继器的一端通过电阻Rbus连接于24V电源，所述中继器的另一端连接于主机。The node includes a main control chip and a bus interface, one end of the bus interface is connected to the data receiving IO port of the main control chip; the other end of the bus interface is connected to the bus, and the other end of the bus interface is connected to the data transmission port of the main control chip The IO port is connected; the bus is connected to one end of the repeater; one end of the repeater is connected to the 24V power supply through a resistor Rbus, and the other end of the repeater is connected to the host.
进一步优化，所述节点为多个。For further optimization, there are multiple nodes.
进一步优化，所述总线接口包括三极管Q2、三极管Q3，所述三极管Q2为PNP型三极管，所述三极管Q2的基极通过电阻R3连接于中继器的一端及主控芯片的数据发送IO口，所述三极管Q2的发射极连接于24V电源，所述三极管Q2的集电极通过电阻R4接地，所述三极管Q3为NPN型三极管，所述三极管Q3的基极通过电阻R5连接于三极管Q2的集电极，所述三极管Q3的发射极接地，所述三极管Q3通过电阻R6连接于3.3V电源及通过电阻R7连接于主控制芯片的数据接收IO口。Further optimization, the bus interface includes a transistor Q2 and a transistor Q3, the transistor Q2 is a PNP transistor, the base of the transistor Q2 is connected to one end of the repeater and the data sending IO port of the main control chip through a resistor R3, The emitter of the transistor Q2 is connected to a 24V power supply, the collector of the transistor Q2 is grounded through a resistor R4, the transistor Q3 is an NPN transistor, and the base of the transistor Q3 is connected to the collector of the transistor Q2 through a resistor R5 , the emitter of the triode Q3 is grounded, and the triode Q3 is connected to the 3.3V power supply through the resistor R6 and connected to the data receiving IO port of the main control chip through the resistor R7.
进一步优化，所述主控芯片的数据发送接IO接口通过电阻R1连接于三极管Q1的基极，所述三极管Q1的发射极接地，所述三极管Q1的集电极连接于中继器的一端。Further optimization, the data sending IO interface of the main control chip is connected to the base of the transistor Q1 through the resistor R1, the emitter of the transistor Q1 is grounded, and the collector of the transistor Q1 is connected to one end of the repeater.
区别于现有技术，上述技术方案利用节点的主控芯片及简单的硬件结构实现低成本单总线双向通信，其结构简单，成本低廉。可灵活配置节点的优先级，利用分布式仲裁进行冲突检测，保证同一时刻内只用一个节点在进行数据发送，保证数据通信的可靠性；并采用串行通信方式，单次最多可传送256字节数据，解决CAN总线数据包大小不足的问题。Different from the prior art, the above technical solution utilizes the main control chip of the node and a simple hardware structure to realize low-cost single-bus bidirectional communication, and has a simple structure and low cost. The priority of nodes can be flexibly configured, and distributed arbitration can be used for conflict detection to ensure that only one node is used for data transmission at the same time, ensuring the reliability of data communication; and using serial communication, a maximum of 256 words can be transmitted at a time Section data, to solve the problem of insufficient CAN bus data packet size.
附图说明Description of drawings
图1为具体实施方式所述一种单线防冲突竞争式总线网络的一种结构示意图；Fig. 1 is a kind of structural schematic diagram of a kind of single-wire anti-collision competition type bus network described in the specific embodiment;
图2为具体实施方式所述总线接口的一种结构示意图，FIG. 2 is a schematic structural diagram of the bus interface described in the specific embodiment,
图3为具体实施方式所述总线时序图的一种结构示意图。FIG. 3 is a schematic structural diagram of the bus sequence diagram described in the specific embodiment.
具体实施方式Detailed ways
为详细说明技术方案的技术内容、构造特征、所实现目的及效果，以下结合具体实施例并配合附图详予说明。In order to explain in detail the technical content, structural features, achieved goals and effects of the technical solution, the following will be described in detail in conjunction with specific embodiments and accompanying drawings.
请参阅图1及图2，本实施例一种单线防冲突竞争式总线网络，包括节点、总线、中继器及主机；Please refer to FIG. 1 and FIG. 2, a single-line anti-collision competition bus network in this embodiment, including nodes, buses, repeaters and hosts;
所述节点包括主控芯片及总线接口，所述总线接口一端与主控芯片的数据接收IO口连接；所述总线接口另一端连接于总线，所述总线接口另一端与主控芯片的数据发送IO口连接；所述总线连接于中继器的一端；所述中继器的一端通过电阻Rbus连接于24V电源，所述中继器的另一端连接于主机。其中，该总线一般用于单主机系统，能够控制一个或多个从机设备。则，节点可以为一个或者多个。主机的控制芯片通过Bus_RX、Bus_TX引脚分别与中继器相应引脚相连，经中继器的1_Wire_Bus与节点1～n的1_Wire_Bus引脚相连，实现主从机的网络连接，从而实现一对一、一对多通信。其中主机的控制芯片也可以通过总线接口与节点的总线接口相连，主机的总线接口与节点的总线接口的结构及连接方式相同。为保证数据传输的可靠性和稳定性，在主机与从机节点之间通过中继器来代替总线接口的功能，可通过调节上拉电子Rbus的阻值进行调节总线的负载能力。在从机节点与主机在100米线距范围内，总线负载32个以内节点传输效果最佳。若要进一步增加传输距离或增加从机节点，则应根据需求及实际现场情况中继器。其中主控芯片可以采用STM32系列的单片机。The node includes a main control chip and a bus interface, one end of the bus interface is connected to the data receiving IO port of the main control chip; the other end of the bus interface is connected to the bus, and the other end of the bus interface is connected to the data transmission port of the main control chip The IO port is connected; the bus is connected to one end of the repeater; one end of the repeater is connected to the 24V power supply through a resistor Rbus, and the other end of the repeater is connected to the host. Among them, the bus is generally used in a single-master system, which can control one or more slave devices. Then, there can be one or more nodes. The control chip of the host is connected to the corresponding pins of the repeater through the Bus_RX and Bus_TX pins, and the 1_Wire_Bus of the repeater is connected to the 1_Wire_Bus pins of nodes 1~n to realize the network connection of the master and slave, thus realizing one-to-one , One-to-many communication. The control chip of the host can also be connected to the bus interface of the node through the bus interface, and the structure and connection method of the bus interface of the host and the bus interface of the node are the same. In order to ensure the reliability and stability of data transmission, the function of the bus interface is replaced by a repeater between the master and slave nodes, and the load capacity of the bus can be adjusted by adjusting the resistance of the pull-up electronic Rbus. When the distance between the slave node and the master is within 100 meters, the transmission effect of the bus load within 32 nodes is the best. If you want to further increase the transmission distance or increase the number of slave nodes, repeaters should be used according to the needs and actual site conditions. Among them, the main control chip can adopt STM32 series single-chip microcomputer.
在总线网络中，所有的节点通过一条总线经1_Wire_Bus并联至中继器中，中继器经上拉电阻Rbus连接于24V电源，上拉电阻Rbus可安装在中继器上，通过调节电阻Rbus的阻值，动态调节总线的负载能力；当总线空闲时，节点的主控芯片的数据接收IO口Bus_RX处于接收监听状态；一旦中继器或者某个节点发出数据时，节点的主控芯片的数据发送IO口Bus_TX输出数据将总线电位拉低，总线的电位状态随主控芯片的数据发送IO口Bus_TX发送数据的变化而变化，当总线的电位被拉低时，则总线接口处于导通状态，从而其他节点的主控芯片的数据接收IO口Bus_RX将收到总线发来的数据，并逐位传输至其主控芯片进行接收缓冲存储，接收到的数据结合预先拟定的通讯协议进行数据解析，实现单总线的数据通信功能。In the bus network, all the nodes are connected in parallel to the repeater through a bus through 1_Wire_Bus, and the repeater is connected to the 24V power supply through the pull-up resistor Rbus. The pull-up resistor Rbus can be installed on the repeater. By adjusting the resistance Rbus Resistance value, dynamically adjust the load capacity of the bus; when the bus is idle, the data receiving IO port Bus_RX of the node's main control chip is in the receiving and monitoring state; once the repeater or a certain node sends data, the data of the node's main control chip Send the output data of IO port Bus_TX to pull down the bus potential. The potential state of the bus changes with the change of the data sent by the main control chip. When the potential of the bus is pulled down, the bus interface is in the conduction state. Therefore, the data receiving IO port Bus_RX of the main control chip of other nodes will receive the data sent by the bus, and transmit it bit by bit to its main control chip for receiving buffer storage, and the received data is combined with the pre-established communication protocol for data analysis. Realize the data communication function of single bus.
通过利用节点的主控芯片及简单的硬件结构实现低成本单总线双向通信，其结构简单，成本低廉。可灵活配置节点的优先级，利用分布式仲裁进行冲突检测，保证同一时刻内只用一个节点在进行数据发送，保证数据通信的可靠性，解决由于总线问题而造成网络瘫痪的问题；并采用串行通信方式，单次最多可传送256字节数据，解决CAN总线数据包大小不足的问题。The low-cost single-bus two-way communication is realized by using the main control chip of the node and a simple hardware structure, and the structure is simple and the cost is low. It can flexibly configure the priority of nodes, use distributed arbitration for conflict detection, ensure that only one node is used for data transmission at the same time, ensure the reliability of data communication, and solve the problem of network paralysis caused by bus problems; and adopt serial It can transmit up to 256 bytes of data at a time, which solves the problem of insufficient CAN bus data packet size.
具体的，所述总线接口包括三极管Q2、三极管Q3，所述三极管Q2为PNP型三极管，所述三极管Q2的基极通过电阻R3连接于中继器的一端及主控芯片的数据发送IO口，所述三极管Q2的发射极连接于24V电源，所述三极管Q2的集电极通过电阻R4接地，所述三极管Q3为NPN型三极管，所述三极管Q3的基极通过电阻R5连接于三极管Q2的集电极，所述三极管Q3的发射极接地，所述三极管Q3通过电阻R6连接于3.3V电源及通过电阻R7连接于主控制芯片的数据接收IO口。所述主控芯片的数据发送接IO接口通过电阻R1连接于三极管Q1的基极，所述三极管Q1的发射极接地，所述三极管Q1的集电极连接于中继器的一端。Specifically, the bus interface includes a transistor Q2 and a transistor Q3, the transistor Q2 is a PNP transistor, the base of the transistor Q2 is connected to one end of the repeater and the data sending IO port of the main control chip through a resistor R3, The emitter of the transistor Q2 is connected to a 24V power supply, the collector of the transistor Q2 is grounded through a resistor R4, the transistor Q3 is an NPN transistor, and the base of the transistor Q3 is connected to the collector of the transistor Q2 through a resistor R5 , the emitter of the triode Q3 is grounded, and the triode Q3 is connected to the 3.3V power supply through the resistor R6 and connected to the data receiving IO port of the main control chip through the resistor R7. The data sending IO interface of the main control chip is connected to the base of the triode Q1 through the resistor R1, the emitter of the triode Q1 is grounded, and the collector of the triode Q1 is connected to one end of the repeater.
当总线处于空闲状态时，总线处于高电位，所有节点处于接收监听状态；当某个节点准备发送数据前，先对总线的状态进行检测，该节点的主控芯片的数据发送IO口BUS_TX输出数据经电阻R1及电阻R2控制三极管Q1将总线电位拉低，总线的电位状态随主控芯片的数据发送IO口Bus_TX发送数据的变化而变化，当总线的电位被拉低时，三极管Q2及三极管Q3处于导通状态，从而其他节点的主控芯片的数据接收IO口Bus_RX将收到总线发来的数据，并逐位传输至主控芯片进行接收缓冲存储，接收到的数据结合预先拟定的通讯协议进行数据解析，从而实现单总线的数据通信功能。When the bus is in the idle state, the bus is at high potential, and all nodes are in the receiving and monitoring state; when a node is ready to send data, it first detects the state of the bus, and the data of the main control chip of the node sends the IO port BUS_TX output data The transistor Q1 is controlled by the resistor R1 and the resistor R2 to pull down the potential of the bus. The potential state of the bus changes with the change of the data sent by the IO port Bus_TX of the main control chip. When the potential of the bus is pulled down, the transistor Q2 and the transistor Q3 In the conduction state, the data receiving IO port Bus_RX of the main control chip of other nodes will receive the data sent by the bus, and transmit it bit by bit to the main control chip for receiving buffer storage, and the received data is combined with the pre-established communication protocol Perform data analysis to realize the data communication function of single bus.
参阅图3，总线时序图，表明了一次完整的数据传输时序。完整的数据信息由起始符、数据信息头、数据信息、结束符等4部分组成。首先，当总线处于空闲状态时，总线处于常态，即高电位状态。随后，发送节点发出一个字节的起始符，用以表明数据信息传输开始。接着，发送节点将7字节数据信息头传至总线，数据信息头包含5字节的目的节点地址和2字节的数据长度信息，其中2字节的数据长度信息表明了后续数据域的信息长度。接着根据数据信息的不同，开始传送N字节的数据信息，该数据信息包含CRC数据校验。最后，待数据传输结束，将总线电平拉高，完成本次总线数据传输的全过程。由于总线使用串行通信方式进行传输，预先对总线的数字逻辑进行了约定，总线以1位低电位与1位高电位组合表示逻辑“1”，以2位低电位与1位高电位组合表示逻辑“0”。Refer to Figure 3, the bus timing diagram, which shows a complete data transmission timing. The complete data information is composed of 4 parts such as the start symbol, the data information header, the data information, and the end symbol. First, when the bus is in an idle state, the bus is in a normal state, that is, a high potential state. Subsequently, the sending node sends out a one-byte start symbol to indicate the start of data transmission. Next, the sending node transmits the 7-byte data header to the bus. The data header includes a 5-byte destination node address and 2-byte data length information, where the 2-byte data length information indicates the information of the subsequent data field length. Then, according to the difference of the data information, the data information of N bytes is transmitted, and the data information includes the CRC data check. Finally, after the data transmission ends, the bus level is pulled high to complete the whole process of this bus data transmission. Since the bus uses serial communication for transmission, the digital logic of the bus has been agreed in advance. The bus uses a combination of 1 low potential and 1 high potential to represent logic "1", and a combination of 2 low potentials and 1 high potential. logic "0".
另一个实施例中，一种单线防冲突竞争式总线通信方法，具体按照以下步骤进行：In another embodiment, a single-line anti-collision competition bus communication method is specifically performed according to the following steps:
步骤1.当总线处于空闲状态时，总线处于高电位，所有节点处于接收监听状态；Step 1. When the bus is in an idle state, the bus is at a high potential, and all nodes are in a receiving and monitoring state;
步骤2.当某个节点准备发送数据前，先对总线的状态进行检测，以确定总线是否处于空闲状态，若总线忙，则需等待直至总线空闲；Step 2. Before a node prepares to send data, it first detects the state of the bus to determine whether the bus is in an idle state. If the bus is busy, it needs to wait until the bus is idle;
步骤3.发送节点将带有目的地址的数据包送入总线，此时总线上可能有多个节点参与总线竞争；由于总线采用串行通信方式，所有参与本次竞争的节点通过发送端，经NPN电路将目的地址逐位送入总线；竞争时，从目的地址的最高位至最低位逐位竞争，只有上一位竞争得胜者才能继续下一位目的地址的传送；Step 3. The sending node sends the data packet with the destination address into the bus. At this time, there may be multiple nodes participating in the bus competition on the bus; since the bus adopts a serial communication mode, all nodes participating in this competition pass through the sending end and pass through The NPN circuit sends the destination address to the bus bit by bit; during competition, it competes bit by bit from the highest bit to the lowest bit of the destination address, and only the winner of the previous competition can continue to transmit the next bit of destination address;
步骤4.竞争不到的发送节点自动撤除其目的地址，最后竞争得胜的节点获得总线使用权，随即启动数据发送，其余节点处于数据监听接收状态；数据传输过程中，总线的电位将随发送引脚变化而变化，目的节点的接收引脚将收到的数据进行接收并存储；为保证数据传输的正确性和完整性，总线采用CRC校验。Step 4. The sending node that cannot compete will automatically remove its destination address, and the node that wins the competition finally obtains the right to use the bus, and then starts data transmission, and the rest of the nodes are in the state of data monitoring and receiving; during data transmission, the potential of the bus will follow. The receiving pin of the destination node will receive and store the received data; in order to ensure the correctness and integrity of data transmission, the bus adopts CRC check.
通过可方法可实现一对一或者一对多的通信，各个主控芯片之间确定相互竞争的通信协议，明确所指定的目标地址、起始标志位、结束标志位就能实现准确可靠的远程通信。One-to-one or one-to-many communication can be realized by means of methods, and each main control chip can determine the communication protocol that competes with each other, and clearly specify the specified target address, start flag, and end flag to achieve accurate and reliable remote control. communication.
需要说明的是，尽管在本文中已经对上述各实施例进行了描述，但并非因此限制本实用新型的专利保护范围。因此，基于本实用新型的创新理念，对本文所述实施例进行的变更和修改，或利用本实用新型说明书及附图内容所作的等效结构或等效流程变换，直接或间接地将以上技术方案运用在其他相关的技术领域，均包括在本实用新型专利的保护范围之内。It should be noted that although the above-mentioned embodiments have been described herein, the patent protection scope of the present utility model is not limited thereby. Therefore, based on the innovative concept of the present utility model, the changes and modifications to the embodiments described herein, or the equivalent structure or equivalent process transformation made by using the description of the utility model and the contents of the accompanying drawings, directly or indirectly convert the above technologies The application of the scheme in other relevant technical fields is included in the protection scope of the utility model patent.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721382011.6UCN207266039U (en) | 2017-10-25 | 2017-10-25 | A kind of single line anti-collision competitive mode bus network |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721382011.6UCN207266039U (en) | 2017-10-25 | 2017-10-25 | A kind of single line anti-collision competitive mode bus network |
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| CN207266039Utrue CN207266039U (en) | 2018-04-20 |
| Application Number | Title | Priority Date | Filing Date |
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| CN201721382011.6UActiveCN207266039U (en) | 2017-10-25 | 2017-10-25 | A kind of single line anti-collision competitive mode bus network |
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