技术领域technical field
本实用新型涉及基于数字可寻址照明接口的照明控制系统，具体涉及一种DALI接口电路。The utility model relates to a lighting control system based on a digital addressable lighting interface, in particular to a DALI interface circuit.
背景技术Background technique
数字可寻址照明接口(DALI)协议是目前照明控制领域唯一国际性的标准协议。基于DALI协议的照明控制系统的典型结构是主从结构，一路DALI总线由总线电源、最多64个控制装置和最多64个控制设备组成。总线电源能提供最大250mA输出电流,每个控制装置和非总线供电控制设备允许从DALI总线上最多消耗2mA电流，总线供电的控制设备通常从总线上消耗10mA电流。The Digital Addressable Lighting Interface (DALI) protocol is currently the only international standard protocol in the field of lighting control. The typical structure of the lighting control system based on DALI protocol is a master-slave structure. One DALI bus is composed of bus power supply, up to 64 control devices and up to 64 control devices. The bus power supply can provide a maximum output current of 250mA. Each control device and non-bus-powered control equipment is allowed to consume a maximum of 2mA current from the DALI bus. Bus-powered control equipment usually consumes 10mA current from the bus.
DALI接口电路控制装置和控制设备之间的通信电路，图1为目前的一种常用的DALI接口电路，如图1所示，DALI接口电路采用两个光耦U1和U2实现DALI总线与控制电路之间的隔离通信。上述结构的DALI接口电路存在以下一些问题：DALI interface circuit The communication circuit between the control device and the control equipment. Figure 1 is a commonly used DALI interface circuit. As shown in Figure 1, the DALI interface circuit uses two optocouplers U1 and U2 to realize the DALI bus and the control circuit Isolated communication between. The DALI interface circuit of the above structure has the following problems:
(1)为了保护光电耦合器U1正常工作，需要Q1、Q3、R5构成一个限流高压保护电路，增加了接口电路的复杂性。(1) In order to protect the normal operation of the photocoupler U1, Q1, Q3, and R5 are required to form a current-limiting high-voltage protection circuit, which increases the complexity of the interface circuit.
(2)光电耦合器U1的工作电流由DALI总线提供，由于接口电路的工作电流小于2mA，不足以让光电耦合器U1处在额定工作状态，造成接收信号RX的延时长达40微秒，降低了通信的可靠性。(2) The working current of the photocoupler U1 is provided by the DALI bus. Since the working current of the interface circuit is less than 2mA, it is not enough to keep the photocoupler U1 in the rated working state, resulting in a delay of up to 40 microseconds for the received signal RX. Reduced communication reliability.
(3)DALI总线在理论上最多可以接入64个控制装置和64个控制设备，64个控制装置总共消耗128mA总线电流，余量不足以给64个非总线供电控制设备供电，更无法满足总线供电控制设备的需求，造成DALI智能照明控制系统必须减少控制装置和控制设备的数量，并尽可能使用非总线供电的控制设备，极大的影响了系统功能，增加了系统复杂性。(3) The DALI bus can theoretically connect up to 64 control devices and 64 control devices. The 64 control devices consume a total of 128mA bus current, and the margin is not enough to supply power to 64 non-bus-powered control devices, let alone meet the requirements of the bus. The demand for power supply control equipment causes the DALI intelligent lighting control system to reduce the number of control devices and control equipment, and use non-bus-powered control equipment as much as possible, which greatly affects system functions and increases system complexity.
有鉴于此，现在急需提供一种功率更低、延时更短、结构更简单、可靠性更高的DALI接口电路。In view of this, there is an urgent need to provide a DALI interface circuit with lower power, shorter delay, simpler structure and higher reliability.
实用新型内容Utility model content
本实用新型所要解决的技术问题是DALI接口电路的RX信号延时较长且功率较大的问题。The technical problem to be solved by the utility model is that the RX signal of the DALI interface circuit has a longer delay and a higher power.
为了解决上述问题，本实用新型提供了一种DALI接口电路，包括整流单元、电平处理单元、收发隔离单元和MOS管，所述收发隔离单元采用的是集成DC/DC转换器的双通道数字隔离器，所述整流单元的输入端接DALI信号，所述整流单元的输出端接所述电平处理单元和所述MOS管的漏极，所述MOS管的源极接地，所述双通道数字隔离器的第一通道的输出端接RX信号，第二通道的输入端接TX信号，所述双通道数字隔离器的第二通道的输出端接所述MOS管的栅极；DALI信号经所述整流单元整流后，由所述电平处理单元进行限流稳压，再从所述双通道数字隔离器的第一通道的输入端输入，由第一通道的输出端输出；TX信号由所述双通道数字隔离器的第二通道的输入端输入，根据TX信号的电平高低控制MOS管开关，使DALI信号相应地变为低电平或维持高电平。In order to solve the above problems, the utility model provides a DALI interface circuit, including a rectification unit, a level processing unit, a transceiver isolation unit and a MOS tube, and the transceiver isolation unit uses a dual-channel digital integrated DC/DC converter An isolator, the input terminal of the rectification unit is connected to the DALI signal, the output terminal of the rectification unit is connected to the level processing unit and the drain of the MOS transistor, the source of the MOS transistor is grounded, and the dual channel The output terminal of the first channel of the digital isolator is connected to the RX signal, the input terminal of the second channel is connected to the TX signal, and the output terminal of the second channel of the dual-channel digital isolator is connected to the gate of the MOS transistor; the DALI signal is passed through After the rectification unit is rectified, the level processing unit performs current limiting and voltage stabilization, and then input from the input end of the first channel of the dual-channel digital isolator, and output from the output end of the first channel; the TX signal is obtained by The input terminal of the second channel of the dual-channel digital isolator controls the switch of the MOS transistor according to the level of the TX signal, so that the DALI signal becomes low level or maintains high level accordingly.
在上述方案中，电平处理单元包括电压电流限制模块、第四电阻和电容，所述电压电流限制模块由第一电阻、第二电阻、第三电阻依次串联组成；所述第四电阻和电容并联后，一端接所述MOS管的栅极，另一端接地。In the above scheme, the level processing unit includes a voltage and current limiting module, a fourth resistor and a capacitor, and the voltage and current limiting module is composed of a first resistor, a second resistor, and a third resistor in series; the fourth resistor and the capacitor After parallel connection, one end is connected to the gate of the MOS transistor, and the other end is grounded.
在上述方案中，还包括稳压二极管，所述稳压二极管的阴极接所述电压电流限制模块的输出端，所述稳压二极管的阳极接地。In the above solution, a voltage stabilizing diode is further included, the cathode of the voltage stabilizing diode is connected to the output terminal of the voltage and current limiting module, and the anode of the voltage stabilizing diode is grounded.
本实用新型，使用一个集成DC/DC转换器的双通道数字隔离器替代了两个光耦，大大简化了电路设计，同时，由于双通道数字隔离器本身由集成的DC/DC转换器工作，此转换器是由主电源而不是DALI总线来供电的，使电路中元器件都能在额定状态下工作，降低了DALI接口电路信号的延时，提高了可靠性；并且数字隔离器不依靠DALI总线供电，极大地降低了DALI总线输入电流，从2mA降低到0.2mA，因此DALI总线可接入更多的控制装置和控制设备。In the utility model, a dual-channel digital isolator integrated with a DC/DC converter is used to replace two optocouplers, which greatly simplifies the circuit design. At the same time, since the dual-channel digital isolator itself is operated by an integrated DC/DC converter, This converter is powered by the main power supply instead of the DALI bus, so that the components in the circuit can work in the rated state, reducing the delay of the DALI interface circuit signal and improving reliability; and the digital isolator does not rely on DALI The bus power supply greatly reduces the DALI bus input current from 2mA to 0.2mA, so the DALI bus can be connected to more control devices and control equipment.
附图说明Description of drawings
图1为现有的DALI接口电路示意图；Fig. 1 is the schematic diagram of existing DALI interface circuit;
图2为本实用新型提供的DALI接口电路示意图。Fig. 2 is a schematic diagram of the DALI interface circuit provided by the utility model.
具体实施方式Detailed ways
本实用新型提供了一种DALI接口电路，电路结构简单、功率低，信号延时低、可靠性高。下面结合说明书附图和具体实施方式对本实用新型做出详细的说明。The utility model provides a DALI interface circuit, which has simple circuit structure, low power, low signal delay and high reliability. The utility model is described in detail below in conjunction with the accompanying drawings and specific embodiments.
如图2所示，本实用新型提供的DALI接口电路由整流单元10、电平处理单元20与收发隔离单元30组成。As shown in FIG. 2 , the DALI interface circuit provided by the present invention is composed of a rectification unit 10 , a level processing unit 20 and a transceiver isolation unit 30 .
电平处理单元20由电压电流限制模块201、第四电阻R6、MOS管Q2、电容C1、稳压二极管D2组成，电压电流限制模块201由第一电阻R2、第二电阻R3、第三电阻R4依次串联组成。收发隔离单元30采用的是集成DC/DC转换器的双通道数字隔离器，本实用新型中双通道数字隔离器的型号为ADUM5211。The level processing unit 20 is composed of a voltage and current limiting module 201, a fourth resistor R6, a MOS transistor Q2, a capacitor C1, and a Zener diode D2. The voltage and current limiting module 201 is composed of a first resistor R2, a second resistor R3, and a third resistor R4 composed sequentially in series. The transceiver isolation unit 30 adopts a dual-channel digital isolator integrated with a DC/DC converter, and the model of the dual-channel digital isolator in the present invention is ADUM5211.
整流单元10由输入保护电阻FR1和整流桥D1组成，输入保护电阻FR1的输入端和整流桥D1的3脚分别连接DALI总线DA1、DA2，输入保护电阻FR1输出端连接整流桥D1的1脚，整流桥D1的4脚接地。The rectifier unit 10 is composed of an input protection resistor FR1 and a rectifier bridge D1. The input end of the input protection resistor FR1 and pin 3 of the rectifier bridge D1 are respectively connected to the DALI bus DA1 and DA2, and the output end of the input protection resistor FR1 is connected to pin 1 of the rectifier bridge D1. Pin 4 of the rectifier bridge D1 is grounded.
整流桥D1的输出端(2脚)接入电压电流限制模块201的输入端和MOS管Q2的漏极；电压电流限制模块201的输出端连接双通道数字隔离器VIA脚(第一通道输入端)；第四电阻R6和电容C1并联后，一端接MOS管Q2的栅极和双通道数字隔离器的VOB脚(第二通道输出端)，另一端接地，第四电阻R6用于为MOS管Q2提供稳定的启动电压，电容C1用于减小电流干扰；MOS管Q2的源极接地，双通道数字隔离器GND1脚和GND2脚接地,双通道数字隔离器VOA脚(第一通道输出端)连接RX信号，双通道数字隔离器的VIB脚(第二通道输入端)连接TX信号，双通道数字隔离器VDD1脚和VDD2脚分别连接输入电压VCCI和VCC。The output terminal (2 pins) of the rectifier bridgeD1 is connected to the input terminal of the voltage and current limiting module 201 and the drain of the MOS transistor Q2; end); after the fourth resistor R6 and capacitor C1 are connected in parallel, one end is connected to the gate of the MOS transistor Q2 and the VOB pin (the output end of the second channel) of the dual-channel digital isolator, and the other end is grounded, and the fourth resistor R6 is used for The MOS tube Q2 provides a stable start-up voltage, and the capacitor C1 is used to reduce current interference; the source of the MOS tube Q2 is grounded, the GND1 and GND2 pins of the dual-channel digital isolator are grounded, and the VOA pin of the dual-channel digital isolator (the first The first channel output terminal) is connected to the RX signal, the VIB pin (the second channel input terminal) of the dual-channel digital isolator is connected to the TX signal, and the VDD1 pin and VDD2 pin of the dual-channel digital isolator are respectively connected to the input voltage VCCI and VCC.
电平处理单元20中还设有一个稳压二极管D2，稳压二极管D2的阳极接地，阴极接电压电流限制模块201的输出端，以保证双通道数字隔离器VIA脚的输入电平处于规定的范围内。A Zener diode D2 is also provided in the level processing unit 20, the anode of the Zener diode D2 is grounded, and the cathode is connected to the output end of the voltage and current limiting module 201, so as to ensure that the input level of the VIA pin of the dual-channel digital isolator is at the specified level. In the range.
下面结合图2介绍电路的工作原理：The working principle of the circuit is introduced below in conjunction with Figure 2:
当DALI总线发送信号时，TX信号保持低电平，MOS管Q2截止，DALI总线的DA1经整流单元整流后，经整流桥对输入信号整流后，由电压电流限制模块201限流进入双通道数字隔离器的第一通道，由第一通道在内部进行隔离后输出，RX信号的电平高低与DALI总线的DA1的输入电平一致，只是高电平经电压电流限制模块201后降至5V左右。When the DALI bus sends signals, the TX signal remains low, and the MOS transistor Q2 is cut off. After the DA1 of the DALI bus is rectified by the rectifier unit, the input signal is rectified by the rectifier bridge, and the current is limited by the voltage and current limiting module 201 to enter the dual-channel digital signal. The first channel of the isolator is internally isolated by the first channel and then output. The level of the RX signal is consistent with the input level of DA1 of the DALI bus, but the high level is reduced to about 5V after the voltage and current limiting module 201 .
DALI总线接收信号时，发送端TX的高低电平将控制MOS管Q2的导通或截止，使DALI总线的DA1被拉低为低电平或维持高电平，具体地说，当发送端TX发送高电平时，信号经过双通道数字隔离器的第二通道输入，进行内部隔离后输入MOS管Q2的栅极，使MOS管Q2导通，DALI总线上的高电平被拉低；当发送端TX发送低电平时，此时MOS管Q2截止，DALI总线上保持高电平。When the DALI bus receives signals, the high and low levels of the sending end TX will control the conduction or cut-off of the MOS transistor Q2, so that the DA1 of the DALI bus is pulled down to a low level or maintained at a high level. Specifically, when the sending end TX When sending a high level, the signal is input through the second channel of the dual-channel digital isolator, and then input to the gate of the MOS transistor Q2 after internal isolation, so that the MOS transistor Q2 is turned on, and the high level on the DALI bus is pulled low; when sending When the terminal TX sends a low level, the MOS transistor Q2 is turned off at this time, and the DALI bus maintains a high level.
本实用新型，采用集成DC/DC转换器的双通道数字隔离器不仅实现了信号隔离，同时，双通道数字隔离器不依靠DALI总线提供工作电流，DALI总线仅提供低至0.2mA电流用于信号传递，因此，降低了传送信号延时和DALI接口电路的供电需求，同时提高了DALI接口电路的可靠性。In the utility model, the dual-channel digital isolator with an integrated DC/DC converter not only realizes signal isolation, but also does not rely on the DALI bus to provide working current, and the DALI bus only provides a current as low as 0.2mA for signal Passing, therefore, reduces the transmission signal delay and power requirements of the DALI interface circuit while increasing the reliability of the DALI interface circuit.
本实用新型不局限于上述最佳实施方式，任何人应该得知在本实用新型的启示下作出的结构变化，凡是与本实用新型明具有相同或相近的技术方案，均落入本实用新型的保护范围之内。The utility model is not limited to the above-mentioned best implementation mode, and anyone should know that the structural changes made under the inspiration of the utility model, and all technical solutions that are the same as or similar to the utility model, all fall into the scope of the utility model. within the scope of protection.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520769246.5UCN204929366U (en) | 2015-09-30 | 2015-09-30 | A DALI interface circuit |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520769246.5UCN204929366U (en) | 2015-09-30 | 2015-09-30 | A DALI interface circuit |
| Publication Number | Publication Date |
|---|---|
| CN204929366Utrue CN204929366U (en) | 2015-12-30 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520769246.5UExpired - LifetimeCN204929366U (en) | 2015-09-30 | 2015-09-30 | A DALI interface circuit |
| Country | Link |
|---|---|
| CN (1) | CN204929366U (en) |
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| CN106067803A (en)* | 2016-07-07 | 2016-11-02 | 上海兴珠信息科技有限公司 | The level-conversion circuit of digital addressable lighting interface DALI |
| CN108684119A (en)* | 2018-06-20 | 2018-10-19 | 苏州欧普照明有限公司 | A kind of hardware circuit based on DALI signal detections |
| CN109445355A (en)* | 2018-12-13 | 2019-03-08 | 中国电子科技集团公司第五十八研究所 | A kind of isolated form sampling SIP |
| CN109445505A (en)* | 2018-11-26 | 2019-03-08 | 珠海世讯科技有限公司 | A kind of bus-powered circuit of DALI |
| CN113661786A (en)* | 2019-03-28 | 2021-11-16 | 昕诺飞控股有限公司 | Power Configuration Across Isolation Barriers |
| CN113891538A (en)* | 2021-09-29 | 2022-01-04 | 深圳民爆光电股份有限公司 | A DALI Addressable Intelligent Sensing Control System |
| CN114928259A (en)* | 2022-05-06 | 2022-08-19 | 深圳市晟瑞科技有限公司 | Communication interface circuit and power consumption device |
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| CN106067803A (en)* | 2016-07-07 | 2016-11-02 | 上海兴珠信息科技有限公司 | The level-conversion circuit of digital addressable lighting interface DALI |
| CN106067803B (en)* | 2016-07-07 | 2023-09-08 | 浙江优联智能科技有限公司 | Level conversion circuit of digital addressable lighting interface DALI |
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| CN108684119B (en)* | 2018-06-20 | 2023-07-18 | 苏州欧普照明有限公司 | Hardware circuit based on DALI signal detection |
| CN109445505A (en)* | 2018-11-26 | 2019-03-08 | 珠海世讯科技有限公司 | A kind of bus-powered circuit of DALI |
| CN109445505B (en)* | 2018-11-26 | 2024-01-02 | 珠海世讯科技有限公司 | DALI bus power supply circuit |
| CN109445355A (en)* | 2018-12-13 | 2019-03-08 | 中国电子科技集团公司第五十八研究所 | A kind of isolated form sampling SIP |
| CN113661786B (en)* | 2019-03-28 | 2024-04-05 | 昕诺飞控股有限公司 | Power supply configuration across isolation barrier |
| CN113661786A (en)* | 2019-03-28 | 2021-11-16 | 昕诺飞控股有限公司 | Power Configuration Across Isolation Barriers |
| US12016101B2 (en) | 2019-03-28 | 2024-06-18 | Signify Holding, B.V. | Power supply configuration across isolation barrier |
| CN113891538A (en)* | 2021-09-29 | 2022-01-04 | 深圳民爆光电股份有限公司 | A DALI Addressable Intelligent Sensing Control System |
| CN114928259A (en)* | 2022-05-06 | 2022-08-19 | 深圳市晟瑞科技有限公司 | Communication interface circuit and power consumption device |
| CN114928259B (en)* | 2022-05-06 | 2023-12-29 | 深圳市晟瑞科技有限公司 | Communication interface circuit and power utilization device |
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| CN204929366U (en) | A DALI interface circuit | |
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |