技术领域technical field
本实用新型涉及集成电路技术领域，尤其涉及一种对电流输出信号进行电流频率转换信号处理的电容充放电控制模块以及电流频率转换电路。The utility model relates to the technical field of integrated circuits, in particular to a capacitor charging and discharging control module and a current-frequency conversion circuit for performing current-frequency conversion signal processing on current output signals.
背景技术Background technique
电流信号输出是传感器常用的信号输出方式，对电流输出信号的处理常用的方法有电流电压转换和电流频率转换。Current signal output is a commonly used signal output mode of sensors, and the commonly used methods for processing current output signals include current-voltage conversion and current-frequency conversion.
电流电压转换方式通过引入电阻实现电流到电压的转换，转换后输出信号为电压信号。由于输出电压信号仍为模拟信号，需要再经过模数转换器变成数字信号，提供给MCU(MicroControl Unit)处理。这种处理方式电路结构复杂，需要的中间过程多，引入噪声大。当需要高精度的信号处理时，还需要增加额外的电路进行降噪处理，需要更高的成本。The current-voltage conversion method realizes the conversion from current to voltage by introducing a resistor, and the output signal after conversion is a voltage signal. Since the output voltage signal is still an analog signal, it needs to be converted into a digital signal through an analog-to-digital converter and provided to the MCU (MicroControl Unit) for processing. This processing method has a complex circuit structure, requires many intermediate processes, and introduces large noise. When high-precision signal processing is required, additional circuits need to be added for noise reduction processing, which requires higher costs.
电流频率转换方式通过引入积分电容，通过电流对积分电容的周期性充放电实现电流到频率的转换，转换后的频率信号为幅值与电源电压相同的方波信号，可由MCU的计数器或定时器直接处理，电路结构简单，参见美国专利公开号为US4109168的专利申请。但其对积分电容进行放电的时间会产生误差，因此会引入一个非线性误差；当输出频率越高时，这个非线性误差越大，影响信号处理的精度。The current frequency conversion method introduces the integration capacitor, and realizes the conversion from current to frequency through the periodic charge and discharge of the current to the integration capacitor. The converted frequency signal is a square wave signal with the same amplitude as the power supply voltage, which can be controlled by the counter or timer of the MCU. Direct processing, simple circuit structure, refer to the patent application of US Patent Publication No. US4109168. However, the time for discharging the integral capacitor will generate an error, so a nonlinear error will be introduced; when the output frequency is higher, the nonlinear error will be larger, which will affect the accuracy of signal processing.
因此，如何实现电流频率转换且避免电容放电引入的非线性误差，提高信号处理的精度成为亟待解决的问题。Therefore, how to realize the current-frequency conversion and avoid the nonlinear error introduced by the capacitor discharge, and improve the accuracy of the signal processing has become an urgent problem to be solved.
实用新型内容Utility model content
本实用新型的目的在于，针对现有技术中电流频率转换方式存在的积分电容放电会引入非线性误差，影响信号处理的精度的技术问题，提供一种处理过程简化、电路结构简单的电容充放电控制模块以及电流频率转换电路，实现电流频率转换且电容放电不会引入非线性误差，同时提高信号处理的精度。The purpose of this utility model is to provide a capacitor charging and discharging with simplified processing and simple circuit structure for the technical problem that the integral capacitor discharge in the current frequency conversion method in the prior art will introduce nonlinear errors and affect the accuracy of signal processing. The control module and the current-frequency conversion circuit realize the current-frequency conversion without introducing nonlinear errors by capacitor discharge, and at the same time improve the accuracy of signal processing.
为实现上述目的，本实用新型提供了一种电容充放电控制模块，适用于积分电路，包括：一接入控制单元以及一放电控制单元；所述接入控制单元，用于根据一第一控制信号控制一第一切换电容与所述积分电路中的积分电容并联后接入电流频率转换电路或根据一第二控制信号控制一第二切换电容与所述积分电容并联后接入电流频率转换电路；所述放电控制单元，用于根据所述第二控制信号控制所述第一切换电容放电或根据所述第一控制信号控制所述第二切换电容进行放电；其中，所述第一控制信号与所述第二控制信号为非此即彼选择控制信号。In order to achieve the above object, the utility model provides a capacitor charge and discharge control module, which is suitable for the integral circuit, including: an access control unit and a discharge control unit; the access control unit is used to The signal controls a first switching capacitor to be connected in parallel with the integrating capacitor in the integrating circuit to be connected to the current-frequency conversion circuit, or a second control signal is used to control a second switching capacitor to be connected in parallel to the integrating capacitor to be connected to the current-frequency converting circuit ; The discharge control unit is configured to control the discharge of the first switched capacitor according to the second control signal or control the discharge of the second switched capacitor according to the first control signal; wherein, the first control signal The second control signal is an either-or selection control signal.
为实现上述目的，本实用新型还提供了一种电流频率转换电路，包括：一积分电路、至少一第一切换电容和一第二切换电容、一比较器、一逻辑控制模块以及一本实用新型所述的电容充放电控制模块，所述积分电路包括一积分电容与一运算放大器；所述运算放大器的第一输入端为所述电流频率转换电路的输入端，用以接收一待转换电流信号，其第二输入端接地或接一参考电压源，其输出端电学连接至所述比较器的第一输入端；所述积分电容并接在所述运算放大器的第一输入端与输出端之间；所述比较器的第一输入端与所述运算放大器的输出端电学连接，其第二输入端与一基准电压源电学连接，其输出端电学连接至所述逻辑控制模块的输入端，所述比较器用于根据其第一输入端输入电压与第二输入端输入电压的比较结果控制其输出端的电平翻转；所述逻辑控制模块的第一输出端电学连接至所述电容充放电控制模块的所述接入控制单元以及放电控制单元，用于根据所述比较器的输出电平输出一第一控制信号，使所述接入控制单元控制所述第一切换电容与所述积分电容并联并与所述运算放大器组合成积分器对所述待转换电流信号进行积分，同时使所述放电控制单元控制所述第二切换电容进行放电；所述逻辑控制模块的第二输出端电学连接至所述电容充放电控制模块的所述接入控制单元以及放电控制单元，用于根据所述比较器的输出电平输出一第二控制信号，使所述接入控制单元控制所述第二切换电容与所述积分电容并联并与所述运算放大器组合成积分器对所述待转换电流信号进行积分，同时使所述放电控制单元控制所述第一切换电容进行放电，其中，所述第一控制信号与所述第二控制信号为非此即彼选择控制信号；所述逻辑控制模块的第三输出端为所述电流频率转换电路的输出端，用于输出转换后的频率信号。In order to achieve the above object, the utility model also provides a current-frequency conversion circuit, including: an integrating circuit, at least a first switching capacitor and a second switching capacitor, a comparator, a logic control module and a utility model In the capacitor charging and discharging control module, the integration circuit includes an integration capacitor and an operational amplifier; the first input terminal of the operational amplifier is the input terminal of the current-frequency conversion circuit for receiving a current signal to be converted , its second input terminal is grounded or connected to a reference voltage source, its output terminal is electrically connected to the first input terminal of the comparator; the integrating capacitor is connected in parallel between the first input terminal and the output terminal of the operational amplifier Between; the first input end of the comparator is electrically connected to the output end of the operational amplifier, its second input end is electrically connected to a reference voltage source, and its output end is electrically connected to the input end of the logic control module, The comparator is used to control the level inversion of the output terminal according to the comparison result of the input voltage at the first input terminal and the input voltage at the second input terminal; the first output terminal of the logic control module is electrically connected to the capacitor charge and discharge control The access control unit and the discharge control unit of the module are used to output a first control signal according to the output level of the comparator, so that the access control unit controls the first switching capacitor and the integration capacitor connected in parallel and combined with the operational amplifier to form an integrator to integrate the current signal to be converted, and at the same time make the discharge control unit control the second switching capacitor to discharge; the second output terminal of the logic control module is electrically connected The access control unit and the discharge control unit of the capacitor charge and discharge control module are configured to output a second control signal according to the output level of the comparator, so that the access control unit controls the second The switching capacitor is connected in parallel with the integrating capacitor and is combined with the operational amplifier to form an integrator to integrate the current signal to be converted, and at the same time make the discharge control unit control the first switching capacitor to discharge, wherein the second A control signal and the second control signal are either-or selection control signals; the third output terminal of the logic control module is the output terminal of the current-frequency conversion circuit for outputting the converted frequency signal.
本实用新型的优点在于：通过电流频率转换电路将电流信号直接转换为数字处理器可处理的方波频率信号，电路结构简单，精度高，成本低；由于该实用新型采用两个或两个以上的切换电容，充电和放电过程交替进行，因此切换电容可以实现无时间间隙切换，一个切换电容参与积分时，另一个切换电容进行放电，不存在电容放电时间不足引入的非线性误差，同时也降低了对放大器响应速率的要求。并且，由于所述逻辑控制模块根据比较器的输出电平自动选择一输出端输出控制信号，因此其内部无需设置定时器控制逻辑，电路实现比较简单。The utility model has the advantages of: the current signal is directly converted into a square wave frequency signal that can be processed by a digital processor through the current frequency conversion circuit, the circuit structure is simple, the precision is high, and the cost is low; because the utility model adopts two or more The switching capacitor, charging and discharging process alternately, so the switching capacitor can realize switching without time gap, when one switching capacitor participates in the integration, the other switching capacitor discharges, there is no nonlinear error caused by insufficient capacitor discharge time, and it also reduces The requirements for the response rate of the amplifier are met. Moreover, since the logic control module automatically selects an output terminal to output the control signal according to the output level of the comparator, there is no need to set timer control logic inside it, and the circuit implementation is relatively simple.
附图说明Description of drawings
图1，本实用新型所述的电流频率转换电路的原理示意图；Fig. 1, the schematic diagram of the principle of the current-frequency conversion circuit described in the utility model;
图2，本实用新型所述的电容充放电控制模块的原理示意图；Fig. 2 is a schematic diagram of the principle of the capacitor charging and discharging control module described in the present invention;
图3，本实用新型所述的电流频率转换电路第一实施例的电路图；Fig. 3, the circuit diagram of the first embodiment of the current-frequency conversion circuit described in the utility model;
图4为图3所示电路一实施例的工作时序图；Fig. 4 is the working timing diagram of an embodiment of the circuit shown in Fig. 3;
图5为图3所示电路另一实施例的工作时序图；Fig. 5 is the working timing diagram of another embodiment of the circuit shown in Fig. 3;
图6，本实用新型所述的电流频率转换电路第二实施例的电路图；Fig. 6, the circuit diagram of the second embodiment of the current-frequency conversion circuit described in the present invention;
图7，本实用新型所述的电流频率转换电路第三实施例的电路图；Fig. 7, the circuit diagram of the third embodiment of the current-frequency conversion circuit described in the present invention;
图8，本实用新型所述的电流频率转换电路第四实施例的电路图。Fig. 8 is a circuit diagram of the fourth embodiment of the current-frequency conversion circuit described in the present invention.
具体实施方式Detailed ways
以下结合附图对本实用新型提供的电容充放电控制模块以及电流频率转换电路做详细说明。The capacitor charging and discharging control module and the current-frequency conversion circuit provided by the present invention will be described in detail below in conjunction with the accompanying drawings.
参考图1，本实用新型所述的电流频率转换电路的原理示意图，所述电流频率转换电路包括：一电容充放电控制模块12，一积分电路，至少一第一切换电容C1和一第二切换电容C2，一比较器A2以及一逻辑控制模块14；其中，所述积分电路包括一运算放大器A1以及一积分电容C0。Referring to Fig. 1, the schematic diagram of the principle of the current-frequency conversion circuit described in the present invention, the current-frequency conversion circuit includes: a capacitor charging and discharging control module 12, an integrating circuit, at least a first switching capacitor C1 and a second switching Capacitor C2, a comparator A2 and a logic control module 14; wherein, the integrating circuit includes an operational amplifier A1 and an integrating capacitor C0.
参考图2，本实用新型所述的电容充放电控制模块的原理示意图；所述电容充放电控制模块12适用于电流频率转换电路的积分电路，包括：一接入控制单元22以及一放电控制单元24。图2仅示意出接入控制单元22以及放电控制单元24与积分电容C0、第一切换电容C1、第二切换电容C2的电性连接方式，并不用于具体限定接入控制单元22以及放电控制单元24与各电容的相对位置。Referring to Fig. 2, the schematic diagram of the principle of the capacitor charge and discharge control module described in the present invention; the capacitor charge and discharge control module 12 is applicable to the integration circuit of the current frequency conversion circuit, including: an access control unit 22 and a discharge control unit twenty four. FIG. 2 only shows the electrical connections between the access control unit 22 and the discharge control unit 24 and the integrating capacitor C0, the first switched capacitor C1, and the second switched capacitor C2, and is not used to specifically limit the access control unit 22 and the discharge control unit. The relative position of unit 24 and each capacitor.
所述接入控制单元22，用于根据一第一控制信号控制第一切换电容C1与所述积分电路中的积分电容C0并联，或根据一第二控制信号控制第二切换电容C2与积分电容C0并联。其中，第一控制信号与第二控制信号为非此即彼选择控制信号，也即同一时刻仅有一控制信号为有效控制信号，另一控制信号为无效控制信号。The access control unit 22 is configured to control the parallel connection between the first switching capacitor C1 and the integrating capacitor C0 in the integration circuit according to a first control signal, or control the second switching capacitor C2 and the integrating capacitor according to a second control signal C0 is connected in parallel. Wherein, the first control signal and the second control signal are either-or selection control signals, that is, only one control signal is an effective control signal at the same time, and the other control signal is an invalid control signal.
所述放电控制单元24，用于根据所述第二控制信号控制第一切换电容C1进行放电，或根据所述第一控制信号控制所述第二切换电容C2进行放电。The discharge control unit 24 is configured to control the first switching capacitor C1 to discharge according to the second control signal, or control the second switching capacitor C2 to discharge according to the first control signal.
也即，当所述第一切换电容C1与所述积分电容C0并联后，所述第二切换电容C2进行放电；当所述第二切换电容C2与所述积分电容C0并联后，所述第一切换电容C1进行放电。That is, when the first switching capacitor C1 is connected in parallel with the integrating capacitor C0, the second switching capacitor C2 is discharged; when the second switching capacitor C2 is connected in parallel with the integrating capacitor C0, the first A switched capacitor C1 is discharged.
作为可选的实施方式，所述接入控制单元22进一步包括一第一开关子单元221以及一第二开关子单元222，第一开关子单元221以及第二开关子单元222根据外部控制信号导通或断开，外部控制信号为第一控制信号或第二控制信号。具体而言，所述第一开关子单元221电气上与所述第一切换电容C1串联，用于根据第一控制信号控制所述第一切换电容C1与所述积分电容C0并联。所述第二开关子单元222电气上与所述第二切换电容C2串联，用于根据第二控制信号控制所述第二切换电容C2与所述积分电容C0并联。作为优选的实施方式，第一控制信号为第一时钟控制信号，第二控制信号为第二时钟控制信号，所述第一时钟控制信号与所述第二时钟控制信号为两相不交叠时钟控制信号，也即同一时刻第一开关子单元221与第二开关子单元222仅有其中之一处于导通状态时，另一个处于断开状态。As an optional implementation manner, the access control unit 22 further includes a first switch subunit 221 and a second switch subunit 222, and the first switch subunit 221 and the second switch subunit 222 guide On or off, the external control signal is the first control signal or the second control signal. Specifically, the first switching subunit 221 is electrically connected in series with the first switching capacitor C1, and is used to control the first switching capacitor C1 to be connected in parallel with the integrating capacitor C0 according to a first control signal. The second switch subunit 222 is electrically connected in series with the second switching capacitor C2, and is used for controlling the second switching capacitor C2 to be connected in parallel with the integrating capacitor C0 according to a second control signal. As a preferred embodiment, the first control signal is a first clock control signal, the second control signal is a second clock control signal, and the first clock control signal and the second clock control signal are two-phase non-overlapping clocks The control signal, that is, when only one of the first switch subunit 221 and the second switch subunit 222 is in the on state at the same time, the other is in the off state.
作为可选的实施方式，所述放电控制单元24进一步包括一第三开关子单元241以及一第四开关子单元242，第三开关子单元241以及第四开关子单元242也为根据外部控制信号导通或断开，外部控制信号为第一控制信号或第二控制信号。具体而言，所述第三开关子单元241电气上与所述第一切换电容C1并联，用于根据所述第二控制信号控制所述第一切换电容C1进行放电。所述第四开关子单元242电气上与所述第二切换电容C2并联，用于根据所述第一控制信号控制所述第二切换电容C2进行放电。作为优选的实施方式，第一控制信号为第一时钟控制信号，第二控制信号为第二时钟控制信号，所述第一时钟控制信号与所述第二时钟控制信号为两相不交叠时钟控制信号，也即同一时刻第三开关子单元241以及第四开关子单元242仅有其中之一处于导通状态时，另一个处于断开状态；且第一开关子单元221与第四开关子单元242均受第一时钟控制信号控制，同时导通、同时断开，第二开关子单元222与第三开关子单元241均受第二时钟控制信号控制，同时导通、同时断开。As an optional implementation, the discharge control unit 24 further includes a third switch subunit 241 and a fourth switch subunit 242, and the third switch subunit 241 and the fourth switch subunit 242 also operate according to the external control signal On or off, the external control signal is the first control signal or the second control signal. Specifically, the third switch subunit 241 is electrically connected in parallel with the first switching capacitor C1, and is used for controlling the first switching capacitor C1 to discharge according to the second control signal. The fourth switching subunit 242 is electrically connected in parallel with the second switching capacitor C2, and is used for controlling the second switching capacitor C2 to discharge according to the first control signal. As a preferred embodiment, the first control signal is a first clock control signal, the second control signal is a second clock control signal, and the first clock control signal and the second clock control signal are two-phase non-overlapping clocks Control signal, that is, when only one of the third switch subunit 241 and the fourth switch subunit 242 is in the on state at the same time, the other is in the off state; and the first switch subunit 221 and the fourth switch subunit 242 The unit 242 is controlled by the first clock control signal, and is turned on and turned off at the same time. The second switch subunit 222 and the third switch subunit 241 are controlled by the second clock control signal, and is turned on and off at the same time.
继续参考图1，所述运算放大器A1的第一输入端为所述电流频率转换电路的输入端，用以接收一待转换电流信号I，其第二输入端接地，其输出端U1电学连接至所述比较器A2的第一输入端。在其它实施方式中，运算放大器A1的第二输入端可以接到其可接受电压范围内的任意一参考电压源，该参考电压源的参考电压可以为某一固定电压或地线电压。Continuing to refer to FIG. 1, the first input terminal of the operational amplifier A1 is the input terminal of the current-frequency conversion circuit for receiving a current signal I to be converted, its second input terminal is grounded, and its output terminal U1 is electrically connected to The first input of the comparator A2. In other embodiments, the second input terminal of the operational amplifier A1 may be connected to any reference voltage source within an acceptable voltage range, and the reference voltage of the reference voltage source may be a fixed voltage or a ground voltage.
所述积分电容C0并接在所述运算放大器A1的第一输入端与输出端U1之间。电容充放电控制模块12控制第一切换电容C1和一第二切换电容C2周期性交替与积分电容C0并联，从而使A1、C0与C1或C2组合成积分器，周期性地对所述待转换电流信号I进行积分；积分所得电压V1输出至所述比较器A2的第一输入端。The integrating capacitor C0 is connected in parallel between the first input terminal and the output terminal U1 of the operational amplifier A1. Capacitor charging and discharging control module 12 controls the first switching capacitor C1 and a second switching capacitor C2 to be periodically connected in parallel with the integrating capacitor C0, so that A1, C0 and C1 or C2 are combined to form an integrator, and the to-be-converted The current signal I is integrated; the integrated voltage V1 is output to the first input terminal of the comparator A2.
所述比较器A2的第一输入端与所述运算放大器A1的输出端U1电学连接，其第二输入端与一基准电压源VREF电学连接，其输出端U2电学连接至所述逻辑控制模块14的输入端，所述比较器A2用于根据其第一输入端输入电压与第二输入端输入电压的比较结果控制其输出端U2的电平VO翻转。例如，当第一输入端输入电压大于第二输入端输入电压，即UV1>UVREF时，输出端U2的电平VO由高电平翻转为低电平，当第一输入端输入电压小于第二输入端输入电压，即UV1<UVREF时，输出端的电平VO由低电平翻转为高电平；从而控制所述逻辑控制模块14输出的控制信号相应改变。The first input terminal of the comparator A2 is electrically connected to the output terminal U1 of the operational amplifier A1, its second input terminal is electrically connected to a reference voltage source VREF, and its output terminal U2 is electrically connected to the logic control module 14 The input terminal of the comparator A2 is used to control the level VO of the output terminal U2 to flip according to the comparison result of the input voltage at the first input terminal and the input voltage at the second input terminal. For example, when the input voltage at the first input terminal is greater than the input voltage at the second input terminal, that is, when UV1 >UVREF , the level VO of the output terminal U2 is turned from high level to low level; when the input voltage at the first input terminal is less than When the voltage is input to the second input terminal, that is, when UV1 <UVREF , the level VO of the output terminal is reversed from low level to high level; thus, the control signal output by the logic control module 14 is changed accordingly.
任一切换电容C1或C2接入积分器后，均与积分电容C0重新分配电荷，使得比较器A2第一输入端的电压值变为电荷重新分配后的电压值。电荷分配公式为：V1＝VREF·C0/(C0+C1)或V1＝VREF·C0/(C0+C2)。当C1和C2容值相同时，任一切换电容C1或C2接入积分器后与积分电容C0重新分配电荷所得到的电压值都相等；其中，当C1＝C2＝C0时，重新分配电荷后所得电压值等于基准电压VREF的二分之一；当C1＝C2>C0时，重新分配电荷后所得电压值小于基准电压VREF的二分之一；当C1＝C2<C0时，重新分配电荷后所得电压值大于基准电压VREF的二分之一。当C1和C2容值不相同时，不同切换电容C1或C2接入积分器后与积分电容C0重新分配电荷所得到的电压值不相等，但仍可根据上述电荷分配公式以及相应电容值预先确定。After any switched capacitor C1 or C2 is connected to the integrator, it redistributes the charges with the integrating capacitor C0, so that the voltage value at the first input terminal of the comparator A2 becomes the voltage value after the redistributed charges. The charge distribution formula is: V1=VREF·C0/(C0+C1) or V1=VREF·C0/(C0+C2). When the capacitances of C1 and C2 are the same, any switching capacitor C1 or C2 is connected to the integrator and the voltage value obtained by redistribution of charge with the integration capacitor C0 is equal; where, when C1=C2=C0, after redistribution of charge The obtained voltage value is equal to one-half of the reference voltage VREF; when C1=C2>C0, the voltage value obtained after redistribution of charges is less than one-half of the reference voltage VREF; when C1=C2<C0, after redistribution of charges The resulting voltage value is greater than one-half of the reference voltage VREF. When the capacitance values of C1 and C2 are not the same, the voltage values obtained by redistribution of charge between different switching capacitors C1 or C2 after being connected to the integrator and the integrating capacitor C0 are not equal, but it can still be determined in advance according to the above charge distribution formula and the corresponding capacitance value .
所述逻辑控制模块14的第一输出端分别电学连接至所述电容充放电控制模块12的所述接入控制单元22以及放电控制单元24，用于根据所述比较器A2的输出电平VO输出一第一控制信号，使所述接入控制单元22控制所述第一切换电容C1与所述积分电容C0并联，第一切换电容C1、积分电容C0与运算放大器A1组合成积分器对所述待转换电流信号I进行积分；同时第一控制信号使所述放电控制单元24控制所述第二切换电容C2进行放电。The first output terminal of the logic control module 14 is respectively electrically connected to the access control unit 22 and the discharge control unit 24 of the capacitor charge and discharge control module 12, for Outputting a first control signal, so that the access control unit 22 controls the first switching capacitor C1 to be connected in parallel with the integrating capacitor C0, and the first switching capacitor C1, the integrating capacitor C0 and the operational amplifier A1 are combined to form an integrator for all The to-be-converted current signal I is integrated; at the same time, the first control signal enables the discharge control unit 24 to control the second switching capacitor C2 to discharge.
所述逻辑控制模块14的第二输出端分别电学连接至所述电容充放电控制模块12的所述接入控制单元22以及放电控制单元24，用于根据所述比较器A2的输出电平VO输出一第二控制信号，使所述接入控制单元22控制所述第二切换电容C2与所述积分电容C0并联，第二切换电容C2、积分电容C0与运算放大器A1组合成积分器对所述待转换电流信号I进行积分；同时第二控制信号使所述放电控制单元24控制所述第一切换电容C1进行放电。The second output terminal of the logic control module 14 is electrically connected to the access control unit 22 and the discharge control unit 24 of the capacitor charge and discharge control module 12 respectively, for Outputting a second control signal, so that the access control unit 22 controls the parallel connection of the second switching capacitor C2 and the integrating capacitor C0, and the second switching capacitor C2, the integrating capacitor C0 and the operational amplifier A1 are combined to form an integrator for all The to-be-converted current signal I is integrated; at the same time, the second control signal enables the discharge control unit 24 to control the first switching capacitor C1 to discharge.
其中，所述第一控制信号与所述第二控制信号为非此即彼选择控制信号，也即同一时刻仅有一控制信号为有效控制信号，另一控制信号为无效控制信号。作为可选的实施方式，所述第一控制信号为第一时钟控制信号，所述第二控制信号为第二时钟控制信号，所述第一时钟控制信号与所述第二时钟控制信号为两相不交叠时钟控制信号。Wherein, the first control signal and the second control signal are either-or selection control signals, that is, only one control signal is an effective control signal at the same time, and the other control signal is an invalid control signal. As an optional implementation manner, the first control signal is a first clock control signal, the second control signal is a second clock control signal, and the first clock control signal and the second clock control signal are two Phase non-overlapping clock control signals.
所述逻辑控制模块14的第三输出端为所述电流频率转换电路的输出端，用于输出经过转换后的频率信号。The third output terminal of the logic control module 14 is the output terminal of the current-frequency conversion circuit for outputting the converted frequency signal.
具体而言，当所述逻辑控制模块14发出第一控制信号时，第一切换电容C1与放电控制单元24断开后通过接入控制单元22与积分电容C0并联并与所述运算放大器A1形成积分器，第二切换电容C2与积分器断开并接入放电控制单元24进行放电；此时C1、C0与A1组成的积分器输出电压V1低于基准电压VREF，比较器A2的输出电平VO为高电平，积分器对输入的待转换电流信号I进行积分；当积分所得电压V1达到基准电压VREF时，VO翻转为低电平，此时所述逻辑控制模块14发出第二控制信号；当所述逻辑控制模块14发出第二控制信号时，第二切换电容C2与放电控制单元24断开后通过接入控制单元22与积分电容C0并联并与所述运算放大器A1形成积分器，第一切换电容C1与积分器断开并接入放电控制单元24进行放电；当C2和C0进行电荷重新分配后，C2、C0与A1组成的积分器输出电压V1下降到低于基准电压VREF，比较器A2的输出VO翻转为高电平，积分器对输入的待转换电流信号I进行积分；当积分所得电压V1达到基准电压VREF时，VO翻转为低电平，此时所述逻辑控制模块14发出第一控制信号；在输入的待转换电流信号I持续期间内，上述过程周期性重复，从而将输入的待转换电流信号I转化为频率信号输出。Specifically, when the logic control module 14 sends out the first control signal, the first switched capacitor C1 is disconnected from the discharge control unit 24 and connected in parallel with the integration capacitor C0 through the access control unit 22 to form a circuit with the operational amplifier A1. Integrator, the second switching capacitor C2 is disconnected from the integrator and connected to the discharge control unit 24 for discharge; at this time, the output voltage V1 of the integrator composed of C1, C0 and A1 is lower than the reference voltage VREF, and the output level of the comparator A2 VO is at a high level, and the integrator integrates the input current signal I to be converted; when the integrated voltage V1 reaches the reference voltage VREF, VO turns to a low level, and the logic control module 14 sends out a second control signal at this time ; When the logic control module 14 sends out the second control signal, the second switching capacitor C2 is disconnected from the discharge control unit 24 and connected in parallel with the integration capacitor C0 through the access control unit 22 and forms an integrator with the operational amplifier A1, The first switched capacitor C1 is disconnected from the integrator and connected to the discharge control unit 24 for discharge; when C2 and C0 perform charge redistribution, the output voltage V1 of the integrator composed of C2, C0 and A1 drops below the reference voltage VREF, The output VO of the comparator A2 flips to a high level, and the integrator integrates the input current signal I to be converted; when the integrated voltage V1 reaches the reference voltage VREF, VO flips to a low level, and the logic control module at this time 14 sends out the first control signal; during the duration of the input current signal I to be converted, the above process is repeated periodically, so that the input current signal I to be converted is converted into a frequency signal for output.
作为优选的实施方式，第一切换电容C1和第二切换电容C2的电容值相同。当C1和C2容值相同时，任一切换电容C1或C2接入积分器后与积分电容C0重新分配电荷所得到的电压值都相等；则积分器对所述待转换电流信号I从该相同电压值到基准电压VREF的积分时间也相等，从而所述逻辑控制模块14的第三输出端输出的转换后的频率信号周期相同。当C1和C2容值不相同时，不同切换电容C1或C2接入积分器后与积分电容C0重新分配电荷所得到的电压值不相等；则积分器对所述待转换电流信号I从不同电压值到基准电压VREF的积分时间不相等。在积分时间不相等的情况下可以在频率输出之前增加分频电路，以使得最后的输出信号为周期相等的频率信号；如果该分频电路为二分频电路，其输出信号的周期为C1和C2分别接入积分器的两个相邻积分周期之和。经过二分频电路分频之后，输出的转换后的频率信号周期相同。As a preferred implementation manner, the capacitance values of the first switching capacitor C1 and the second switching capacitor C2 are the same. When the capacitance values of C1 and C2 are the same, any switching capacitor C1 or C2 is connected to the integrator and the voltage value obtained by redistributing the charge with the integrating capacitor C0 is equal; The integration time from the voltage value to the reference voltage VREF is also equal, so that the period of the converted frequency signal output by the third output terminal of the logic control module 14 is the same. When the capacitance values of C1 and C2 are not the same, the voltage values obtained by redistributing charges with the integrating capacitor C0 after different switching capacitors C1 or C2 are connected to the integrator are not equal; values to the reference voltage VREF with unequal integration times. In the case of unequal integration time, a frequency division circuit can be added before the frequency output, so that the final output signal is a frequency signal with an equal period; if the frequency division circuit is a frequency division circuit by two, the period of its output signal is C1 and C2 is connected to the sum of two adjacent integration periods of the integrator respectively. After the frequency division by the frequency division circuit by two, the period of the output converted frequency signal is the same.
本实用新型通过电流频率转换电路将电流信号直接转换为数字处理器可处理的频率信号，电路结构简单，精度高，成本低；切换电容无缝切换，不存在电容放电引入的非线性误差。并且由于所述逻辑控制模块根据比较器的输出电平自动选择一输出端输出控制信号，因此其内部无需设置定时器控制逻辑，控制功能比较简单；且根据控制信号切换电容可以实现无缝切换，一切换电容工作时，另一切换电容放电，无需延时控制，因此所述逻辑控制模块内部无需设置延时器控制逻辑，进一步简化其控制功能，同时也降低了对放大器的响应速率要求。The utility model directly converts the current signal into a frequency signal that can be processed by a digital processor through a current-frequency conversion circuit. The circuit structure is simple, the precision is high, and the cost is low; switching capacitors are seamlessly switched, and there is no nonlinear error introduced by capacitor discharge. And because the logic control module automatically selects an output terminal to output the control signal according to the output level of the comparator, it does not need to set timer control logic inside, and the control function is relatively simple; and switching the capacitor according to the control signal can realize seamless switching, When one switched capacitor is working, the other switched capacitor is discharged without delay control, so the logic control module does not need to set a delayer control logic inside, which further simplifies its control function, and also reduces the response rate requirement of the amplifier.
下面结合附图给出本实用新型提供的电流频率转换电路的几个实施例，以对本实用新型做进一步解释说明。Several embodiments of the current-frequency conversion circuit provided by the present invention are given below in conjunction with the accompanying drawings to further explain the present invention.
结合图3-5，其中，图3为本实用新型所述的电流频率转换电路第一实施例的电路图，图4为图3所示电路一实施例的工作时序图，图5为图3所示电路另一实施例的工作时序图。In combination with Figures 3-5, Figure 3 is a circuit diagram of the first embodiment of the current-frequency conversion circuit described in the present invention, Figure 4 is a working sequence diagram of an embodiment of the circuit shown in Figure 3 , and Figure 5 is a diagram of the circuit shown in Figure 3 The working sequence diagram of another embodiment of the circuit is shown.
参见图3，其中，每一开关所对应标示的Φ1和表示其所接收的控制信号；Φ1和是两相不交叠时钟控制信号，由逻辑控制模块14产生；电压VREF是由其它电路提供的基准电压源。Refer to Figure 3, where Φ1 and Φ1 marked corresponding to each switch Indicates the control signal it receives; Φ1 and is a two-phase non-overlapping clock control signal, which is generated by the logic control module 14; the voltage VREF is a reference voltage source provided by other circuits.
在电路启动时，假设逻辑控制模块14输出的Φ1信号(第一时钟控制信号)有效、信号(第二时钟控制信号)无效。所有接收Φ1信号的开关(第一开关子单元221与第四开关子单元242)闭合，所有接收信号的开关(第二开关子单元222与第三开关子单元241)断开，运算放大器A1与电容C0、C1组合成积分器，在输入电流I的作用下，运算放大器A1的输出V1从0到电压VREF积分；比较器A2输出VO为高电平，电容C2两端短路，其存储电荷为0。当V1达到电压VREF时，VO翻转为低电平，第二个积分周期开始；此时，逻辑控制模块14输出的信号有效、Φ1信号无效，所有接收Φ1信号的开关(第一开关子单元221与第四开关子单元242)断开，所有接收信号的开关(第二开关子单元222与第三开关子单元241)闭合；C2接入积分器，C2与C0平均分配C0上的电荷，使V1电压从VREF下降，VO翻转为高电平；电容C0，C2与运算放大器A1组合成积分器，对输入电流I从电荷分配后的电压值到VREF进行积分。同时电容C1上的积分电荷被放电，最终C1上的电荷被放电到0。当V1达到电压VREF时，VO翻转为低电平，第三个积分周期开始；此时，逻辑控制模块14输出的Φ1信号有效、信号无效。在输入的待转换电流信号I持续期间内，上述第二个积分周期和第三个积分周期交替重复，从而将输入的待转换电流信号I转化为频率信号输出。如果启动时积分电容的初始电荷为零，第一个积分周期所对应的频率要比稳定后每个周期T所对应的频率低。When the circuit starts, it is assumed that the Φ1 signal (the first clock control signal) output by the logic control module 14 is effective, signal (second clock control signal) is invalid. All the switches (the first switch subunit 221 and the fourth switch subunit 242) that receive the Φ1 signal are closed, and all the switches that receive the Φ1 signal The signal switch (the second switch subunit 222 and the third switch subunit 241) is disconnected, and the operational amplifier A1 is combined with the capacitors C0 and C1 to form an integrator. Under the action of the input current I, the output V1 of the operational amplifier A1 changes from 0 Integrate to the voltage VREF; the comparator A2 output VO is high level, the two ends of the capacitor C2 are short-circuited, and the stored charge is 0. When V1 reaches the voltage VREF, VO flips to a low level, and the second integration cycle begins; at this time, the output of the logic control module 14 The signal is valid, the Φ1 signal is invalid, all the switches (the first switch subunit 221 and the fourth switch subunit 242) that receive the Φ1 signal are turned off, and all the switches that receive the Φ1 signal The switch of the signal (the second switch subunit 222 and the third switch subunit 241) is closed; C2 is connected to the integrator, C2 and C0 evenly distribute the charge on C0, so that the voltage of V1 drops from VREF, and VO turns to a high level; Capacitors C0 and C2 are combined with operational amplifier A1 to form an integrator, which integrates the input current I from the voltage value after charge distribution to VREF. At the same time, the integrated charge on the capacitor C1 is discharged, and finally the charge on C1 is discharged to 0. When V1 reaches the voltage VREF, VO flips to a low level, and the third integration period begins; at this time, the Φ1 signal output by the logic control module 14 is valid, Invalid signal. During the continuous period of the input current signal I to be converted, the second integration period and the third integration period are repeated alternately, so that the input current signal I to be converted is converted into a frequency signal for output. If the initial charge on the integrating capacitor is zero at start-up, the frequency corresponding to the first integration period will be lower than the frequency corresponding to each period T after stabilization.
当C0，C1，C2电容取值相同均为C时，在电路稳定工作时，图3所示的电流频率转换电路的工作时序为：When the values of C0, C1, and C2 capacitors are the same as C, when the circuit works stably, the working sequence of the current-frequency conversion circuit shown in Figure 3 is:
1、当逻辑控制模块14输出的Φ1信号有效(例如为高电平)、信号无效(为低电平)时，所有接收Φ1信号的开关闭合、所有接收信号的开关断开，运算放大器A1与电容C0，C1组合成积分器，在输入电流I的作用下，运算放大器A1的输出V1从VREF/2到电压VREF积分，比较器A2输出VO为高电平，C2电容两端短路，其存储电荷为0。1. When the Φ1 signal output by the logic control module 14 is valid (for example, high level), When the signal is invalid (low level), all switches receiving the Φ1 signal are closed, and all receiving The signal switch is turned off, the operational amplifier A1 is combined with the capacitors C0 and C1 to form an integrator, under the action of the input current I, the output V1 of the operational amplifier A1 is integrated from VREF/2 to the voltage VREF, and the output VO of the comparator A2 is a high voltage Ping, the two ends of the C2 capacitor are short-circuited, and the stored charge is 0.
2、当V1达到电压VREF时，比较器A2输出VO翻转为低电平；逻辑控制模块14输出的信号有效(为高电平)、Φ1信号无效(为低电平)，所有接收Φ1信号的开关断开，所有接收信号的开关闭合；C2接入积分器，C2与C0平均分配C0上的电荷，使V1电压从VREF下降到VREF/2；由于V1电压下降，VO翻转为高电平；电容C0，C2与运算放大器A1组合成积分器，对输入电流I从VREF/2到VREF进行积分。电容C1上的积分电荷被放电，最终C1上的电荷被放电到0。2. When V1 reaches the voltage VREF, the output VO of the comparator A2 flips to a low level; the output of the logic control module 14 The signal is valid (high level), the Φ1 signal is invalid (low level), all switches receiving the Φ1 signal are off, and all receiving The switch of the signal is closed; C2 is connected to the integrator, and C2 and C0 evenly distribute the charge on C0, so that the voltage of V1 drops from VREF to VREF/2; due to the voltage drop of V1, VO flips to a high level; capacitors C0, C2 and the operation Amplifier A1 is combined as an integrator to integrate the input current I from VREF/2 to VREF. The integrated charge on the capacitor C1 is discharged, and finally the charge on C1 is discharged to 0.
3、当V1再次达到电压VREF时，VO翻转为低电平；逻辑控制模块14输出的Φ1信号有效(为高电平)、信号无效(为低电平)，所有接收信号的开关断开，所有接收Φ1信号的开关闭合；C1接入积分器，C1与C0平均分配C0上的电荷，使V1电压从VREF下降到VREF/2；由于V1电压下降，VO翻转为高电平；电容C0，C1与运算放大器A1组合成积分器，对输入电流I从VREF/2到VREF进行积分。电容C2上的积分电荷被放电，最终C2上的电荷被放电到0。3. When V1 reaches the voltage VREF again, VO turns to low level; the Φ1 signal output by the logic control module 14 is valid (high level), The signal is invalid (low level), all receive The switch of the signal is turned off, and all the switches receiving the Φ1 signal are closed; C1 is connected to the integrator, and C1 and C0 evenly distribute the charge on C0, so that the voltage of V1 drops from VREF to VREF/2; due to the drop of V1 voltage, VO flips to high level; capacitors C0, C1 and operational amplifier A1 are combined to form an integrator, which integrates the input current I from VREF/2 to VREF. The integrated charge on the capacitor C2 is discharged, and finally the charge on C2 is discharged to 0.
4、在输入电流I持续期间内，所述的电流频率转换电路重复2、3两步的工作时序，在V1端产生锯齿波，在VO端产生方波，从而将输入电流转化为方波频率输出，工作时序如图4所示。4. During the duration of the input current I, the current-frequency conversion circuit repeats the working sequence of steps 2 and 3 to generate a sawtooth wave at the V1 terminal and a square wave at the VO terminal, thereby converting the input current into a square wave frequency output, the working sequence is shown in Figure 4.
波形的频率与输入电流I成正比，电流频率转换方程为：The frequency of the waveform is proportional to the input current I, and the current-frequency conversion equation is:
当C1与C2电容取值相同，并与C0不同时，在电路稳定工作时，图3所示的电流频率转换电路的工作时序仍为上述时序，工作时序仍可参考图4，但稳定后的积分开始电压则为0到VREF之间除0和VREF以及VREF/2以外的其它值。When the capacitance values of C1 and C2 are the same and different from C0, when the circuit works stably, the working sequence of the current-frequency conversion circuit shown in Figure 3 is still the above sequence, and the working sequence can still refer to Figure 4, but after stabilization The integral start voltage is other values between 0 and VREF except 0, VREF and VREF/2.
当C0，C1，C2电容取值不相同时，在电路稳定工作时，图3所示的电流频率转换电路的工作时序仍为上述时序，但积分器的积分起始电压值则不一定为VREF/2，并需加入分频电路(图3中未示出)才能保证输出信号的周期性。本实施例以C1<C2为例，此时工作时序如图5所示。图中C1接入积分器时的积分起始电压值为VC1、积分周期为T1，C2接入积分器时的积分起始电压值为VC2、积分周期为T2，T为转换后的频率信号周期。When the values of C0, C1, and C2 capacitors are different, when the circuit works stably, the working sequence of the current-frequency conversion circuit shown in Figure 3 is still the above-mentioned sequence, but the integral initial voltage value of the integrator is not necessarily VREF /2, and a frequency division circuit (not shown in Figure 3) needs to be added to ensure the periodicity of the output signal. This embodiment takes C1<C2 as an example, and the working sequence at this time is shown in FIG. 5 . In the figure, when C1 is connected to the integrator, the integral initial voltage value is VC1, and the integral period is T1; when C2 is connected to the integrator, the integral initial voltage value is VC2, and the integral period is T2, and T is the converted frequency signal period .
参见图6-8，其中图6为本实用新型所述的电流频率转换电路第二实施例的电路图，图7为本实用新型所述的电流频率转换电路第三实施例的电路图，图8为本实用新型所述的电流频率转换电路第四实施例的电路图，其中，各附图中相同标号组件表示相同或相似组件。与图3所示实施例不同之处在于所示电容充放电控制模块内部接入控制单元22以及放电控制单元24的开关子单元的开关配置及电路连接方式，图6-8所示电路的工作原理和控制逻辑与图3所示电路类似，在此不再赘述。Referring to Figs. 6-8, Fig. 6 is a circuit diagram of the second embodiment of the current-frequency conversion circuit described in the present invention, Fig. 7 is a circuit diagram of the third embodiment of the current-frequency conversion circuit described in the present invention, and Fig. 8 is The circuit diagram of the fourth embodiment of the current-frequency conversion circuit described in the present invention, wherein the components with the same number in each drawing represent the same or similar components. The difference from the embodiment shown in FIG. 3 lies in the switch configuration and circuit connection mode of the switch sub-units of the capacitor charge and discharge control module connected to the control unit 22 and the discharge control unit 24, and the operation of the circuit shown in FIGS. 6-8 The principle and control logic are similar to the circuit shown in Figure 3, and will not be repeated here.
以上所述仅是本实用新型的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本实用新型原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本实用新型的保护范围。The above is only a preferred embodiment of the utility model, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the utility model, some improvements and modifications can also be made. It should be regarded as the protection scope of the present utility model.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520362193.5UCN204666166U (en) | 2015-05-29 | 2015-05-29 | Capacitor charge and discharge control module and power frequency change-over circuit |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520362193.5UCN204666166U (en) | 2015-05-29 | 2015-05-29 | Capacitor charge and discharge control module and power frequency change-over circuit |
| Publication Number | Publication Date |
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| CN204666166Utrue CN204666166U (en) | 2015-09-23 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520362193.5UExpired - LifetimeCN204666166U (en) | 2015-05-29 | 2015-05-29 | Capacitor charge and discharge control module and power frequency change-over circuit |
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| CN (1) | CN204666166U (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106289333A (en)* | 2015-05-29 | 2017-01-04 | 苏州坤元微电子有限公司 | Capacitor charge and discharge control module and power frequency change-over circuit |
| CN112491418A (en)* | 2020-11-19 | 2021-03-12 | 垣矽技术(青岛)有限公司 | Current frequency conversion circuit |
| CN112857408A (en)* | 2021-03-10 | 2021-05-28 | 北京同芯科技有限公司 | High-reliability current frequency conversion circuit |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106289333A (en)* | 2015-05-29 | 2017-01-04 | 苏州坤元微电子有限公司 | Capacitor charge and discharge control module and power frequency change-over circuit |
| CN106289333B (en)* | 2015-05-29 | 2019-01-25 | 苏州坤元微电子有限公司 | Capacitor charge and discharge control module and power frequency conversion circuit |
| CN112491418A (en)* | 2020-11-19 | 2021-03-12 | 垣矽技术(青岛)有限公司 | Current frequency conversion circuit |
| CN112857408A (en)* | 2021-03-10 | 2021-05-28 | 北京同芯科技有限公司 | High-reliability current frequency conversion circuit |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term | Granted publication date:20150923 |