CN203574638U

Movatterモバイル変換

Info

Publication number: CN203574638U
Application number: CN201320779993.8U
Authority: CN
Inventors: 马延军
Original assignee: Xian University of Science and Technology
Current assignee: Xian University of Science and Technology
Priority date: 2013-11-29
Filing date: 2013-11-29
Publication date: 2014-04-30
Anticipated expiration: 2023-11-29

Abstract

本实用新型公开一种模块化短波软件无线电开发试验装置，A/D模块依次与FPGA模块、以太网模块和PC机连接，FPGA模块还分别与音频编解码模块和D/A模块连接。本使用新型解决软件无线电的短波通信系统不能根据具体要求更换不同模块，致使该技术的灵活性和通用性差的技术问题。

The utility model discloses a modularized short-wave software radio development test device. An A/D module is sequentially connected with an FPGA module, an Ethernet module and a PC, and the FPGA module is also respectively connected with an audio codec module and a D/A module. The novel method solves the technical problem that the shortwave communication system of the software radio cannot replace different modules according to specific requirements, resulting in poor flexibility and versatility of the technology.

Description

Translated fromChinese

一种模块化短波软件无线电开发试验装置A Modular Shortwave Software Radio Development Test Device

技术领域technical field

本实用新型涉及无线通信领域，特别涉及一种模块化短波软件无线电开发试验装置。The utility model relates to the field of wireless communication, in particular to a modular short-wave software radio development test device.

背景技术Background technique

软件定义无线电SDR是将A/D转换器尽可能的靠近射频天线，充分利用软件技术实现或模拟收发信机在实际情况下处理数据时使用的各种算法。该技术避免了传统收发信机中使用的庞大而复杂的多次变频技术，大大降低试验测试成本，且使用该技术后的装置能与实际收发信机的性能保持高度一致，其温度稳定性、可靠度等指标都得到了大幅度提升，目前这项技术已经广泛应用于通信行业的各个领域。Software-defined radio SDR is to place the A/D converter as close as possible to the radio frequency antenna, and make full use of software technology to realize or simulate various algorithms used by the transceiver to process data in actual situations. This technology avoids the huge and complex multiple frequency conversion technology used in traditional transceivers, greatly reduces the cost of testing and testing, and the device after using this technology can maintain a high degree of consistency with the performance of the actual transceiver, its temperature stability, Reliability and other indicators have been greatly improved. At present, this technology has been widely used in various fields of the communication industry.

在实现上述技术方案的过程中，发明人发现现有技术中至少存在以下技术问题：短波通信技术因其自身的优良特性在军事、应急通信等领域运用广泛，然而目前基于软件无线电的短波通信系统都是针对特定应用环境开发的专用系统，不能根据具体要求更换不同模块，致使该技术的灵活性和通用性差，不利于在新产品的测试、教学及其他领域中的推广。In the process of realizing the above-mentioned technical solution, the inventor found that there are at least the following technical problems in the prior art: short-wave communication technology is widely used in the fields of military affairs and emergency communication due to its own excellent characteristics, but the current short-wave communication system based on software radio All are dedicated systems developed for specific application environments, and different modules cannot be replaced according to specific requirements, resulting in poor flexibility and versatility of the technology, which is not conducive to the promotion of new product testing, teaching and other fields.

实用新型内容Utility model content

本实用新型目的是提供一种模块化短波软件无线电开发试验装置，解决基于软件无线电的短波通信系统都是针对特定应用环境开发的专用系统，不利于推广普及的技术问题。The purpose of the utility model is to provide a modular short-wave software radio development test device to solve the technical problem that the short-wave communication system based on software radio is a special system developed for a specific application environment, which is not conducive to popularization.

本实用新型采用的技术方案是，一种模块化短波软件无线电开发试验装置，包括A/D模块、音频编解码模块、FPGA模块、D/A模块、以太网模块和PC机，其中，A/D模块依次与FPGA模块、以太网模块和PC机连接，FPGA模块还分别与音频编解码模块和D/A模块连接。The technical solution adopted by the utility model is a modular short-wave software radio development test device, including an A/D module, an audio codec module, an FPGA module, a D/A module, an Ethernet module and a PC, wherein the A/D The D module is connected with the FPGA module, the Ethernet module and the PC in turn, and the FPGA module is also connected with the audio codec module and the D/A module respectively.

进一步的，FPGA模块内部包括A/D控制器、数字下变频器、FIFO存储器、数字上变频器、D/A控制器、IS模块，其中，Further, the FPGA module includes an A/D controller, a digital down converter, a FIFO memory, a digital up converter, a D/A controller, and an IS module, wherein,

A/D控制器依次与数字下变频器、FIFO存储器连接，A/D控制器还与A/D模块连接；The A/D controller is connected with the digital down converter and the FIFO memory in turn, and the A/D controller is also connected with the A/D module;

D/A控制器依次与数字上变频器、FIFO存储器连接，D/A控制器还与D/A模块连接；The D/A controller is sequentially connected with the digital up-converter and the FIFO memory, and the D/A controller is also connected with the D/A module;

FIFP存储器通过IS模块与音频编解码模块连接,FIFP存储器还与以太网模块。The FIFP memory is connected with the audio codec module through the IS module, and the FIFP memory is also connected with the Ethernet module.

进一步的，数字下变频器包括数字震荡控制器、第一CIC抽取滤波器、第二CIC抽取滤波器、第一FIR抽取滤波器、第三CIC抽取滤波器、第四CIC抽取滤波器、第二FIR抽取滤波器，其中，Further, the digital down converter includes a digital oscillation controller, a first CIC decimation filter, a second CIC decimation filter, a first FIR decimation filter, a third CIC decimation filter, a fourth CIC decimation filter, a second FIR decimation filter, where,

数字震荡控制器与A/D控制器连接；The digital oscillation controller is connected with the A/D controller;

数字震荡控制器还依次与第一CIC抽取滤波器、第二CIC抽取滤波器、第一FIR抽取滤波器连接，第一FIR抽取滤波器还与FIFO存储器连接；The digital oscillation controller is also connected with the first CIC decimation filter, the second CIC decimation filter, and the first FIR decimation filter in sequence, and the first FIR decimation filter is also connected with the FIFO memory;

数字震荡控制器还依次第三CIC抽取滤波器、第四CIC抽取滤波器、第二FIR抽取滤波器连接，第二FIR抽取滤波器还与FIFO存储器连接。The digital oscillation controller is also connected to the third CIC decimation filter, the fourth CIC decimation filter, and the second FIR decimation filter in sequence, and the second FIR decimation filter is also connected to the FIFO memory.

进一步的，A/D模块内置14位125M的LTC2145和/或16位20M的LTC2270芯片。Further, the A/D module has built-in 14-bit 125M LTC2145 and/or 16-bit 20M LTC2270 chips.

进一步的，FPGA模块内置EP3C25芯片。Furthermore, the FPGA module has a built-in EP3C25 chip.

进一步的，以太网模块内置KSZ9021芯片。Furthermore, the Ethernet module has a built-in KSZ9021 chip.

进一步的，音频编解码模块内置TLV320AIC23B芯片。Furthermore, the audio codec module has a built-in TLV320AIC23B chip.

进一步的，D/A模块内置14位165M的DAC904E芯片。Furthermore, the D/A module has a built-in 14-bit 165M DAC904E chip.

本实用新型公开了一种模块化短波软件无线电开发试验装置。模块间通过物理接口进行组合，根据需要，可以进一步开发不同功能及性能的其他模块，可广泛应用于软件无线电产品的开发与试验及教学等环境，增强了可移植和各系统之间的兼容性，方便推广和普及。The utility model discloses a development test device for a modularized short-wave software radio. The modules are combined through physical interfaces, and other modules with different functions and performances can be further developed according to the needs, which can be widely used in software radio product development, testing and teaching environments, and enhance portability and compatibility between systems , to facilitate promotion and popularization.

附图说明Description of drawings

图1为本实用新型模块化短波软件无线电开发试验装置的示意图；Fig. 1 is the schematic diagram of the utility model modularized short-wave software radio development test device;

图2为本实用新型中的FPGA模块的结构示意图；Fig. 2 is the structural representation of the FPGA module in the utility model;

图3为本实用新型中的接收信号的流程框图；Fig. 3 is the block flow diagram of receiving signal in the utility model;

图4为本实用新型中的接收信号的流程框图。Fig. 4 is a flow block diagram of receiving signals in the utility model.

具体实施方式Detailed ways

如图1所示，本实用新型模块化短波软件无线电开发试验装置，包括A/D模块1、音频编解码模块2、FPGA模块3、D/A模块4、以太网模块5、PC机，其中，A/D模块1依次与FPGA模块3、以太网模块5和PC机连接，FPGA模块3还分别与音频编解码模块2和D/A模块4连接。A/D模块1内置14位125M的LTC2145和/或16位20M的LTC2270芯片。FPGA模块3内置EP3C25芯片。以太网模块5内置KSZ9021芯片。音频编解码模块2内置TLV320AIC23B芯片。D/A模块4内置14位165M的DAC904E芯片。As shown in Figure 1, the utility model modularized shortwave software radio development test device comprises A/D module 1, audio codec module 2, FPGA module 3, D/A module 4, Ethernet module 5, PC, wherein , A/D module 1 is connected with FPGA module 3, Ethernet module 5 and PC in sequence, and FPGA module 3 is also connected with audio codec module 2 and D/A module 4 respectively. A/D module 1 has built-in 14-bit 125M LTC2145 and/or 16-bit 20M LTC2270 chips. FPGA module 3 has a built-in EP3C25 chip. The Ethernet module 5 has a built-in KSZ9021 chip. The audio codec module 2 has a built-in TLV320AIC23B chip. The D/A module 4 has a built-in 14-bit 165M DAC904E chip.

下面对上述装置进行更具体的描述：The above-mentioned device is described in more detail below:

LTC2145/LTC2270开发试验板可支持LTC2145或者LTC2270芯片，LTC2145芯片为14位125M高速A/D转换芯片，LTC2270为16位20M高速A/D转换芯片。此模块对整个短波频段进行过采样。从天线来的信号被转换到数字域。同时，此模块包含2个A/D采样通道，可扩展并支持数字中频处理。此模块通过插针接口与FPGA模块3连接。通过在FPGA模块3的内部预设定的算法实现A/D采样控制、数字下变频DDC、数字上变频DUC、千兆以太网KSZ9021的MAC协议控制并支持IP/UDP数据收发、音频输入输出控制及高速D/A模块控制等功能。内置KSZ9021芯片的以太网模块5完成千兆以太网的PHY功能，并通过接口连接到FPGA模块3上面。音频编解码模块2采用TLV320AIC23B芯片完成音频编解码处理，同样通过接口连接到FPGA模块3上面。内置于D/A模块4的DAC904E芯片为14位165M速率的D/A转换芯片，EP3C25完成数字上变频后，通过此模块，将调制信号发送出去。此模块同样通过接口连接到FPGA模块3上面。LTC2145/LTC2270 development test board can support LTC2145 or LTC2270 chip, LTC2145 chip is a 14-bit 125M high-speed A/D conversion chip, LTC2270 is a 16-bit 20M high-speed A/D conversion chip. This module oversamples the entire shortwave frequency band. The signal from the antenna is converted into the digital domain. At the same time, this module contains 2 A/D sampling channels, which can be expanded and support digital intermediate frequency processing. This module is connected with the FPGA module 3 through a pin interface. Realize A/D sampling control, digital down-conversion DDC, digital up-conversion DUC, MAC protocol control of Gigabit Ethernet KSZ9021 and support IP/UDP data transmission and reception, audio input and output control through the algorithm preset in the FPGA module 3 And high-speed D/A module control and other functions. The Ethernet module 5 with a built-in KSZ9021 chip completes the PHY function of Gigabit Ethernet, and is connected to the FPGA module 3 through an interface. The audio codec module 2 uses the TLV320AIC23B chip to complete the audio codec processing, and is also connected to the FPGA module 3 through an interface. The DAC904E chip built in the D/A module 4 is a 14-bit 165M rate D/A conversion chip. After the EP3C25 completes the digital up-conversion, the modulated signal is sent out through this module. This module is also connected to the FPGA module 3 through the interface.

FPGA模块3包括A/D控制器31、数字下变频器32、FIFO存储器33、数字上变频器34、D/A控制器35、I2S模块36，其中，A/D控制器31依次与数字下变频器32、FIFO存储器33连接，A/D控制器31还与A/D模块1连接；D/A控制器35依次与数字上变频器34、FIFO存储器33连接，D/A控制器35还与D/A模块4连接；FIFP存储器33通过I2S模块36与音频编解码模块2连接,FIFP存储器33还与以太网模块5。FPGA module 3 comprises A/D controller 31, digital downconverter 32, FIFO memory 33, digital upconverter 34, D/A controller 35, I2S module 36, wherein, A/D controller 31 and digital downconverter successively The frequency converter 32 and the FIFO memory 33 are connected, and the A/D controller 31 is also connected with the A/D module 1; the D/A controller 35 is connected with the digital up-converter 34 and the FIFO memory 33 in turn, and the D/A controller 35 is also connected It is connected with D/A module 4; FIFP memory 33 is connected with audio codec module 2 through I2S module 36, and FIFP memory 33 is also connected with Ethernet module 5.

数字下变频器32包括数字震荡控制器321、第一CIC抽取滤波器322、第二CIC抽取滤波器323、第一FIR抽取滤波器324、第三CIC抽取滤波器325、第四CIC抽取滤波器326、第二FIR抽取滤波器327，其中，数字震荡控制器321与A/D控制器31连接；数字震荡控制器321还依次与第一CIC抽取滤波器322、第二CIC抽取滤波器323、第一FIR抽取滤波器324连接，第一FIR抽取滤波器324还与FIFO存储器33连接；数字震荡控制器321还依次第三CIC抽取滤波器325、第四CIC抽取滤波器326、第二FIR抽取滤波器327连接，第二FIR抽取滤波器327还与FIFO存储器33连接。The digital down converter 32 includes a digital oscillation controller 321, a first CIC decimation filter 322, a second CIC decimation filter 323, a first FIR decimation filter 324, a third CIC decimation filter 325, a fourth CIC decimation filter 326. The second FIR decimation filter 327, wherein the digital oscillation controller 321 is connected to the A/D controller 31; the digital oscillation controller 321 is also sequentially connected to the first CIC decimation filter 322, the second CIC decimation filter 323, First FIR decimation filter 324 is connected, and first FIR decimation filter 324 is also connected with FIFO memory 33; The filter 327 is connected, and the second FIR decimation filter 327 is also connected to the FIFO memory 33 .

下面结合图2对FPGA模块3中各个单元的用途进行详细描述：The purpose of each unit in the FPGA module 3 is described in detail below in conjunction with FIG. 2:

A/D控制器31用于完成接口控制时序及A/D数值范围变换，A/D采样的位数支持16位或14位；数字下变频器32采用CORDIC算法对A/D转换后的数据进行数字下变频，数字下变频后输出24位；NCO的频率由PC机6通过以太网传输过来。第一CIC抽取滤波器322、第三CIC抽取滤波器325为第一级滤波，抽取因子固定为8；第二CIC抽取滤波器323、第四CIC抽取滤波器326为第二级滤波，抽取滤波器抽取因子可变，其取值可为5、10、20、40，第一FIR抽取滤波器324、第二FIR抽取滤波器327为最后一级滤波，抽取因子为8。，PC机6通过以太网传输I/Q信号到FIFO存储器33，I/Q的速率为48Ksps，此数据经过CIC内插滤波器,参数值固定为2560，得到速率为122.88Msps，进入CORDIC数字上变频器34，其中，数字上变频器的频率由PC机6下发，最后，经过D/A控制器35进行时序逻辑控制驱动DAC904E。音频编解码器模块2采用I2S模块完成MIC语音信号的上传及Speaker语音信号的下传。The A/D controller 31 is used to complete the interface control sequence and the A/D value range transformation, and the number of bits sampled by the A/D supports 16 or 14 bits; the digital down-converter 32 adopts the CORDIC algorithm to convert the A/D data Carry out digital down-conversion, and output 24 bits after digital down-conversion; the frequency of NCO is transmitted by PC 6 through Ethernet. The first CIC decimation filter 322 and the third CIC decimation filter 325 are first-stage filtering, and the decimation factor is fixed at 8; the second CIC decimation filter 323 and the fourth CIC decimation filter 326 are second-stage filtering, and the decimation filter The filter decimation factor is variable, and its value can be 5, 10, 20, 40. The first FIR decimation filter 324 and the second FIR decimation filter 327 are the last stage of filtering, and the decimation factor is 8. , PC 6 transmits I/Q signal to FIFO memory 33 through Ethernet, the rate of I/Q is 48Ksps, this data passes through CIC interpolation filter, parameter value is fixed as 2560, obtains rate is 122.88Msps, enters CORDIC digital on The frequency converter 34, wherein the frequency of the digital up-converter is issued by the PC 6, and finally, the D/A controller 35 performs sequential logic control to drive the DAC904E. The audio codec module 2 uses the I2S module to complete the upload of the MIC voice signal and the download of the Speaker voice signal.

结合图3简述接收信号的处理过程：Combined with Figure 3, the processing process of the received signal is briefly described:

1001、PC机6下发收发频率及CIC滤波器抽取因子等参数；1001. The PC 6 issues parameters such as the transceiver frequency and the extraction factor of the CIC filter;

1002、数字下变频器32进行数据的下变频与抽取滤波，得到速率为48K/96K/192K/384Ksps的I/Q基带数据；1002. The digital down-converter 32 performs data down-conversion and decimation filtering to obtain I/Q baseband data whose rate is 48K/96K/192K/384Ksps;

1003、基带数据进入到FIFO存储器33；1003. The baseband data enters the FIFO memory 33;

1004、FIFO存储器033中的数据通过以太网模块5上传到PC机6；1004, the data in the FIFO memory 033 is uploaded to the PC 6 through the Ethernet module 5;

1005、PC机6对I/Q基带数据进行解调；1005. The PC 6 demodulates the I/Q baseband data;

1006、PC机6将解调后的数据通过以太网模块5下发到音频编解码模块2。1006. The PC 6 sends the demodulated data to the audio codec module 2 through the Ethernet module 5.

结合图4简述发射信号的处理过程：Combined with Figure 4, the processing process of the transmitted signal is briefly described:

2001、音频编解码模块2把MIC的数据传输到FIFO存储器33；2001, the audio codec module 2 transmits the data of the MIC to the FIFO memory 33;

2002、FIFO存储器33的数据上传到PC机6；2002, the data of FIFO memory 33 is uploaded to PC machine 6;

2003、PC机6进行调制处理，得到I/Q数据；2003, the PC 6 performs modulation processing to obtain I/Q data;

2004、PC机将I/Q数据通过以太网模块5下传；2004. The PC downloads the I/Q data through the Ethernet module 5;

2005、得到I/Q数据后，进行DUC，通过D/A模块4输出。2005. After obtaining the I/Q data, perform DUC and output it through the D/A module 4 .

以上，仅为本实用新型的具体实施方式，但本实用新型的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本实用新型揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本实用新型的保护范围之内。因此，本实用新型的保护范围应以权利要求的保护范围为准。The above are only specific implementations of the present utility model, but the scope of protection of the present utility model is not limited thereto. Any skilled person familiar with the technical field can easily think of changes or replacements within the technical scope disclosed by the utility model. , should be covered within the protection scope of the present utility model. Therefore, the protection scope of the present utility model should be based on the protection scope of the claims.

Claims

Translated fromChinese

1.一种模块化短波软件无线电开发试验装置，其特征在于，包括A/D模块（1）、音频编解码模块（2）、FPGA模块（3）、D/A模块（4）、以太网模块（5）和PC机（6），其中，所述A/D模块（1）依次与FPGA模块（3）、以太网模块（5）和PC机（6）连接，所述FPGA模块（3）还分别与音频编解码模块（2）和D/A模块（4）连接。1. A modular shortwave software radio development test device, characterized in that it includes an A/D module (1), an audio codec module (2), an FPGA module (3), a D/A module (4), an Ethernet module (5) and PC (6), wherein, the A/D module (1) is connected with FPGA module (3), Ethernet module (5) and PC (6) in turn, and the FPGA module (3 ) are also connected with the audio codec module (2) and the D/A module (4) respectively.

2.根据权利要求1所述的一种模块化短波软件无线电开发试验装置，其特征在于，所述FPGA模块（3）包括A/D控制器（31）、数字下变频器（32）、FIFO存储器（33）、数字上变频器（34）、D/A控制器（35）和I2S模块（36）；其中，所述A/D控制器（31）依次与所述数字下变频器（32）、FIFO存储器（33）连接，所述A/D控制器（31）还与所述A/D模块（1）连接；所述D/A控制器（35）依次与所述数字上变频器（34）、FIFO存储器（33）连接，所述D/A控制器（35）还与所述D/A模块（4）连接；所述FIFP存储器（33）通过所述I2S模块（36）与所述音频编解码模块（2）连接,所述FIFP存储器（33）还与所述以太网模块（5）。2. A modular shortwave software radio development test device according to claim 1, characterized in that the FPGA module (3) includes an A/D controller (31), a digital down converter (32), a FIFO Memory (33), digital up-converter (34), D/A controller (35) and I2S module (36); wherein, the A/D controller (31) is sequentially connected with the digital down-converter (32 ), the FIFO memory (33), the A/D controller (31) is also connected to the A/D module (1); the D/A controller (35) is sequentially connected to the digital up-converter (34), the FIFO memory (33) is connected, and the D/A controller (35) is also connected with the D/A module (4); the FIFP memory (33) is connected with the I2S module (36) The audio codec module (2) is connected, and the FIFP memory (33) is also connected to the Ethernet module (5).

3.根据权利要求2所述的一种模块化短波软件无线电开发试验装置，其特征在于，所述数字下变频器（32）包括数字震荡控制器（321）、第一CIC抽取滤波器（322）、第二CIC抽取滤波器（323）、第一FIR抽取滤波器（324）、第三CIC抽取滤波器（325）、第四CIC抽取滤波器（326）和第二FIR抽取滤波器（327），其中，3. A modular shortwave software radio development test device according to claim 2, characterized in that the digital down converter (32) includes a digital oscillation controller (321), a first CIC decimation filter (322 ), the second CIC decimation filter (323), the first FIR decimation filter (324), the third CIC decimation filter (325), the fourth CIC decimation filter (326) and the second FIR decimation filter (327 ),in,

所述第一数字震荡控制器（321）与所述A/D控制器（31）连接；The first digital oscillation controller (321) is connected to the A/D controller (31);

所述第一数字震荡控制器（321）还依次与第一CIC抽取滤波器（322）、第二CIC抽取滤波器（323）、第一FIR抽取滤波器（324）连接，所述第一FIR抽取滤波器（324）还与所述FIFO存储器（33）连接；The first digital oscillation controller (321) is also sequentially connected with the first CIC decimation filter (322), the second CIC decimation filter (323), and the first FIR decimation filter (324), and the first FIR The decimation filter (324) is also connected to the FIFO memory (33);

所述第一数字震荡控制器（321）还依次第三CIC抽取滤波器（325）、第四CIC抽取滤波器（326）、第二FIR抽取滤波器（327）连接，所述第二FIR抽取滤波器（327）还与所述FIFO存储器（33）连接。The first digital oscillation controller (321) is also sequentially connected to the third CIC decimation filter (325), the fourth CIC decimation filter (326), and the second FIR decimation filter (327), and the second FIR decimation filter The filter (327) is also connected to the FIFO memory (33).

4.根据权利要求3所述的一种模块化短波软件无线电开发试验装置，其特征在于，所述数字上变频器（34）包括第二数字震荡控制器（341）、第五CIC抽取滤波器（342）和第六CIC抽取滤波器（343）；其中，第二数字震荡控制器（341）分别于所述第五CIC抽取滤波器（342）、第六CIC抽取滤波器（343）连接，所述第二数字震荡控制器（341）还与所述D/A控制器（35）连接，所述第五CIC抽取滤波器（342）、第六CIC抽取滤波器（343）还分别于所述FIFO存储器（33）连接。4. A modular shortwave software radio development test device according to claim 3, characterized in that the digital up-converter (34) includes a second digital oscillation controller (341), a fifth CIC decimation filter (342) and a sixth CIC decimation filter (343); wherein, the second digital oscillation controller (341) is respectively connected to the fifth CIC decimation filter (342) and the sixth CIC decimation filter (343), The second digital oscillation controller (341) is also connected to the D/A controller (35), and the fifth CIC decimation filter (342) and the sixth CIC decimation filter (343) are also connected to the The above FIFO memory (33) is connected.

5.根据权利要求1-4中所述的任一一种模块化短波软件无线电开发试验装置，其特征在于，所述A/D模块（1）内置14位125M的LTC2145和/或16位20M的LTC2270芯片。5. According to any one of the modular shortwave software radio development and test devices described in claims 1-4, it is characterized in that the A/D module (1) has built-in 14-bit 125M LTC2145 and/or 16-bit 20M The LTC2270 chip.

6.根据权利要求1-4中所述的任一一种模块化短波软件无线电开发试验装置，其特征在于，所述FPGA模块（3）内置EP3C25芯片。6. A modular shortwave software radio development test device according to any one of claims 1-4, characterized in that the FPGA module (3) has a built-in EP3C25 chip.

7.根据权利要求1-4中所述的任一一种模块化短波软件无线电开发试验装置，其特征在于，所述以太网模块（5）内置KSZ9021芯片。7. A modular shortwave software radio development test device according to any one of claims 1-4, characterized in that the Ethernet module (5) has a built-in KSZ9021 chip.

8.根据权利要求1-4中所述的任一一种模块化短波软件无线电开发试验装置，其特征在于，所述音频编解码模块（2）内置TLV320AIC23B芯片。8. A modular shortwave software radio development test device according to any one of claims 1-4, characterized in that the audio codec module (2) has a built-in TLV320AIC23B chip.

9.根据权利要求1-4中所述的任一一种模块化短波软件无线电开发试验装置，其特征在于，所述D/A模块（4）内置14位165M的DAC904E芯片。9. A modular shortwave software radio development test device according to any one of claims 1-4, characterized in that the D/A module (4) has a built-in 14-bit 165M DAC904E chip.