The utility model content
The purpose of the utility model is to provide a kind of reset circuit, is intended to solve prior art because the unusual problem of start of appearance falls in supply voltage temporarily.In order to solve the problems of the technologies described above, the utility model adopts following scheme to be achieved:
A kind of reset circuit comprises the output unit that is used to export reset level, and the first input end of said output unit is connected with first input voltage, and said reset circuit also comprises the monitoring means that is used to monitor mains voltage variations; The output of said monitoring means is connected with second input of output unit, and the first input end of said monitoring means, second input, the 3rd input are connected with second input voltage, the 3rd input voltage, Opportunity awaiting control for linear signal respectively.
Further, said monitoring means comprises first resistance, second resistance, the 3rd resistance, the 4th resistance, the 5th resistance, first triode, second triode, the 3rd triode, first electric capacity;
One end of wherein said first resistance is connected with second input voltage, and the other end is connected with the emitter of first triode; The base stage of said first triode is connected with the 3rd input voltage through second resistance, and the collector electrode of said first triode is connected with the collector electrode of second triode; The base stage of said second triode is connected with the Opportunity awaiting control for linear signal through the 3rd resistance; Also successively through ground connection behind the 4th resistance, first electric capacity, the emitter of said second triode is connected with the base stage of the 3rd triode through the 5th resistance the base stage of said second triode; The grounded emitter of said the 3rd triode, the current collection of said the 3rd triode is the output of monitoring means very.
Further, said output unit comprises the 6th resistance, the 7th resistance, the 8th resistance, the 9th resistance, the tenth resistance, the 4th triode, the 5th triode, second electric capacity, voltage stabilizing didoe;
First end of wherein said the 7th resistance is connected with first input voltage, second end is connected with the negative electrode of zener diode, and said first input voltage also is connected with the collector electrode of the 4th triode, the base stage of the 5th triode respectively through the 8th resistance; The base stage of said the 4th triode is connected with first end of the anode of voltage stabilizing didoe, the 6th resistance respectively, the emitter of said the 4th triode is connected with second end of said the 6th resistance and ground connection, and the base stage of said the 4th triode is second input of output unit; Said first input voltage also through the 9th resistance respectively with the collector electrode of the 5th triode, the positive pole of second electric capacity, first end of the tenth resistance; The emitter of said the 5th triode is connected ground connection with the negative pole of second electric capacity, and second end of said the tenth resistance is the output of output unit.
Further, said second input voltage is directly supply+5V-SB of power supply, and said second input voltage still is the supply power voltage of MCU; Said the 3rd input voltage is the VCC-5V that power supply is directly exported through the DC-DC module, and said the 3rd input voltage still is the main supply power voltage of system.
Further, said first input voltage is the 3.3V-SB of said second input voltage through the output of voltage stabilizing chip.
Further, said the 4th resistance, first electric capacity are formed the RC delay circuit, and the hysteresis output time of said RC delay circuit is by the parameter value decision of the 4th resistance, first electric capacity.
Further, said first triode is the positive-negative-positive triode; Said second triode, the 3rd triode are NPN type triode.
Further, the reverse breakdown voltage value of said voltage stabilizing didoe is less than 3.3V.
Further, said second electric capacity is polar capacitor.
Another purpose of the utility model also provides the television set with above-mentioned reset circuit.
The reset circuit that the utility model adopts is through supply voltage is monitored, when voltage dip occurring; System is resetted; System is reworked, effectively solved, improved sense of experience of users because problems such as the start of appearance is unusual fall in supply voltage temporarily.
Embodiment
For the purpose, technical scheme and the advantage that make the utility model is clearer,, the utility model is further elaborated below in conjunction with accompanying drawing and embodiment; Should be appreciated that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.
As shown in Figure 1; The reset circuit that the utility model provides; Comprise theoutput unit 101 that is used to export reset level, the first input end of saidoutput unit 101 is connected with first input voltage, and said reset circuit also comprises the monitoring means 102 that is used to monitor mains voltage variations; Said monitoring means 102
Output be connected with second input ofoutput unit 101, the first input end of said monitoring means 102, second input, the 3rd input respectively with second input voltage, the 3rd input voltage, Opportunity awaiting control for linear signal
STANDBY connects.
In the utility model embodiment, said second input voltage is directly supply+5V-SB of power supply, and said second input voltage+5V-SB still is the supply power voltage of MCU; Said the 3rd input voltage is the VCC-5V that power supply is directly exported through the DC-DC module, and said the 3rd input voltage VCC-5V still is the main supply power voltage of system; Said first input voltage is the 3.3V-SB of said second input voltage+5V-SB through the output of voltage stabilizing chip.
Said monitoring means 102 comprisesfirst resistance R 1, second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5, the first triode Q1, the second triode Q2, the 3rd triode Q3,first capacitor C 1;
One end of wherein saidfirst resistance R 1 is connected with second input voltage+5V-SB, and the other end is connected with the emitter of the first triode Q1; The base stage of the said first triode Q1 is connected with the 3rd input voltage VCC-5V through second resistance R 2, and the collector electrode of the said first triode Q1 is connected with the collector electrode of the second triode Q2; The base stage of the said second triode Q2 is connected with Opportunity awaiting control for linear signal STANDBY through the 3rd resistance R 3; Also successively through the 4th resistance R 4, first capacitor C, 1 back ground connection, the emitter of the said second triode Q2 is connected with the base stage of the 3rd triode Q3 through the 5th resistance R 5 base stage of the said second triode Q2; The grounded emitter of said the 3rd triode Q3, the current collection of said the 3rd triode Q3 is the output ofmonitoring means 102 very; The wherein said first triode Q1 is the positive-negative-positive triode, and the said second triode Q2, the 3rd triode Q3 are NPN type triode;
Said the 4th resistance R 4,first capacitor C 1 are formed the RC delay circuit, and the hysteresis output time of said RC delay circuit is by the parameter value decision of the 4th resistance R 4,first capacitor C 1.
Saidoutput unit 101 comprises the 6th resistance R 6, the 7th resistance R 7, the 8th resistance R 8, the 9th resistance R 9, the tenth resistance R 10, the 4th triode Q4, the 5th triode Q5, second capacitor C 2, voltage stabilizing didoe ZD1;
First end of wherein said the 7th resistance R 7 is connected with the first input voltage 3.3V-SB, second end is connected with the negative electrode of zener diode ZD1, and the said first input voltage 3.3V-SB also is connected with the collector electrode of the 4th triode Q4, the base stage of the 5th triode Q5 respectively through the 8th resistance R 8; The base stage of said the 4th triode Q4 is connected with first end of the anode of voltage stabilizing didoe ZD1, the 6th resistance R 6 respectively, the emitter of said the 4th triode Q4 is connected with second end of said the 6th resistance R 6 and ground connection, and the base stage of said the 4th triode Q4 is second input ofoutput unit 101; The said first input voltage 3.3V-SB also through the 9th resistance R 9 respectively with the collector electrode of the 5th triode Q5, the positive pole of second capacitor C 2, first end of the tenth resistance R 10; The emitter of said the 5th triode Q5 is connected ground connection with the negative pole of second capacitor C 2, and second end of said the tenth resistance R 10 is the output ofoutput unit 101; Wherein said second capacitor C 2 is a polar capacitor, and the reverse breakdown voltage value of said voltage stabilizing didoe ZD1 is less than 3.3V.
In the utility model embodiment, Opportunity awaiting control for linear signal STANDBY is the standby signal that MCU gives power supply, and operate as normal is a high level, is low level during standby; Reset level ORESET low level resets.
This reset circuit operation principle is following:
After system's opening power; At first exporting second input voltage+5V_SB provides the operating voltage and the first input voltage 3V3-SB to output unit resetting voltage to be provided to MCU and since the first input voltage 3V3-SB voltage in uphill process less than the voltage stabilizing value of voltage stabilizing didoe ZD1, voltage stabilizing didoe ZD1 is in cut-off state; The 4th triode Q4 also is in cut-off state; The 5th triode Q5 then gets into conducting state, and reset level ORESET is in low level, and system carries out system reset earlier; When the first input voltage 3V3SB voltage during greater than the voltage stabilizing value of voltage stabilizing didoe ZD1; Voltage stabilizing didoe ZD1 conducting; The 4th triode Q4 gets into conducting state; The 5th triode Q5 then gets into cut-off state, and the first input voltage 3V3-SB charges through 9 pairs second capacitor C 2 of the 9th resistance R, and the charging interval is resetting time.After the completion that resets, MCU at first can provide an Opportunity awaiting control for linear signal STANDBY (high level), and power supply carries out operate as normal then, and each road voltage such as the 3rd input voltage VCC_5V is normally exported to other circuit of system, system's operate as normal.
The sequential of system boot is here: second input voltage+5V_SB (the first input voltage 3V3SB) → reset level output ORESET → Opportunity awaiting control for linear signal STANDBY → the 3rd input voltage VCC_5V; Because the RC delay circuit hysteresis output time of being made up of the 4th resistance R 4,first capacitor C 1 is grown (can change RC delay circuit hysteresis output time through the parameter value that changes the 4th resistance R 4, first capacitor C 1) than the hysteresis output time of the 3rd input voltage VCC_5V and Opportunity awaiting control for linear signal STANDBY; So after system's opening power; Opportunity awaiting control for linear signal STANDBY is a high level, but because the sequential relationship of system boot, before the second triode Q2 conducting; The 3rd input voltage VCC-5V is loaded into the base stage of the first triode Q1 through second resistance R 2; Then the first triode Q1 ends, and the second triode Q2 also ends, and promptlymonitoring means 102 can not work when operate as normal;Output unit 101 can not produce mistake output, has prevented that system's mistake from resetting.
When phenomenon that falling temporarily appears in supply voltage,, can keep work because the load of second input voltage+5V_SB is light; Opportunity awaiting control for linear signal STANDBY also keeps high level, but the 3rd input voltage VCC_5V can follow supply voltage and occur falling temporarily because circuit load is heavy very much; At this moment, the first triode Q1 is because the falling and conducting of the 3rd input voltage VCC_5V temporarily, and the conducting through the second triode Q2 simultaneously makes the 3rd triode Q3 also get into conducting state; Because the grounded emitter of the 3rd triode Q3; The current collection of then said the 3rd triode Q3 is low level very, thereby the 4th triode Q4 gets into cut-off state, and ending of the 4th triode Q4 makes the 5th triode Q5 get into conducting state; Reset level output ORESET is a low level, and system gets into reset mode.At this moment, system is through after resetting, rearming, thus solve because problems such as the start of appearance is unusual fall in supply voltage temporarily.
The reset circuit that the utility model adopts is through supply voltage is monitored, when voltage dip occurring; System is resetted; System is reworked, effectively solved, improved sense of experience of users because problems such as the start of appearance is unusual fall in supply voltage temporarily.
The above is merely the preferred embodiment of the utility model; Not in order to restriction the utility model; Any modification of being done within all spirit and principles at the utility model, be equal to replacement and improvement etc., all should be included within the protection range of the utility model.