Further; Logic control voltage gating circuit 310 comprises: comprise the 3rd transistor N31, the 4th transistor N32, the 5th transistor N33, the first inverter INV31, the second inverter INV32, first and door AND31, second with door AND32, the 3rd with an AND33; The grid of said the 3rd transistor N31 connect said first with the door AND31 output; The source electrode of said the 3rd transistor N31 meets the positive input Vs of the first operational amplifier OP31; The drain electrode of said the 3rd transistor N31 meets the 3rd reference voltage V ref_H; The grid of said the 4th transistor N32 connect said second with the door AND32 output, the source electrode of said the 4th transistor N32 meets the positive input Vs of the said first operational amplifier OP31, the drain electrode of said the 4th transistor N32 meets the sampled voltage FB_d of said sampled signal FB_d output; The grid of said the 5th transistor N33 connect the said the 3rd with the door AND33 output; The source electrode of said the 5th transistor N33 meets the positive input Vs of the said first operational amplifier OP31, and the drain electrode of said the 5th transistor N33 meets the 4th reference voltage V ref_B; The output of the said first inverter INV31 and the second inverter INV32 be connected respectively second with the door AND32 and the 3rd with the door AND33 input; The input of the said first inverter INV31 of output termination of the said first comparator C OMP31 and said first with the door AND31 an input, the input of the said second inverter INV32 of output termination of said hysteresis comparator COMP32, said first with the door AND31 another input and said second with the door AND32 an input.

Further, square wave generation circuit 205 comprises:

Said CS peak current comparator C OMP22 positive input receive in succession 2 select 1 selector output voltage V ref2; Negative input connects the current monitoring end pin CS of said PWM switch power controller, and the output of said CS peak current comparator is connected to the input of the first NAND gate I21; Said error comparator COMP23 positive input is connected to sampled signal FB_d output, and negative input connects current monitoring end pin, and the output of said error comparator COMP23 is connected to another input of the first NAND gate I21; The output of the first not gate I21 is held through the R that logical device connects rest-set flip-flop, the moving circuit Soft Driver of said rest-set flip-flop output control floppy drive, and the moving circuit output logic of floppy drive is connected respectively to the grid end of the first transistor N21 and transistor seconds N22;

The input of said oscillator OSC is connected with Vref1, Vref2, Iosc1 and Iosc2 signal; The output of said oscillator is connected to the S end of rest-set flip-flop; Oscillator OSC utilizes bias current Iosc1 and Iosc2 that oscillator OSC internal capacitance C41 is charged; When oscillator OSC internal capacitance C41 voltage during greater than Vref1, bias current Iosc1 and Iosc2 begin the discharge to oscillator OSC internal capacitance C41, when oscillator OSC capacitance voltage during less than Vref2; Bias current Iosc1 and Iosc2 begin the charging to oscillator OSC internal capacitance C41 again, and so circulation makes and is output as the concussion square-wave signal.Said oscillator OSC has also determined the maximum functional duty ratio of said PWM switch power controller.

Further, oscillator OSC comprises: comprise the 6th transistor P41, the 7th transistor P42, the 8th transistor P43, the 9th transistor P44, the tenth transistor P45, the 11 transistor N41, the tenth two-transistor N42, the 13 transistor N43, the 14 transistor N44, the 15 transistor N45, oscillator OSC internal capacitance C41, the second comparator C OMP41, the 3rd comparator C OMP42, the 4th with a door AND41, the 5th with a door AND42, the 3rd inverter INV41, the 4th inverter INV42, the 5th inverter INV43, hex inverter INV44 and the 7th inverter INV45;

The grid of said the 6th transistor P41 meets bias voltage Iosc1, and the source electrode of said the 6th transistor P41 meets the said second voltage source LVDD, and the drain electrode of said the 6th transistor P41 connects the source electrode of said the 7th transistor P42;

The grid of said the 7th transistor P42 meets bias voltage Iosc2, and the drain electrode of said the 7th transistor P42 connects the grid of the drain electrode of said the 6th transistor N42, said the 6th transistor N42 and the grid of said the 14 transistor N44;

The grid of said the 8th transistor P43 meets bias voltage Iosc1, and the source electrode of said the 6th transistor P41 meets the said second voltage source LVDD, and the drain electrode of said the 8th transistor P43 connects the source electrode of said the 9th transistor P44;

The grid of said the 9th transistor P44 meets bias voltage Iosc2; The drain electrode of said the 9th transistor P44 connects the source electrode of said the tenth transistor P45; The grid of said the tenth transistor P45 connects the output of said hex inverter INV44 and the input of said the 7th inverter INV45, and the drain electrode of said the tenth transistor P45 connects the drain terminal of said the 15 transistor N45, said oscillator OSC internal capacitance C41 positive pole, the negative input of the said second comparator C OMP41 and the positive input of said the 3rd comparator C OMP42;

The source electrode of said the tenth two-transistor N42 connects the grid of the drain electrode of said the 11 transistor N41, said the 11 transistor N41 and the grid of said the 13 transistor N43;

The source ground of said the 11 transistor N41, the source ground of said the 13 transistor N43, the drain electrode of said the 13 transistor N43 connects the source electrode of said the 14 transistor N44;

The source electrode of said the 15 transistor N45 connects the drain electrode of said the 14 transistor N44, the grid of said the 15 transistor N45 connect the output of said the 4th inverter INV42, said the 5th inverter INV43 input and the said the 4th with the door AND41 an input;

The positive input of the said second comparator C OMP41 meets the first reference voltage V ref1, the output termination the said the 4th of the said second comparator C OMP41 and another input of door AND41;

The negative input of said the 3rd comparator C OMP42 connects voltage 2 and selects 1 the output second reference voltage V ref2, the output termination the said the 5th of said the 3rd comparator C OMP42 and the input of door AND42;

The said the 4th with the input of said the 3rd inverter INV41 of output termination of door AND41; The output termination the said the 5th of said the 3rd inverter INV41 and another input of door AND42; The said the 5th with the input of said the 4th inverter INV42 of output termination of door AND42; The input of the said hex inverter INV44 of output termination of said the 5th inverter INV43, the output of said the 7th inverter INV45 form oscillator square-wave signal CLK.

Further; Square wave generation circuit 205 also comprises lead-edge-blanking circuit LEB; The input of said lead-edge-blanking circuit LEB is connected to square-wave signal PWM end; And trigger lead-edge-blanking circuit LEB shielding time delay by the rising edge of said square-wave signal PWM; The output of said lead-edge-blanking circuit LEB is connected to the input of the second NAND gate I22, and the output of the first NAND gate I21 is connected to another input of the second not gate I22, and the output of the second NAND gate I22 is connected to the R end of rest-set flip-flop; Or square wave generation circuit 205 also comprises negative circuit, and the output of the first not gate I21 connects the R end of rest-set flip-flop through negative circuit.

The utility model embodiment also provides a kind of Switching Power Supply, and the Switching Power Supply body is provided with like aforesaid pulse width modulating switch power source controller.

This pulse width modulating switch power source controller is integrated brand-new frequency conversion mode of operation and discontinuous operation pattern, can make the switching frequency of system can be along with alleviating of load step-down, reduce power consumption to greatest extent.In order to achieve the above object; The utility model is according to the sampled signal FB_d size decision-making system load condition of the feedback voltage signal FB of error amplifier; Thereby confirm the mode of operation of PWM switch power controller; Selecting module to produce the corresponding work electric current through current-mode then is used for the control generator operating frequency, realizes the self adaptation of system works frequency under the different loads.System works frequency self-adaption process is following: when system load was heavy condition, the AC/DC Switching Power Supply of said a kind of low standby power loss was operated in the maximum system operating frequency; The supposing the system load begins to reduce load from heavy condition; Before load is reduced to the load critical condition that the AC/DC Switching Power Supply of said a kind of low standby power loss sets; The AC/DC Switching Power Supply of said a kind of low standby power loss still is operated in the maximum system operating frequency; After load was reduced to said load critical condition, the AC/DC Switching Power Supply of said a kind of low standby power loss reduced power consumption along with the reduction of load condition begins to reduce switching frequency; In load under the very light or no-load condition; System gets into intermittent mode, and the AC/DC Switching Power Supply of said a kind of low standby power loss can be closed transducer output fully, only relies on the transformer energy stored to keep loaded work piece; When energy decreases arrives certain value; Restarting transducer is the transformer makeup energy, repeats to close the action of transducer output afterwards again, reaches the further purpose that has reduced said Switching Power Supply stand-by power consumption through such method.

Description of drawings

Fig. 1 is the AC/DC switch power supply system application structure block diagram of a kind of low standby power loss of the utility model;

Fig. 2 is a kind of pulse width modulating switch power source controller internal circuit principle assumption diagram of the utility model;

Fig. 3 is the current-mode selecting circuit structure figure that is used to control the adaptive oscillator frequency of the utility model;

Fig. 4 is the structure chart of the frequency self-adaption oscillator of the AC/DC Switching Power Supply that is used for a kind of low standby power loss of the utility model.

The main element description of symbols

101: a kind of AC/DC Switching Power Supply of low standby power loss

201: soft starting circuit

The 202:FB sample circuit

203: current-mode is selected circuit

204: the frequency self-adaption oscillator

205: square wave generation circuit

310: logic control voltage gating circuit

Embodiment

Carry out detailed explanation below in conjunction with accompanying drawing and embodiment.

Consult Fig. 1, be the AC/DC switch power supply system application structure block diagram of a kind of low standby power loss of the utility model.It is initial to power on;Power switch pipe 107 is closed, and AC power is charged through 103 pairs of electric capacity ofstarting resistance 104 throughbridge rectifier 102, when voltage is higher than chip UVLO_OFF on theelectric capacity 104; Said PWM Switching PowerSupply 101 starts, and sends and enable 107 conductings of signal triggering power switch pipe; The electric current that flows throughtransformer 106 primary inductances in 107 conduction periods of power tube flows through CS peakcurrent detection resistance 108 with the controlled rate of rise; PWMSwitching Power Supply 101 detects the pressure drop that produces on the CS peakcurrent detection resistance 108, thereby power controllingswitching tube 107 turn-offs; After power tube turn-offs; The crest voltage at 105 pairs of transformers of the clamped circuit of RCD, 106 elementary winding two ends carries out clamped; Transformer 106 secondary winding provide energy through 113 pairs of outputs of output rectifier diode, andtransformer 106 auxiliary windings provide energy through 114 couples of VDD of VDD rectifier diode simultaneously; Outputvoltage sampling resistor 110 relatively amplifies with the magnitude of voltage and theerror amplifier 112 of resistance 111 series connection dividing potential drops;Error amplifier 112 relatively amplifies later electric current and flows throughoptical coupling amplifier 109; Amplify the FB function leads ends that later electric current flows through PWM Switching Power Supply 101 throughoptical coupling amplifier 109; PWM Switching Power Supply 101 produces the corresponding work electric current through the size that detects FB end feedback current and is used for the control generator operating frequency, realizes the self adaptation of system works frequency under the different loads.The operating frequency that can make system reduces and reduces with load, reduces power consumption to greatest extent, promotes efficient.

Consult Fig. 2,3,4, wherein the pulse width modulating switch power source controller comprises:

Square wave generation circuit 205; The first input end of square wave generation circuit 205, second input, the 3rd input, four-input terminal, the 5th input, the 6th input; Connect peak-limitation voltage vth1, current monitoring end pin CS, sampled signal FB_d output, the first reference voltage V ref1, the oscillator first electric current I osc1 output and the second electric current I osc2 output of current monitoring end pin CS input voltage respectively; 205 the first output logic signal output, the second output logic signal output; Be connected respectively to the grid end of transistor N21 and transistor N22, the 205 peak-limitation voltage vth1 according to current monitoring end pin CS input voltage, current monitoring end pin CS signal, sampled signal FB_d, the first reference voltage V ref1, the oscillator first electric current I osc1 and the second electric current I osc2 obtain first output logic signal and second output logic signal of switch power controller;

The grid end of transistor N21 is also clamped to the reverse breakdown voltage on ground through diode D23; The drain terminal of transistor N21 is connected to supply power voltage pin vdd terminal; The source end of transistor N22 is connected to ground; The source end of transistor N21 and the control output end GATE function pin that is connected to said PWM switch power controller after the drain terminal of transistor N22 is connected, said GATE function leads ends is resistance R 25 of series connection to ground.

Further; Current-mode is selected the second input termination RI pin of circuit 203; And obtain reference current Iref in view of the above, 205 also according to the first reference voltage V ref1 and second reference voltage V ref2 output clock square wave CLK, wherein; Reference voltage V ref2 is the peak-limitation voltage vth1 of current monitoring end pin CS input voltage; Also comprise soft starting circuit 201, the first input end of soft starting circuit 201 connects reference current Iref output, the second input termination clock square wave CLK output of soft starting circuit 201; And under the control of output clock square wave CLK, adopt reference current Iref charging to make output rise to the peak-limitation voltage vth1 of current monitoring end pin CS input voltage.

Further; Soft starting circuit 201 comprises charge pump PUMP circuit; Said charge pump PUMP circuit input end is controlled by oscillator output square-wave signal CLK and reference current Iref jointly; Its output voltage SS is connected to soft start termination comparator C OMP21 and gets positive input, exports the selection control signal with COMP21 negative input voltage vth1 result relatively, and 2 select the first input end selecting of 1 selector to select control signal output ends; And according to selecting control signal from the peak-limitation voltage vth1 of the current monitoring end pin CS input voltage of input and charge pump PUMP circuit input voltage SS, to select output reference voltage Vref2.

Further, FB sample circuit 202 also comprises diode D21, diode D22, resistance R 21, resistance R 22, resistance R 23, resistance R 24, and the negative pole of said diode D21 meets feedback pin fb; And link to each other with the negative pole of resistance R 21; The negative pole of the anodal connecting resistance R22 of diode D21, and link to each other with the positive pole of diode D22, said resistance R 21 positive poles link to each other with second source LVDD; Resistance R 22 positive poles link to each other with second source LVDD; The positive pole of resistance R 23 links to each other with the negative pole of diode D22, and the negative pole of resistance R 23 links to each other with the positive pole of resistance R 24, and the negative pole of resistance R 24 is connected to grounding pin.

Further; Current-mode selects circuit 203 also to comprise: logic control voltage gating circuit 310, grounding pin end transistor N34, oscillator electric current I osc1 end transistor P31, oscillator electric current I osc2 end transistor P32, comparator C OMP31, hysteresis comparator COMP32, operational amplifier OP31, operational amplifier OP32, operational amplifier OP33, resistance R 31; The 3rd operational amplifier OP33 positive input is connected to the 2V direct voltage; Negative input is connected to the RI pin with output; And the outer meeting resistance R115 that passes through the RI pin forms bias current Iref; The second operational amplifier OP32 positive input is connected to direct voltage Vref_L; The second operational amplifier OP32 negative input is connected to an end of the 6th resistance R 31 with output; The first operational amplifier OP31 positive input is connected to the output Vs of logic control voltage gating circuit 310, and the first operational amplifier OP31 negative input is connected to the other end of the 6th resistance R 31 and the source end of grounding pin end transistor N34, and the output of the first operational amplifier OP31 is connected to the grid end of grounding pin end transistor N34; The drain terminal of grounding pin end transistor N34 is connected to drain terminal and the grid end Iosc2 of the oscillator second electric current I osc2 end transistor P32; The source end of the oscillator second electric current I osc2 end transistor P32 is connected to grid end and the drain terminal Iosc1 of the oscillator first electric current I osc1 end transistor P31; The source end of the oscillator first electric current I osc1 end transistor P31 is connected to inner low-tension supply LVDD, and first input pin of logic control voltage gating circuit 310 links to each other with the output of COMP31; Second input pin links to each other with the output of COMP32; The 3rd input pin links to each other with the negative input Vref_H of COMP31; The 4th input pin links to each other with the positive input FB_d of COMP31 and COMP32; The 5th input pin links to each other with the negative input Vref_B of COMP32; 310 output links to each other with the positive input of OP31; Wherein logic control voltage gating circuit 310 is used for exporting the different voltages with different value through judging the voltage range of FB_d,

In the time of FB_d>=Vref_H; Vs=Vref_H; Vref_H is first reference voltage, and oscillator charging and discharging currents

oscillator is sent out ripple with fixing operating frequency;

Further; Logic control voltage gating circuit 310 comprises: comprise transistor N31, transistor N32, transistor N33, inverter INV31, inverter INV32, with a door AND31, with a door AND32, with a door AND33; The grid of said transistor N31 connects output said and door AND31; The source electrode of said transistor N31 meets the positive input Vs of operational amplifier OP31; The drain electrode of transistor N31 meets direct voltage Vref_H; The grid of said transistor N32 connects output said and door AND32, and the source electrode of said transistor N32 meets the positive input Vs of said operational amplifier OP31, and the drain electrode of transistor N32 meets the sampled voltage FB_d of said sampled signal FB_d output; The grid of transistor N33 connects the output with door AND33, and the source electrode of transistor N33 meets the positive input Vs of operational amplifier OP31, and the drain electrode of transistor N33 meets direct voltage Vref_B; The output of inverter INV31 and inverter INV32 be connected respectively with door AND32 and with the input of door AND33; The input of the said inverter INV31 of output termination of said comparator C OMP31 and with the input of door AND31, the input of the said inverter INV32 of output termination of said hysteresis comparator COMP32, with another input of door AND31 and with the input of door AND32.

Further, square wave generation circuit 205 comprises:

Said CS peak current comparator C OMP22 positive input receive in succession 2 select 1 selector output voltage V ref2; Negative input connects the current monitoring end pin CS of said PWM switch power controller, and the output of said CS peak current comparator is connected to the input of NAND gate I21; Said error comparator COMP23 positive input is connected to sampled signal FB_d output, and negative input connects current monitoring end pin promptly, and the output of error comparator COMP23 is connected to another input of NAND gate I21; The output of not gate I21 is held through the R that logical device connects rest-set flip-flop, the moving circuit Soft Driver of said rest-set flip-flop output control floppy drive, and the moving circuit output logic of floppy drive is connected respectively to the grid end of transistor N21 and transistor N22;

Further, oscillator OSC comprises: comprise transistor P41, transistor P42, transistor P43, transistor P44, transistor P45, transistor N41, transistor N42, transistor N43, transistor N44, transistor N45, oscillator OSC internal capacitance C41, comparator C OMP41, comparator C OMP42, with a door AND41, with a door AND42, inverter INV41, inverter INV42, inverter INV43, inverter INV44 and inverter INV45;

The grid of said transistor P41 meets bias voltage Iosc1, and the source electrode of said transistor P41 meets the said second voltage source LVDD, and the drain electrode of said transistor P41 connects the source electrode of said transistor P42;

The grid of said transistor P42 meets bias voltage Iosc2, and the drain electrode of said transistor P42 connects the drain electrode of transistor N42, the grid of transistor N42 and the grid of transistor N44;

The grid of transistor P43 meets bias voltage Iosc1, and the source electrode of transistor P41 meets the said second voltage source LVDD, and the drain electrode of transistor P43 connects the source electrode of transistor P44;

The grid of transistor P44 meets bias voltage Iosc2; The drain electrode of transistor P44 connects the source electrode of transistor P45; The grid of transistor P45 connects the output of inverter INV44 and the input of inverter INV45, and the drain electrode of transistor P45 connects the drain terminal of transistor N45, said oscillator OSC internal capacitance C41 positive pole, the negative input of comparator C OMP41 and the positive input of comparator C OMP42;

The source electrode of transistor N42 connects the drain electrode of transistor N41, the grid of transistor N41 and the grid of transistor N43;

The source ground of transistor N41, the source ground of transistor N43, the drain electrode of transistor N43 connects the source electrode of transistor N44;

The source electrode of transistor N45 connects the drain electrode of transistor N44, the grid of transistor N45 connect inverter INV42 output, inverter INV43 input and with the input of door AND41;

The positive input of comparator C OMP41 meets the first reference voltage V ref1, another input of the output termination of comparator C OMP41 and door AND41;

The negative input of comparator C OMP42 connects voltage 2 and selects 1 output reference voltage Vref2, the input of the output termination of comparator C OMP42 and door AND42;

Input with the output termination inverter INV41 of door AND41; Another input of the output termination of inverter INV41 and door AND42; Input with the output termination inverter INV42 of door AND42; The input of the output termination inverter INV44 of inverter INV43, the output of inverter INV45 form oscillator square-wave signal CLK.

Further; Square wave generation circuit 205 also comprises lead-edge-blanking circuit LEB; The input of said lead-edge-blanking circuit LEB is connected to square-wave signal PWM end, and triggers lead-edge-blanking circuit LEB shielding time delay by the rising edge of said square-wave signal PWM, and the output of said lead-edge-blanking circuit LEB is connected to the input of NAND gate I22; The output of NAND gate I21 is connected to another input of not gate I22, and the output of NAND gate I22 is connected to the R end of rest-set flip-flop; Or square wave generation circuit 205 also comprises negative circuit, and the output of the first not gate I21 connects the R end of rest-set flip-flop through negative circuit.

The embodiment of the utility model provides a kind of pulse width modulating switch power source controller; The sampled signal FB d size decision-making system load condition of feedback voltage signal FB through error amplifier; Thereby confirm the mode of operation of PWM switch power controller; Selecting module to produce the corresponding work electric current through current-mode then is used for the control generator operating frequency, realizes the self adaptation of system works frequency under the different loads.The operating frequency that can make system reduces and reduces with load, reduces power consumption to greatest extent, promotes efficient.

Explain for convenient, below discuss with reference to anti-and swash topological AC/DC Switching Power Supply, but the person of ordinary skill in the field will recognize that the utility model also can be applicable to the PWM Mode A C/DC switch power supply system of other type.Understand simultaneously the technical scheme of the utility model better, will combine accompanying drawing and execution mode that the embodiment of the utility model is done further detailed description below for the technical staff who makes the present technique field.

Like prepulse width modulated switch power controller, comprise soft starting circuit 201, FB sample circuit 202, current-mode selection circuit 203, frequency self-adaption oscillator 204, CS peak current comparator C OMP22, error comparator COMP23, rest-set flip-flop, lead-edge-blanking circuit LEB, the moving circuit Soft Driver of floppy drive, resistance R 25, diode D23, transistor N21 and N22, NAND gate I21 and I22.

By knowing among the figure two; Soft starting circuit 201 charges a period of time to charge pump PUMP is fixing at each cycle inner control reference current Iref of the output square wave CLK of frequency self-adaption oscillator 204, so the output voltage SS of charge pump PUMP is along with each clk cycle constantly increases.In the time of SS≤vth1, Vref2=SS; In the time of SS＞vth1, Vref2=vth1.The output voltage SS of charge pump PUMP is simultaneously relevant with frequency self-adaption oscillator 204 with CS peak current comparator C OMP22, thus in soft start state CS peak current and adaptive oscillator frequency all along with the voltage rising of SS and increase.The size of FB sample circuit 202 sample detecting FB end feedback current; And feedback current changed the change in voltage change into FB_d; Thereby pass through error comparator COMP23 and CS voltage ratio; Thereby the conducting duty ratio of power controllingswitching tube 107, current-mode selects circuit 203 to be used for the control generator operating frequency according to corresponding oscillator electric current I osc1 and the Iosc2 of voltage range generation of FB_d simultaneously, realizes the self adaptation of system works frequency under the different loads.The voltage relationship of FB_d and FB end is approximately equal to:

FB_d = FB \times \frac{R 24}{R 23 + R 24} - - - (1)

It is high that the output square wave CLK of adaptive oscillator 204 triggers the moving circuit Soft Driver driving of floppy drive GATE function pin through rest-set flip-flop, thereby makespower switch pipe 107 conductings.CS peak current comparator C OMP22 and error comparator COMP23 be 107 turn-off times of power controlling switching tube point after the blanking circuit LEB shielding time ahead of the curve then, and the maximum ON time ofpower switch pipe 107 is by the output square wave CLK decision of adaptive oscillator 204.

Current-mode like preceding control adaptive oscillator frequency is selected circuit, comprises logic control voltage gating circuit 310, transistor N34, transistor P31, transistor P32, comparator C OMP31, hysteresis comparator COMP32, operational amplifier OP31, operational amplifier OP32, operational amplifier OP33, resistance R 31.Operational amplifier OP33 positive input connects the reference voltage of 2V, and its output and negative input short circuit form the source with amplifier, and be connected to PWMSwitching Power Supply 101 RI function leads ends, and form bias current Iref with resistance 115:

Iref = \frac{2}{R_{RI}} - - - (2)

By knowing among the figure, be core with operational amplifier OP31 and OP32, constitute two negative feedback structures, and determined the size of oscillator charging and discharging currents with resistance R 31.

Iosc = \frac{Vs - Vref_L}{R 31} - - - (3)

Comparator C OMP31 and hysteresis comparator COMP32 select a conducting among transistor N31, transistor N32, the transistor N33 according to the voltage range of FB_d, thereby form different Vs magnitudes of voltage.The magnitude of voltage of supposing FB_d changes from high to low:

In the time of FB_d>=Vref_H; Vs=Vref_H, oscillator charging and discharging currents

oscillator is sent out ripple with fixing operating frequency;

In the time of Vref_H＜FB_d>=Vref_M-Vos; Vs=FB_d, the operating frequency of oscillator charging and discharging currents

In the time of FB_d＜Vref_M-Vos; Vs=Vref_B; Under oscillator charging and discharging currents

output loading underloading or the Light Condition, oscillator is with the intermittent ripple of sending out of minimum frequency of operation;

The magnitude of voltage of supposing FB_d changes from low to high:

In the time of FB_d＜Vref_M+Vos; Vs=Vref_B; Under oscillator charging and discharging currents

In the time of Vref_H＜FB_d>=Vref_M+Vos; Vs=FB_d, the operating frequency of oscillator charging and discharging currents

In the time of FB_d>=Vref_H; Vs=Vref_H, oscillator charging and discharging currents oscillator is sent out ripple with fixing operating frequency;

Wherein, Vref_H, Vref_M, Vref_B and Vref_L are reference voltage value; Vos is the hysteresis voltage value of comparator C OMP32, Vref_H＞Vref_M＞Vref_M-Vos＞Vref_B＞Vref_L between the stagnant regions that is used to a kind of AC/DC Switching Power Supply entering of low standby power loss is set and withdraw from an intermittent ripple.

Like the frequency self-adaption oscillator OSC circuit of the AC/DC Switching Power Supply of preceding low standby power loss, comprise transistor P41, transistor P42, transistor P43, transistor P44, transistor P45, transistor N41, transistor N42, transistor N43, transistor N44, transistor N45, capacitor C 41, comparator C OMP41, comparator C OMP42, with a door AND41, with a door AND42, inverter INV41, inverter INV42, inverter INV43, inverter INV44 and inverter INV45.Said oscillator charges to capacitor C 41 through the oscillator bias current of transistor P43 and transistor P44; After the voltage of C41 is greater than Vref1; CP logical signal oxide-semiconductor control transistors P45 turn-offs oscillator biasing charging current; The discharging current of CN logical signal oxide-semiconductor control transistors N45 oscillator biasing simultaneously discharges to capacitor C 41 through the oscillator bias current of transistor N43 and transistor N44, when the voltage of C41 less than after Vref2; CP logical signal oxide-semiconductor control transistors P45 is conducting oscillator biasing charging current once more, so moves in circles to form concussion output logic signal CLK.It should be noted that Vref2=SS in soft start-up process, so the frequency of oscillation of CLK also raises along with the rising of soft starting circuit output voltage in the soft start engineering.

The sampled signal FB_d size decision-making system load condition of feedback voltage signal FB through error amplifier; Thereby confirm the mode of operation of PWM switch power controller; Selecting module to produce the corresponding work electric current through current-mode then is used for the control generator operating frequency, realizes the self adaptation of system works frequency under the different loads.The operating frequency that can make system reduces and reduces with load, reduces power consumption to greatest extent, promotes efficient.

The above only is the preferred implementation of the utility model; Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the utility model principle; Can also do some improvement and retouching, these improvement and retouching also should be regarded as the protection range of the utility model.

Claims

1. a pulse width modulating switch power source controller is characterized in that: comprise that supply power voltage pin, grounding pin, feedback pin fb, control output end pin gate, current monitoring end pin cs and bias current are provided with port RI pin; And

2. pulse width modulating switch power source controller according to claim 1; It is characterized in that current-mode is selected the second input termination RI pin of circuit 203, and obtains reference current Iref in view of the above; 205 also according to the first reference voltage V ref1 and second reference voltage V ref2 output clock square wave CLK; Wherein, the second reference voltage V ref2 is the peak-limitation voltage vth1 of current monitoring end pin CS input voltage, also comprises soft starting circuit 201; The first input end of soft starting circuit 201 connects reference current Iref output; The second input termination clock square wave CLK output of soft starting circuit 201, and under the control of output clock square wave CLK, adopt reference current Iref charging to make output rise to the peak-limitation voltage vth1 of current monitoring end pin CS input voltage.

3. pulse width modulating switch power source controller according to claim 2; It is characterized in that; Soft starting circuit 201 comprises charge pump PUMP circuit; Said charge pump PUMP circuit input end is controlled by oscillator output square-wave signal CLK and reference current Iref jointly; Its output voltage SS is connected to soft start termination comparator C OMP21 and gets positive input, exports the selection control signal with COMP21 negative input voltage vth1 result relatively, and 2 select the first input end selecting of 1 selector to select control signal output ends; And, export the second reference voltage V ref2 according to selecting control signal from the peak-limitation voltage vth1 of the current monitoring end pin CS input voltage of input and charge pump PUMP circuit input voltage SS, to select.

4. pulse width modulating switch power source controller according to claim 1; It is characterized in that FB sample circuit 202 also comprises the second diode D21, the 3rd diode D22, second resistance R 21, the 3rd resistance R 22, the 4th resistance R 23, the 5th resistance R 24, the negative pole of the said second diode D21 meets feedback pin fb; And link to each other with the negative pole of second resistance R 21; The positive pole of the second diode D21 connects the negative pole of the 3rd resistance R 22, and links to each other with the positive pole of the 3rd diode D22, and said second resistance R, 21 positive poles link to each other with second source LVDD; The 3rd resistance R 22 positive poles link to each other with second source LVDD; The positive pole of the 4th resistance R 23 links to each other with the negative pole of the 3rd diode D22, and the negative pole of the 4th resistance R 23 links to each other with the positive pole of the 5th resistance R 24, and the negative pole of the 5th resistance R 24 is connected to grounding pin.

5. pulse width modulating switch power source controller according to claim 1; It is characterized in that; Current-mode selects circuit 203 also to comprise: logic control voltage gating circuit 310, grounding pin end transistor N34, the oscillator first electric current I osc1 end transistor P31, the oscillator second electric current I osc2 end transistor P32, the first comparator C OMP31, hysteresis comparator COMP32, the first operational amplifier OP31, the second operational amplifier OP32, the 3rd operational amplifier OP33, the 6th resistance R 31; The 3rd operational amplifier OP33 positive input is connected to the 2V direct voltage; Negative input is connected to the RI pin with output; And the outer meeting resistance R115 that passes through the RI pin forms bias current Iref; The second operational amplifier OP32 positive input is connected to the 4th reference voltage Vref _ L; The second operational amplifier OP32 negative input is connected to an end of the 6th resistance R 31 with output; The first operational amplifier OP31 positive input is connected to the output Vs of logic control voltage gating circuit 310, and the first operational amplifier OP31 negative input is connected to the other end of the 6th resistance R 31 and the source end of grounding pin end transistor N34, and the output of the first operational amplifier OP31 is connected to the grid end of grounding pin end transistor N34; The drain terminal of grounding pin end transistor N34 is connected to drain terminal and the grid end Iosc2 of the oscillator second electric current I osc2 end transistor P32; The source end of the oscillator second electric current I osc2 end transistor P32 is connected to grid end and the drain terminal Iosc1 of the oscillator first electric current I osc1 end transistor P31; The source end of the oscillator first electric current I osc1 end transistor P31 is connected to inner low-tension supply LVDD, and first input pin of logic control voltage gating circuit 310 links to each other with the output of COMP31; Second input pin links to each other with the output of COMP32; The 3rd input pin links to each other with the negative input Vref_H of COMP31; The 4th input pin links to each other with the positive input FB_d of COMP31 and COMP32; The 5th input pin links to each other with the negative input Vref_B of COMP32; 310 output links to each other with the positive input of OP31; Wherein logic control voltage gating circuit 310 is used for exporting the different voltages with different value through judging the voltage range of FB_d,

oscillator is sent out ripple with fixing operating frequency;

In the time of Vref_H＜FB_d>=Vref_M-Vos; Vs=FB_d; Vref_M is the 3rd reference voltage, and the operating frequency of oscillator charging and discharging currents oscillator begins to reduce along with the reduction of output loading frequency;

In the time of FB_d＜Vref_M-Vos; Vs=Vref_B; Vref_B is second reference voltage; Under oscillator charging and discharging currents output loading underloading or the Light Condition, oscillator is with the intermittent ripple of sending out of minimum frequency of operation.

6. pulse width modulating switch power source controller according to claim 1; It is characterized in that; Logic control voltage gating circuit 310 comprises: comprise the 3rd transistor N31, the 4th transistor N32, the 5th transistor N33, the first inverter INV31, the second inverter INV32, first and door AND31, second with door AND32, the 3rd with an AND33; The grid of said the 3rd transistor N31 connect said first with the door AND31 output; The source electrode of said the 3rd transistor N31 meets the positive input Vs of the first operational amplifier OP31; The drain electrode of said the 3rd transistor N31 meets the 3rd reference voltage V ref_H; The grid of said the 4th transistor N32 connect said second with the door AND32 output, the source electrode of said the 4th transistor N32 meets the positive input Vs of the said first operational amplifier OP31, the drain electrode of said the 4th transistor N32 meets the sampled voltage FB_d of said sampled signal FB_d output; The grid of said the 5th transistor N33 connect the said the 3rd with the door AND33 output; The source electrode of said the 5th transistor N33 meets the positive input Vs of the said first operational amplifier OP31, and the drain electrode of said the 5th transistor N33 meets the 4th reference voltage V ref_B; The output of the said first inverter INV31 and the second inverter INV32 be connected respectively second with the door AND32 and the 3rd with the door AND33 input; The input of the said first inverter INV31 of output termination of the said first comparator C OMP31 and said first with the door AND31 an input, the input of the said second inverter INV32 of output termination of said hysteresis comparator COMP32, said first with the door AND31 another input and said second with the door AND32 an input.

7. pulse width modulating switch power source controller according to claim 1 is characterized in that, square wave generation circuit 205 comprises:

The input of said oscillator OSC is connected with Vref1, Vref2, Iosc1 and Iosc2 signal; The output of said oscillator is connected to the S end of rest-set flip-flop; Oscillator OSC utilizes bias current Iosc1 and Iosc2 that oscillator OSC internal capacitance C41 is charged; When oscillator OSC internal capacitance C41 voltage during greater than Vref1; Bias current Iosc1 and Iosc2 begin oscillator OSC internal capacitance C41 discharge, and when oscillator OSC capacitance voltage during less than Vref2, bias current Iosc1 and Iosc2 begin again oscillator OSC internal capacitance C41 is charged; So circulation makes and is output as the concussion square-wave signal, and said oscillator OSC has also determined the maximum functional duty ratio of said PWM switch power controller.

8. pulse width modulating switch power source controller according to claim 7; It is characterized in that oscillator OSC comprises: comprise the 6th transistor P41, the 7th transistor P42, the 8th transistor P43, the 9th transistor P44, the tenth transistor P45, the 11 transistor N41, the tenth two-transistor N42, the 13 transistor N43, the 14 transistor N44, the 15 transistor N45, oscillator OSC internal capacitance C41, the second comparator C OMP41, the 3rd comparator C OMP42, the 4th with a door AND41, the 5th with a door AND42, the 3rd inverter INV41, the 4th inverter INV42, the 5th inverter INV43, hex inverter INV44 and the 7th inverter INV45;

9. pulse width modulating switch power source controller according to claim 7; It is characterized in that; Square wave generation circuit 205 also comprises lead-edge-blanking circuit LEB; The input of said lead-edge-blanking circuit LEB is connected to square-wave signal PWM end, and triggers lead-edge-blanking circuit LEB shielding time delay by the rising edge of said square-wave signal PWM, and the output of said lead-edge-blanking circuit LEB is connected to the input of the second NAND gate I22; The output of the first NAND gate I21 is connected to another input of the second not gate I22, and the output of the second NAND gate I22 is connected to the R end of rest-set flip-flop; Or square wave generation circuit 205 also comprises negative circuit, and the output of the first not gate I21 connects the R end of rest-set flip-flop through negative circuit.

10. Switching Power Supply, it is characterized in that: the Switching Power Supply body is provided with like the described pulse width modulating switch power source controller of the arbitrary claim of claim 1 to 9.