CN201716968U - Angle cutting circuit and liquid crystal drive circuit with same - Google Patents

Abstract

The utility model discloses an angle cutting circuit and a liquid crystal drive circuit with same. The angle cutting circuit comprises a first switching circuit of which the on/off state is controlled by a sequential control off signal, wherein an on/off path of the first switching circuit is connected between the input end of a DC power supply and an angle cutting voltage output end, and a voltage stabilizing circuit is also connected with the angle cutting voltage output end and selects access according to a sequential control on signal. The angle cutting circuit adopting simple discrete components not only eliminates the dependence on special integrated chips and lowers the overall cost, but also has the advantages of simple structural design, small component use amount, small occupation area on PCB (Printed Circuit Board) and high circuit operating reliability. The angle cutting circuit is applied in the drive circuit design of liquid crystal display screens of such household appliances as liquid crystal televisions and the like, thereby not only effectively controlling the production cost, but also facilitating the miniaturized design of devices.

Description

A kind of top rake circuit and have the liquid crystal display drive circuit of this circuit

Technical field

The utility model belongs to LCDs driving circuit technical field, specifically, relate to the top rake circuit of the required cut-in voltage of a kind of line scanning end that is used to produce LCDs (being the gate end) and based on the designed LCDs driving circuit of this top rake circuit.

Background technology

LCDs (LCD) is to utilize the electric field intensity be clipped on the liquid crystal molecule to change the orientation that changes liquid crystal molecule, and then comes display image by the power of control liquid crystal molecule printing opacity.At present, LCDs is because in light weight, characteristics such as volume is little, thin thickness that himself had, and is widely used in the terminal presentation facility of full range of sizes.In general, LCDs comprises LCD panel with picture element matrix and the driving circuit that is used to drive this LCD panel.At the design aspect of driving circuit, most special integrated chip ASIC that use produce the cut-in voltages that drive liquid crystal deflecting element, i.e. VGH voltage transfers to the gate end of LCDs, i.e. the line scanning end.

The top rake circuit is the part of LCDs driving circuit, usually the liquid crystal molecule array is sent high level successively from the gate end of liquid crystal display pannel and is opened liquid crystal molecule, data are sent into the data line of liquid crystal molecule array simultaneously, and data are write line by line like this.When the speed of gate end scanning liquid crystal molecule was enough fast, liquid crystal display just can show continuous video image.Usually, the voltage VGH that opens liquid crystal molecule is about 30V, in order to satisfy the characteristic of liquid crystal molecule, need handle the VGHP voltage of direct current by the top rake circuit, generates the VGH voltage of waveform as shown in Figure 1 with conversion.Wherein, VGHP voltage is the DC voltage about 30V; VGH voltage is through the output voltage after the top rake processing of circuit.

In present LCDs design of drive circuit, most special integrated chip U1 that adopt design described top rake circuit, circuit structure as shown in Figure 2.The DC voltage VGHP of the power input reception+30V of integrated chip U1, and signal GVON is opened in the sequential control of time schedule controller output in liquid crystal display and jointly controlling under the effect of signal GVOFF closed in sequential control, direct current VGHP voltage is carried out top rake to be handled, to generate and to export the cut-in voltage VGH of waveform as shown in Figure 1, and then transfer to the gate end of liquid crystal display, be used to open liquid crystal molecule.Fig. 3 and Fig. 4 are respectively the typical waveform figure of GVON signal and GVOFF signal, and the amplitude of these two signals all is consistent with phase place, only difference to some extent on dutycycle.

Employing special integrated chip ASIC comes the top rake circuit in the design driven circuit, though the circuits built structure is simple relatively, realize that cost is higher easily, thereby influenced competition capability, be not suitable in the fierce relatively household appliances of price competition, applying.

The utility model content

The utility model adopts special integrated chip to carry out the high problem of hardware cost that circuit design caused in order to solve existing top rake circuit, a kind of top rake circuit of new structure is provided, by adopting simple discrete component to carry out circuit design, thereby avoided the use of special integrated chip, reduced the hardware cost of product to a great extent.

In order to solve the problems of the technologies described above, the utility model is achieved by the following technical solutions:

A kind of top rake circuit, comprise that an on off state is controlled by first on-off circuit that signal is closed in sequential control, the switch ways of described first on-off circuit is connected between dc supply input and the top rake voltage output end, also is connected with one and opens the mu balanced circuit that the level state of signal select to insert according to sequential control on described top rake voltage output end.

Further, be in series with divider resistance in the line between described first on-off circuit and top rake voltage output end.

Further again, in described mu balanced circuit, include a stabilivolt, the negative electrode of described stabilivolt connects the top rake voltage output end, and anode is by the switch ways ground connection of second switch circuit, and the control end of described second switch circuit receives sequential control and opens signal.

Wherein, the breakdown reverse voltage of described stabilivolt equals to be connected the desired driving voltage of late-class circuit of described top rake voltage output end.

For the size of current that flows through stabilivolt is limited, between the negative electrode of described stabilivolt and top rake voltage output end, be in series with current-limiting resistance.

Preferably, described second switch circuit adopts a N-channel MOS FET field effect transistor to carry out circuit design, and the drain electrode of described field effect transistor connects the anode of stabilivolt, and source ground, grid receive described sequential control and open signal.

In order to realize break-make control to first on-off circuit, the control end of described first on-off circuit is connected described dc supply input on the one hand, by the switch ways ground connection of the 3rd on-off circuit, the control end of described the 3rd on-off circuit receives sequential control and closes signal on the other hand.

Further again, in described first on-off circuit, include a P channel mosfet field effect transistor, the grid of described P channel mosfet field effect transistor connects described dc supply input by first divider resistance on the one hand, the switch ways that connects described the 3rd on-off circuit on the other hand by second divider resistance, and the switch ways ground connection of passing through the 3rd on-off circuit; The source electrode of described P channel mosfet field effect transistor connects described dc supply input, and drain electrode connects the top rake voltage output end.

Further again, in described the 3rd on-off circuit, include a N-channel MOS FET field effect transistor, the drain electrode of described MOSFET field effect transistor connects second divider resistance, and source ground, grid receive described sequential control and close signal.

Based on above-mentioned top rake circuit structure, the utility model provides a kind of liquid crystal display drive circuit that adopts described top rake circuit design again, utilize the sequential control pass signal of time schedule controller output in the LCDs to come the on off state of first on-off circuit in the top rake circuit is controlled, and then when the controlled conducting of first on-off circuit, the transmitting DC that to introduce by dc supply input is to the top rake voltage output end, and then transfer to the line scanning end of liquid crystal display, be the gate end, open liquid crystal molecule to offer the liquid crystal molecule array; For being carried out top rake, handles by the direct supply of introducing, the utility model further utilizes the sequential control of time schedule controller output to open signal and is implemented in selection access mu balanced circuit on the top rake voltage output end, and then makes the final voltage waveform that forms can satisfy the desired cut-in voltage VGH of liquid crystal display waveform.

Compared with prior art, advantage of the present utility model and good effect are: top rake circuit of the present utility model adopts simple discrete component to set up and forms, not only broken away from dependence to special integrated chip, reduced the complete machine cost, and decoration structure features simple design, use the quantity of components and parts few, it is little to take the PCB area, circuit operational reliability height.Be applied to not only can effectively control cost of products in the LCDs design of drive circuit of household appliances such as LCD TV, and provide convenience for the miniaturization Design of equipment.

After reading the detailed description of the utility model embodiment in conjunction with the accompanying drawings, other characteristics of the present utility model and advantage will become clearer.

Description of drawings

Fig. 1 is the typical waveform figure of VGH voltage;

Fig. 2 is the existing schematic diagram that adopts the top rake circuit of special integrated chip design;

Fig. 3 is the typical waveform figure of GVON signal;

Fig. 4 is the typical waveform figure of GVOFF signal;

Fig. 5 is the circuit theory diagrams of a kind of embodiment of the top rake circuit that proposes of the utility model;

Fig. 6 is based on the theory diagram of the liquid crystal display drive circuit of top rake circuit shown in Figure 5.

Embodiment

Below in conjunction with accompanying drawing embodiment of the present utility model is done explanation in further detail.

The utility model is in order to reduce hardware cost, simplify circuit design, adopt discrete component to build the top rake circuit, to obtain the voltage signal of waveform as shown in Figure 1, satisfy the circuit design requirement of some electronic product such as LCDs, specifically comprise chief components such as direct supply, on-off circuit and mu balanced circuit.Wherein, the switching sequence of on-off circuit closes signal by sequential control to be controlled, to determine the sequential by top rake voltage output end outputting drive voltage; Carrying out sequential that top rake handles for the direct supply by on-off circuit output then opens signal by sequential control and controls, by mu balanced circuit being linked into selectively described top rake voltage output end, and then the current potential of direct supply is reduced on the voltage stabilizing current potential of mu balanced circuit, thereby realized the top rake of direct supply is handled, made driving voltage waveform can satisfy the reception requirement of late-class circuit by described top rake voltage output end output.

Be example below with the LCDs, elaborate the concrete establishment structure and the principle of work thereof of described top rake circuit by a specific embodiment.

Embodiment one, and referring to shown in Figure 5, the on-off circuit of present embodiment is that example describes with the power switch pipe.Wherein, first on-off circuit can adopt a P-channel enhancement type MOSFET field effect transistor M1 to carry out circuit design, with the source electrode connection dc supply input J_VGHP of MOSFET field effect transistor M1, to receive the direct supply VGHP about 30V; Drain electrode connects top rake voltage output end J_VGH, the perhaps further divider resistance R6 that connects between drain electrode and top rake voltage output end J_VGH, with the required cut-in voltage VGH of gate end by top rake voltage output end J_VGH output liquid crystal display, i.e. the voltage signal of waveform as shown in Figure 1.

In order to realize that mu balanced circuit is linked on the top rake voltage output end J_VGH selectively, to reach the top rake of direct supply VGHP to be handled, present embodiment adopts the second switch circuit that the access state of mu balanced circuit is controlled, as shown in Figure 5.Described mu balanced circuit is that example describes with stabilivolt D1, and the negative electrode of stabilivolt D1 is connected described top rake voltage output end J_VGH, perhaps connects described top rake voltage output end J_VGH by current-limiting resistance R2; The anode of stabilivolt D1 is by the switch ways ground connection of second switch circuit, and the on off state of described second switch circuit is controlled by the sequential control of time schedule controller output and opens signal GVON.When sequential control is opened signal GVON and is in high level state, make the plus earth of stabilivolt D1 by control second switch circuit turn-on, with the normal access of realization mu balanced circuit, and then under the pressure limiting effect of stabilivolt D1, realize the top rake of direct supply VGHP is handled.The breakdown reverse voltage of described stabilivolt D1 should specifically be selected according to the desired driving voltage amplitude of late-class circuit that is connected top rake voltage output end J_VGH.For present LCDs, can select breakdown reverse voltage is that the stabilivolt D1 of 25V carries out circuit design, drives requirement with the line scanning of satisfying liquid crystal molecule.

In the present embodiment, described second switch circuit can adopt a N channel enhancement MOSFET field effect transistor M3 to carry out circuit design, as shown in Figure 5.The grid of described N channel field-effect pipe M3 is connected time schedule controller, and signal GVON is opened in the sequential control that receives time schedule controller output, and connects direct supply VCC3 by resistance R 5.The source ground of described N channel field-effect pipe M3, drain electrode connects the anode of described stabilivolt D1.When sequential control is opened signal GVON and is in high level state, direct supply VCC3 draws on being undertaken by the grid potential of 5 pairs of N channel field-effects of resistance R pipe M3, with control N channel field-effect pipe M3 saturation conduction, make the plus earth of stabilivolt D1, the direct supply VGHP that is transferred to top rake voltage output end J_VGH is carried out top rake handle.And when sequential control is opened signal GVON and is in low level state,, thereby make the connecting path of stabilivolt D1 disconnect because N channel field-effect pipe M3 ends, the direct supply VGHP by MOSFET field effect transistor M1 output is not handled.

In addition, in order to realize, also further be connected with the 3rd on-off circuit at the grid of described MOSFET field effect transistor M1 to the control of the switch of MOSFET field effect transistor M1.Described the 3rd on-off circuit can adopt a N channel enhancement MOSFET field effect transistor M2 to carry out circuit design equally, as shown in Figure 5.With the time schedule controller in the grid connection liquid crystal display of field effect transistor M2, signal GVOFF is closed in the sequential control that receives time schedule controller output, the source ground of field effect transistor M2, drain electrode connects dc supply input J_VGHP by the potential-divider network of being made up of divider resistance R1, R3, and the dividing potential drop node of described potential-divider network connects the grid of MOSFET field effect transistor M1.Certainly, the drain electrode of described field effect transistor M2 can directly not be connected with dc supply input J_VGHP with the grid of MOSFET field effect transistor M1 by potential-divider network yet, can play the switch control action to MOSFET field effect transistor M1 equally.

Its principle of work is: when the sequential control pass of time schedule controller output signal GVOFF is in high level state, the controlled conducting of field effect transistor M2, the direct supply VGHP that introduces by dc supply input J_VGHP this moment is input to the source electrode of MOSFET field effect transistor M1 on the one hand, carries out acting on after the voltage division processing grid of MOSFET field effect transistor M1 on the other hand by potential-divider network.Controlled conducting transfers to top rake voltage output end J_VGH with direct supply VGHP by divider resistance R6 to the MOSFET field effect transistor M1 of this moment greater than its grid voltage owing to its source voltage, promptly exports the straight high level part of waveform as shown in Figure 1.After this, sequential control is opened signal GVON and is entered high level state, and the control mu balanced circuit inserts, and then realizes the top rake of direct supply VGHP is handled by mu balanced circuit, promptly forms the top rake part of waveform as shown in Figure 1.And when sequential control pass signal GVOFF is in low level state, field effect transistor M2 ends, this moment, MOSFET field effect transistor M1 ended owing to its source voltage equals its grid voltage, thereby make that the current potential of top rake voltage output end J_VGH is zero, promptly form the low level part of waveform as shown in Figure 1.

This shows that the top rake circuit by present embodiment can generate voltage waveform as shown in Figure 1 well.In the design of liquid crystal display driving circuit, can provide its required cut-in voltage VGH with described top rake circuit application for the liquid crystal molecule array of LCDs.Its concrete establishment structure as shown in Figure 6, the sequential control that is about to top rake circuit shown in Figure 5 is opened signal end and sequential control and is closed signal end and be connected with time schedule controller in the liquid crystal display respectively, and signal GVON is opened in the sequential control that receives time schedule controller output respectively and signal GVOFF is closed in sequential control; Then, the dc supply input J_VGHP of described top rake circuit is connected to the power management chip of liquid crystal display, receive power management chip output+the 30V direct supply; The top rake voltage output end J_VGH of described top rake circuit is connected to the line scanning end of liquid crystal display, it is the gate end, can constitute the road driving circuit branch that is used to generate VGH voltage in the liquid crystal display driving circuit, and then provide the cut-in voltage that to open liquid crystal molecule VGH for the liquid crystal molecule array of liquid crystal display.Because the design of drive circuit that is used to generate required other driving power of liquid crystal display has nothing to do with the top rake circuit design of present embodiment (such as the design of drive circuit that is used to generate the Source power supply etc.), therefore, present embodiment is not described in detail at this design of drive circuit that produces other driving power.

Certainly, first, second, third above-mentioned on-off circuit also can adopt other the simple components and parts with on-off action except that the MOSFET field effect transistor to carry out circuit design, such as triode, controllable silicon, relay etc., present embodiment is not limited in above giving an example.

Top rake circuit structure of the present utility model is simple, uses component number less, and the reliability height, with low cost, not only be fit to be applied in the design of drive circuit of LCDs, and need receive the electronic circuit of the voltage signal of similar waveform shown in Figure 1, same being suitable for for other.

Certainly; above-mentioned explanation is not to be to restriction of the present utility model; the utility model also is not limited in above-mentioned giving an example, and variation, remodeling, interpolation or replacement that those skilled in the art are made in essential scope of the present utility model also should belong to protection domain of the present utility model.

Claims (10)

1. top rake circuit, it is characterized in that: comprise that an on off state is controlled by first on-off circuit that signal is closed in sequential control, the switch ways of described first on-off circuit is connected between dc supply input and the top rake voltage output end, also is connected with one and opens the mu balanced circuit that the level state of signal select to insert according to sequential control on described top rake voltage output end.

2. top rake circuit according to claim 1 is characterized in that: be in series with divider resistance in the line between described first on-off circuit and top rake voltage output end.

3. top rake circuit according to claim 2, it is characterized in that: in described mu balanced circuit, include a stabilivolt, the negative electrode of described stabilivolt connects the top rake voltage output end, anode is by the switch ways ground connection of second switch circuit, and the control end of described second switch circuit receives sequential control and opens signal.

4. top rake circuit according to claim 3 is characterized in that: be in series with current-limiting resistance between the negative electrode of described stabilivolt and top rake voltage output end.

5. top rake circuit according to claim 3 is characterized in that: the breakdown reverse voltage of described stabilivolt equals to be connected the desired driving voltage of late-class circuit of described top rake voltage output end.

6. top rake circuit according to claim 3, it is characterized in that: in described second switch circuit, include a N-channel MOS FET field effect transistor, the drain electrode of described field effect transistor connects the anode of stabilivolt, and source ground, grid receive described sequential control and open signal.

7. according to each described top rake circuit in the claim 1 to 6, it is characterized in that: the control end of described first on-off circuit connects described dc supply input on the one hand, by the switch ways ground connection of the 3rd on-off circuit, the control end of described the 3rd on-off circuit receives sequential control and closes signal on the other hand.

8. top rake circuit according to claim 7, it is characterized in that: in described first on-off circuit, include a P channel mosfet field effect transistor, the grid of described P channel mosfet field effect transistor connects described dc supply input by first divider resistance on the one hand, the switch ways that connects described the 3rd on-off circuit on the other hand by second divider resistance, and the switch ways ground connection of passing through the 3rd on-off circuit; The source electrode of described P channel mosfet field effect transistor connects described dc supply input, and drain electrode connects the top rake voltage output end.

9. top rake circuit according to claim 8, it is characterized in that: in described the 3rd on-off circuit, include a N-channel MOS FET field effect transistor, the drain electrode of described MOSFET field effect transistor connects second divider resistance, and source ground, grid receive described sequential control and close signal.

10. liquid crystal display drive circuit, it is characterized in that: comprise as the described top rake circuit of each claim in the claim 1 to 9, described top rake circuit connects the time schedule controller in the liquid crystal display, signal and sequential control pass signal are opened in the sequential control that receives time schedule controller output, and the top rake voltage output end of described top rake circuit connects the line scanning end of liquid crystal display.

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