





技术领域technical field
本发明涉及一种建立数学模型的方法,特别涉及一种建立互连树电路的时域状态空间数学模型的方法。The invention relates to a method for establishing a mathematical model, in particular to a method for establishing a time-domain state-space mathematical model of an interconnection tree circuit.
背景技术Background technique
随着0.18微米集成电路工艺技术的出现,来自互连负载的延时明显增加。对于采用90纳米技术实现的标准单元ASIC(专用集成电路)来说,电路单元与互连的延时比例已经接近2∶8。也就是说,随着超大规模集成电路技术的发展,互连线(interconnect)的时延已经成为决定电路速度的重要因素。传统的以器件为核心的设计方法已向以互连线为核心的时序驱动(Timing Driven)的设计方法转变。With the advent of 0.18-micron IC process technology, the delay from interconnect loading has increased significantly. For standard cell ASICs (Application Specific Integrated Circuits) implemented in 90nm technology, the delay ratio between circuit cells and interconnects is close to 2:8. That is to say, with the development of VLSI technology, the time delay of interconnect lines (interconnect) has become an important factor in determining the speed of circuits. The traditional device-centric design method has been transformed into a timing-driven (Timing Driven) design method with interconnect lines as the core.
高速集成电路设计要求前端综合与下游的布局布线工具之间进行多次设计反复,以获得时序收敛。布局中间结果的质量评价以及布局结果的调整都要求在布局阶段及时地对时延做出评估。如果时序估计与实际的布局布线后延迟情况出入比较大而存在时序冲突的话,从前端到后端的设计反复次数将大大增加,使获得时序收敛所需的工作量将大大地增加。High-speed IC design requires multiple design iterations between front-end synthesis and downstream place-and-route tools to achieve timing closure. Both the quality evaluation of the layout intermediate results and the adjustment of the layout results require timely evaluation of the delay during the layout phase. If there is a large discrepancy between the timing estimation and the actual post-placement and routing delay and there is a timing conflict, the number of design iterations from the front end to the back end will greatly increase, and the workload required to obtain timing convergence will greatly increase.
随着芯片工作频率的提高和集成规模的增大,对时延估算的精度及速度不断提出新的要求。片上系统(SoC)的出现对模型的延时估算精度和速度提出了更高的要求。With the improvement of chip operating frequency and the increase of integration scale, new requirements are constantly put forward for the accuracy and speed of delay estimation. The appearance of System on Chip (SoC) puts forward higher requirements on the precision and speed of delay estimation of the model.
因此,建立能满足高速电路设计需要的快速而又精确的互连线时延方法是目前超大规模的高速集成电路(0.18微米以下工艺)设计中亟待解决的一个问题。它对于的时延验证、门级模拟以及性能驱动的版图设计具有重要的理论意义和实践意义。Therefore, establishing a fast and accurate interconnect delay method that can meet the needs of high-speed circuit design is an urgent problem to be solved in the design of ultra-large-scale high-speed integrated circuits (processes below 0.18 microns). It has important theoretical and practical significance for delay verification, gate-level simulation and performance-driven layout design.
时延评估方法的关键是设法建立互连线的各种时延模型。从电路的角度看,有仅考虑互连线本身的电阻R和对地的电容C的RC模型;有考虑互连线电感L的RLC模型;但是与实际的高速电路最接近的应该是再考虑对地电导G的RLCG模型。The key to the time delay evaluation method is to try to establish various time delay models of interconnection lines. From the perspective of the circuit, there is an RC model that only considers the resistance R of the interconnection itself and the capacitance C to the ground; there is an RLC model that considers the inductance L of the interconnection; but the closest to the actual high-speed circuit should be reconsidered RLCG model of ground conductance G.
在先技术中,发明人徐勤卫,李征帆和陈文,提供一种用于模拟高速互连线瞬态响应的高效数值方法《电子学报,1999,27(11):114-116》。它采用分布参数,通过偏微分方程求得瞬态响应的解析解或数值解。用这种方法处理单根的互连线尚可,但处理互连线的大规模的树型结构存在一定的难度。In the prior art, inventors Xu Qinwei, Li Zhengfan and Chen Wen provided an efficient numerical method for simulating the transient response of high-speed interconnect lines "Acta Electronics, 1999, 27(11): 114-116". It uses distributed parameters to obtain the analytical or numerical solution of the transient response through partial differential equations. It is acceptable to use this method to deal with a single interconnection line, but it is difficult to deal with a large-scale tree structure of interconnection lines.
互连线模型也可采用集总参数。集总参数模型的阶数趋于无穷时可逼近分布参数模型。但此时模型的规模必定十分庞大。当模型的每一项元素表达比较复杂(如含双曲函数)的话,这种高阶模型的计算将十分耗时。此外,计算的复杂度又跟互连线树型结构的分叉级数有关,一般对于分叉采用叠代算法,其计算过程更无法忍受。为了节省大规模树结构的运算时间,人们提出了不少模型简化(model reduction)的方法,用低阶的模型来近似原始的高阶模型。低阶模型虽然快速,但是存在着较大误差、误差不容易控制以及不稳定等一系列问题。The interconnect model can also use lumped parameters. When the order of the lumped parameter model tends to infinity, it can approach the distributed parameter model. But the scale of the model must be very large at this time. When the expression of each element of the model is relatively complex (such as including hyperbolic functions), the calculation of this high-order model will be very time-consuming. In addition, the computational complexity is related to the bifurcation series of the interconnection tree structure. Generally, the iterative algorithm is used for the bifurcation, and the calculation process is even more unbearable. In order to save the calculation time of large-scale tree structures, many model reduction methods have been proposed, using low-order models to approximate the original high-order models. Although the low-order model is fast, there are a series of problems such as large errors, difficult to control errors, and instability.
在先技术中,研究时延特性的互连线集总参数模型主要是沿着Elmore时延,如W.C,Elmore,提供的The Transient Response of Damped Linear Network withParticular Regard to Wideband Amplifiers(关于宽带放大器阻尼线性网络的瞬态响应)《Journal of Applied Physics,19(1):55-63,1948》,矩匹配(moment matching)如Ismail,Y.I.,E.G.Friedman and J.L.Neves.提供的Equivalent Elmore delay for RLCtrees(RLC树的等效Elmore时延)《IEEE Trans,2000,CAD 19(1):83-97》,这一思路发展,模型大多是从频域传输函数来着手建立的。从频域再转换到时域进行时延估算不可避免将影响估算的速度和精度。In the prior art, the interconnection lumped parameter model for researching delay characteristics is mainly along the Elmore time delay, such as W.C, Elmore, The Transient Response of Damped Linear Network with Particular Regard to Wideband Amplifiers (on broadband amplifier damping linear Network transient response) "Journal of Applied Physics, 19(1): 55-63, 1948", moment matching (moment matching) such as Equivalent Elmore delay for RLCtrees (RLC provided by Ismail, Y.I., E.G.Friedman and J.L.Neves. The equivalent Elmore delay of the tree) "IEEE Trans, 2000, CAD 19(1): 83-97", the development of this idea, most of the models are established from the frequency domain transfer function. Transforming from the frequency domain to the time domain for delay estimation will inevitably affect the speed and accuracy of the estimation.
发明内容Contents of the invention
本发明的目的是为了克服上述在先技术中所存在的问题,提供一种建立时域状态空间的高阶电阻、电感、电容、电导互连树模型的方法,The purpose of the present invention is in order to overcome the problems existing in the above-mentioned prior art, and a kind of method of establishing the high-order resistance, inductance, capacitance, conductance interconnection tree model of time-domain state space is provided,
为了实现上述目的,本发明采用的技术方案是:一种建立互连树电路的时域状态空间数学模型的方法,其特征在于建立一种包括电阻、电感、电容、电导互连树电路的时域状态空间数学模型,建立的方法步骤是:In order to achieve the above object, the technical solution adopted by the present invention is: a method for establishing a time-domain state-space mathematical model of an interconnection tree circuit, which is characterized in that a time-domain state-space mathematical model including resistance, inductance, capacitance, and conductance interconnection tree circuit is established. The domain state space mathematical model, the method steps of establishment are:
(a)首先,建立互连树的电路模型,按照实际版图互连树的主干和分支路的拓扑结构建立互连线树的π型包括电阻、电感、电容、电导的电路模型;(a) First, establish a circuit model of the interconnection tree, and establish a π-type circuit model of the interconnection tree including resistance, inductance, capacitance, and conductance according to the topology of the trunk and branch roads of the actual layout interconnection tree;
(b)确定电路模型中主干和各分支路的级联数:确定上述步骤(a)中所建立的电路模型主干与各支路的级联数;(b) determine the number of cascades of the trunk and each branch in the circuit model: determine the number of cascades between the trunk and each branch of the circuit model established in the above step (a);
(c)建立时域状态空间数学模型:根据克希霍夫(Kirchhoff)电压定律和克希霍夫电流定律基于上述(a)(b)步骤的结果建立时域状态空间数学模型为:(c) Establish a time-domain state-space mathematical model: according to Kirchhoff’s voltage law and Kirchhoff’s current law, the time-domain state-space mathematical model based on the results of the above (a) and (b) steps is:
y(t)=Cx(t)+Du(t)y(t)=Cx(t)+Du(t)
其中:A为包含电阻R、电感L、电容C、电导G的矩阵,B为包含电感L的矩阵,C为0和1组成的矩阵,D为零;Among them: A is a matrix including resistance R, inductance L, capacitance C, and conductance G, B is a matrix including inductance L, C is a matrix composed of 0 and 1, and D is zero;
x为2m维的向量,各维的值为主干电路和各分叉支路各级联的电流I和级联节点电压V交替,其中m为主干和各支路电路的级联数的和;x is a 2m-dimensional vector, and the value of each dimension is the alternating current I and cascade node voltage V of each cascade of the main circuit and each branch circuit, where m is the sum of the cascaded numbers of the main circuit and each branch circuit;
为x(t)向量各维对时间t求导;Derivative for each dimension of the x(t) vector with respect to time t;
u(t)为输入电压;u(t) is the input voltage;
y(t)为输出电压。y(t) is the output voltage.
本发明与现有技术比较,有诸多的优点:Compared with the prior art, the present invention has many advantages:
(1)本发明的模型A矩阵基本上只有对角线三行元素,形式简洁,又在时域表达,因而估计信号时延在时域中运算不必转换,速度较快,在MATLAB进行阶跃响应的仿真,瞬间即可完成;(1) The model A matrix of the present invention basically only has three rows of diagonal elements, which is concise in form and expressed in the time domain, so the estimated signal time delay does not need to be converted in the time domain operation, and the speed is faster, and the step is carried out in MATLAB The simulation of the response can be completed in an instant;
(2)本发明在电路模型中引进了电导G,使模型更贴近实际;(2) The present invention introduces conductance G in the circuit model, making the model closer to reality;
(3)矩阵大小仅与支路个数的1次方成正比,对于一般的复杂互连线电路可直接使用高阶模型,因而结果比较精确;(3) The size of the matrix is only proportional to the first power of the number of branches, and the high-order model can be used directly for general complex interconnection circuits, so the results are more accurate;
(4)本发明相比单根互连线的结果,给出了复杂互连线树的一般结果,更为通用,实用性更强。(4) Compared with the result of a single interconnection line, the present invention provides a general result of a complex interconnection line tree, which is more general and more practical.
附图说明Description of drawings
图1是不带信号源和负载的单根互连线的RLCG电路模型;Figure 1 is the RLCG circuit model of a single interconnect without signal source and load;
图2是带信号源的单根互连线的RLCG电路模型;Fig. 2 is an RLCG circuit model of a single interconnection line with a signal source;
图3是带负载的单根互连线的RLCG电路模型;Fig. 3 is the RLCG circuit model of a single interconnection line with a load;
图4是2级2分叉互连线树的RLCG电路模型;Fig. 4 is the RLCG circuit model of the 2-level 2-fork interconnection tree;
图5是4级多分叉互连线树RLCG电路模型;Fig. 5 is a 4-level multi-fork interconnection tree RLCG circuit model;
图6是4级多分叉互连线树的RLCG电路模型的状态方程的系数A矩阵结构;Fig. 6 is the coefficient A matrix structure of the state equation of the RLCG circuit model of the 4-level multi-fork interconnection tree;
图7是任意分叉互连线树的RLCG电路模型;Fig. 7 is the RLCG circuit model of arbitrary forked interconnection tree;
图8是一个用于实际运算的实施例的芯片版图;Fig. 8 is a chip layout of an embodiment for actual operation;
图9是建立图8中实施例的π型RLCG的电路模型。FIG. 9 is a circuit model for establishing the π-type RLCG of the embodiment in FIG. 8 .
R为电阻、L为电感、C为电容、G为电导R is resistance, L is inductance, C is capacitance, G is conductance
具体实施方式Detailed ways
以下结合附图,进一步说明本发明的特点。Below in conjunction with accompanying drawing, further illustrate the feature of the present invention.
图1是不带信号源和负载的单根互连线的RLCG电路模型,电路由π型电阻R、电感L、电容C和电导G组成,R和L为互连线本身的电阻和电感,C和G为互连线对地的电容和电导。每一级电阻与电感串联;电容与电导并联。本级的电感与后级的电阻的连接处和本级的电容电导的一端相交组成节点。整个电路的节点自左到右分别为节点1、节点2……直到节点n-1、节点n。Figure 1 is the RLCG circuit model of a single interconnection line without signal source and load. The circuit is composed of π-type resistance R, inductance L, capacitance C and conductance G. R and L are the resistance and inductance of the interconnection line itself. C and G are the capacitance and conductance of the interconnection line to ground. Each stage of resistance is connected in series with inductor; capacitor is connected in parallel with conductance. The junction of the inductance of this stage and the resistance of the subsequent stage intersects with one end of the capacitance and conductance of this stage to form a node. The nodes of the whole circuit are respectively
根据图1所构成的不带信号源和负载的单根互连线的RLCG电路模型,求得该电路模型的级联数。According to the RLCG circuit model of a single interconnection line without signal source and load constituted in Figure 1, the cascade number of the circuit model is obtained.
不带信号源和负载的单根互连线的时域状态空间的数学模型推导如下:The mathematical model of the time-domain state space of a single interconnect without signal sources and loads is derived as follows:
对于图1电路各节点,根据克希霍夫(Kirchhoff)电压定律和克希霍夫电流定律有:For each node of the circuit in Figure 1, according to Kirchhoff’s voltage law and Kirchhoff’s current law:
整理后得:After tidying up:
表达为状态空间模型Expressed as a state-space model
y(t)=Cx(t)+Du(t)y(t)=Cx(t)+Du(t)
式中In the formula
x=[I1 V1 I2 V2 … In-1 Vn-1 In Vn]T,x∈R2nx=[I1 V1 I2 V2 ... In-1 Vn-1 In Vn ]T ,x∈R2n
y=Vout=Vn,y∈Ry = Vout = Vn , y∈R
u=Vin,u∈Ru=Vin , u∈R
{A,B,C,D}分别为{A, B, C, D} are respectively
C1×2n=[0 0 0 0 … 0 0 0 1]C1×2n = [0 0 0 0 ... 0 0 0 1]
D=0,D = 0,
{ABCD}系数矩阵特征:{ABCD} coefficient matrix features:
A矩阵 矩阵大小为2n×2n,n为电路模型的级联数。除了在矩阵的左上至右下对称的3条对角斜线外,其余元素均为0。右上一条对角斜线由a12、a23……a(2n-2),(2n-1)和a(2n-1),2n等2n-1个元素组成,它们的值分别为和交替,即
B矩阵 矩阵大小为2n×1,n为电路模型的级联数。除了第1行为外,其余均为0。B matrix The size of the matrix is 2n×1, and n is the cascade number of the circuit model. except
C矩阵 矩阵大小为1×2n,n为电路模型的级联数。除了最后一列为1外,其余均为0。C matrix The size of the matrix is 1×2n, and n is the cascade number of the circuit model. All are 0 except the last column which is 1.
D矩阵 D=0D matrix D=0
图2是带信号源的单根互连线的RLCG电路模型,信号源电压Vs,信号源内阻Rs。Figure 2 is the RLCG circuit model of a single interconnection line with a signal source, the signal source voltage Vs, and the signal source internal resistance Rs.
根据图2所构成的带信号源的单根互连线的RLCG电路模型,求得该电路模型的级联数。According to the RLCG circuit model of a single interconnection line with a signal source constituted in Figure 2, the cascade number of the circuit model is obtained.
带信号源的单根互连线的RLCG电路模型的时域状态空间模型除了A矩阵中由于信号源电阻Rs与第一级联中的电阻R为串联关系,
图3是带负载的单根互连线的RLCG电路模型,带有负载电容CL,负载电阻RL。Fig. 3 is the RLCG circuit model of a single interconnection line with a load, with a load capacitanceCL and a load resistanceRL .
根据图3所构成的带负载的单根互连线的RLCG电路模型,求得该电路模型的级联数。According to the RLCG circuit model of a single interconnection line with load constituted in Figure 3, the cascade number of the circuit model is obtained.
带负载的单根互连线的时域状态空间模型除了A矩阵中由于负载电阻RL与最后一级联中的电导G为并联关系以及负载电容CL与最后一级联中的电容C为并联关系,使得
图4是2级2分叉互连线树的RLCG电路模型,2级2分叉电路即在第0级主干电路后有作为第1级的2个分叉的支路。Fig. 4 is an RLCG circuit model of a 2-level 2-fork interconnection tree. The 2-level 2-fork circuit has two forked branches as the first level after the 0-level main circuit.
主干电路模型与带信号源的单根互连线电路模型相同,信号源Vs,信号源内阻为Rs;分叉电路模型与带负载的单根互连线电路模型相同,负载电容、电阻分别为CL1、CL2和RL1、RL2。。输出端设于最下面的一个分叉,即第2个分叉支路末端。The main circuit model is the same as the circuit model of a single interconnection line with a signal source, the signal source is Vs, and the internal resistance of the signal source is Rs; the bifurcation circuit model is the same as the circuit model of a single interconnection line with a load, and the load capacitance and resistance are respectively CL1 , CL2 and RL1 , RL2 . . The output end is set at the bottom fork, that is, the end of the second fork branch.
主干与分叉支路都是由n级联的π型RLCG电路构成。主干电路每一级电阻、电感、电容和电导分别为R0、L0、C0和G0;第1分叉支路电路每一级电阻、电感、电容和电导分别为R1、L1、C1和G1;第2分叉支路电路每一级电阻、电感、电容和电导分别为R2、L2、C2和G2。Both the trunk and the bifurcated branches are composed of n cascaded π-type RLCG circuits. The resistance, inductance, capacitance and conductance of each stage of the main circuit are R0 , L0 , C0 and G0 respectively; the resistance, inductance, capacitance and conductance of each stage of the first bifurcated branch circuit are R1 , L1 , C1 and G1 ; the resistance, inductance, capacitance and conductance of each stage of the second branch circuit are R2 , L2 , C2 and G2 .
电路各节点命名如下。主干电路节点为节点1、节点2……直到节点n-1、节点n,第1个分叉支路节点为节点11、12……直到节点1(n1-1)、1n1,第2个分叉支路节点为节点21、22……直到节点2(n2-1)、2n2。The nodes of the circuit are named as follows. The main circuit nodes are
根据图4所构成的2级2分叉互连线树的RLCG电路模型,求得该电路模型的级联数。According to the RLCG circuit model of the 2-level 2-fork interconnection tree formed in Fig. 4, the cascade number of the circuit model is obtained.
2级2分叉电路时域状态空间的数学模型推导如下:The mathematical model of the time-domain state space of the 2-level 2-fork circuit is derived as follows:
对于电路各节点,根据克希霍夫(Kirchhoff)电压定律和克希霍夫电流定律有:For each node of the circuit, according to Kirchhoff’s voltage law and Kirchhoff’s current law:
整理后得after finishing
表达为状态空间方程Expressed as a state-space equation
y(t)=Cx(t)+Du(t)y(t)=Cx(t)+Du(t)
式中In the formula
u=Vs,u∈Ru=Vs, u∈R
C1×2m=[0 0 0 0 … 0 0 0 1]C1×2m = [0 0 0 0 ... 0 0 0 1]
D=0D=0
各变量下标中m=n+1n1+2n2,n、1n1、2n2分别为主干和两个分叉支路电路模型的级联数。In the subscripts of each variable, m=n+1n1 +2n2 , where n, 1n1 and 2n2 are the cascading numbers of the trunk and two bifurcated branch circuit models respectively.
状态变量特征:State variable characteristics:
A矩阵A matrix
A矩阵大小为2m×2m,m=n+1n1+2n2,n、1n1、2n2分别为主干和两个分叉支路电路模型的级联数。对于每一支路(包括主干),一般可使用相同级联数的电路模型,即n=1n1=2n2,则有m=kn,k为支路(包括主干)数,对于本2级2分叉电路,k=3,则A矩阵大小为6n×6n。The size of the matrix A is 2m×2m, m=n+1n1 +2n2 , where n, 1n1 and 2n2 are the cascading numbers of the main circuit model and the two branch circuit models respectively. For each branch (including the trunk), a circuit model with the same number of cascades can generally be used, that is, n=1n1 =2n2 , then m=kn, where k is the number of branches (including the trunk), for this
主干和分叉支路各组成一个2n×2n的子矩阵。由于主干电路起始端增加了信号源Vs,信号源内阻为Rs,因此主干子矩阵的形式同带信号源的单根互连线模型;由于两个分叉支路末端分别增加了负载电阻RL1和RL2以及负载电容CL1和CL2,因此两个分叉支路子矩阵的形式同带负载的单根互连线模型。上述主干和分叉支路组成的子矩阵对角排列组成对角子矩阵。次序依次为主干子矩阵、第1分叉支路子矩阵和第2分叉支路子矩阵。除了对角子矩阵外还有下列非0元素:在主干子矩阵的最后一行和两个分叉支路子矩阵的第1列的交叉处有和即元素
B矩阵B matrix
B矩阵大小为2m×1,m=n+1n1+2n2,n、1n1、2n2分别为主干和两个分叉支路电路模型的级联数。当n=1n1=2n2时,B矩阵大小为6n×1。除了第1行为以外,其余均为0。The size of the B matrix is 2m×1, m=n+1n1 +2n2 , and n, 1n1 , 2n2 are respectively the cascading numbers of the main circuit model and the two bifurcated branch circuits. When n=1n1 =2n2 , the size of the B matrix is 6n×1. except
C矩阵C matrix
C矩阵大小为1×2m,m意义同上。当n=1n1=2n2时,C矩阵大小为1×6n。除了最后一列(即第6n列)为1以外,其余均为0。The size of the C matrix is 1×2m, and the meaning of m is the same as above. When n=1n1 =2n2 , the size of the C matrix is 1×6n. Except for the last column (i.e. the 6nth column) which is 1, the rest are 0.
D矩阵D matrix
D=0。D=0.
图5是一个4级多分叉的互连线RLCG电路模型,图中负载阻抗ZL为负载电阻RL与负载电容CL并联。4级多分叉的互连线电路模型是一个特殊的任意分叉互连线电路模型。一般的任意分叉互连线电路模型可仿照该特殊的任意分叉互连线电路模型得到。Fig. 5 is a 4-level multi-forked interconnection line RLCG circuit model, in which the load impedance ZL is the parallel connection of the load resistanceRL and the load capacitanceCL . The 4-level multi-fork interconnect circuit model is a special arbitrary fork interconnect circuit model. The general circuit model of any bifurcated interconnection line can be obtained by imitating the special circuit model of any bifurcated interconnection line.
电路的主干和每一分叉支路使用n级联的单根互连线电路模型,主干和每一分叉支路的n可以相同,也可以不同。主干l,后有3个第1级子分叉,分别为l1、l2和l3。l1后有2个第2级子分叉:l11和l12。l2后也有2个第2级子分叉:l21和l22。l21后有3个第3级子分叉:l211、l212和l213。L22后没有再分叉。l3后没有分叉。包括主干共有11个支路。The backbone of the circuit and each bifurcation branch use a single interconnection line circuit model in which n is cascaded, and the n of the trunk and each bifurcation branch can be the same or different. After the main trunk l, there are three first-level sub-branches, namely l1 , l2 and l3 . After l1, there are two second-level sub-forks: l11 and l12 . After l2, there are also two second-level child forks: l21 and l22 . After l21, there are three sub-forks of the third level: l211 , l212 and l213 . No further forks after L22 . l There is no fork after3 . There are 11 branches including the trunk.
同2级2分叉电路,在主干电路的起始端接信号源Vs,信号源内阻为Rs;在每条分叉支路的末端分别接负载阻抗。输出端设于最下方一个分叉支路,即l3的末端。The same as the 2-level 2-fork circuit, the signal source Vs is connected at the beginning of the main circuit, and the internal resistance of the signal source is Rs; the load impedance is respectively connected at the end of each fork branch. The output end is located at the bottom of a bifurcated branch, that is, the end ofl3 .
根据图5所构成的4级多分叉的互连线RLCG电路模型,分别求得该电路模型的主干电路的级联数和分支电路的级联数。According to the 4-level multi-fork interconnection line RLCG circuit model constituted in Fig. 5, the cascading number of the main circuit and the cascading number of the branch circuits of the circuit model are obtained respectively.
仿2级2分叉电路求取时域状态空间的数学模型的方法可以求得本4级多分叉的互连线电路的时域状态空间的数学模型,形式与2级2分叉电路的时域状态空间的数学模型一致,区别在于A、B、C、D四个系数矩阵的形式:The method of imitating the mathematical model of the time-domain state space of the 2-level 2-fork circuit can obtain the mathematical model of the time-domain state space of the 4-level multi-fork interconnection circuit, and the form is the same as that of the 2-level 2-fork circuit The mathematical models of the time-domain state space are consistent, the difference lies in the form of the four coefficient matrices of A, B, C, and D:
A矩阵构成:主干和每一分叉支路各组成大小为2n×2n的子矩阵,n为各主干电路或每一分叉电路的级联数,各子矩阵的级联数n可以不等。子矩阵对角排列构成对角子矩阵,次序为l、l1、l11、l12、l2、l21、l211、l212、l213、l22和l3。A matrix composition: the backbone and each bifurcation branch form a sub-matrix with a size of 2n×2n, n is the cascading number of each main circuit or each bifurcation circuit, and the cascading number n of each sub-matrix can be different . The sub-matrixes are arranged diagonally to form a diagonal sub-matrix, and the order is l, l1 , l11 , l12 , l2 , l21 , l211 , l212 , l213 , l22 and l3 .
主干l的子矩阵采用带信号源的单根互连线模型的A矩阵,中间分叉支路l1、l2、l21的子矩阵采用不带信号源和负载的单根互连线模型的A矩阵,末端分叉支路l11、l12、l211、l212、l213、l22和l3的子矩阵采用带负载的单根互连线模型的A矩阵。The sub-matrix of the backbone l adopts the A matrix of a single interconnection model with a signal source, and the sub-matrixes of the middle bifurcated branches l1 , l2 , and l21 adopt a single interconnection model without a signal source and load The A matrix of the terminal bifurcation branches l11 , l12 , l211 , l212 , l213 , l22 and l3 sub-matrices adopts the A matrix of the model of a single interconnection line with load.
每一父干的最后一行与子干的第1列的交叉点增加元素k为支路下标;每一子干的第一行与父干的最后一列交叉点增加元素k为支路下标,其结构形式如图6所示。Add elements at the intersection of the last row of each parent stem and the first column of the child stem k is the subscript of the branch; add elements at the intersection of the first row of each child stem and the last column of the parent stem k is the subscript of the branch, and its structure is shown in Figure 6.
本4级多分叉的互连线电路包括主干共有支路数nb=11,取各主干和支路的级联数n相同,A矩阵大小为(2·nb·n)×(2·nb·n)=22n×22n,A矩阵大小与主干和支路数成正比。This 4-level multi-branched interconnection line circuit includes the number of branches nb = 11 in the trunk, and the cascade number n of each trunk and branch is the same, and the size of the A matrix is (2 nb n) × (2 ·nb ·n)=22n×22n, the size of A matrix is proportional to the number of trunks and branches.
B矩阵大小为(2·nb·n)×1=22n×1,
C矩阵大小为1×(2·nb·n)=1×22n。C=[0 0 0 0 … 0 0 0 1]The size of the C matrix is 1×(2·nb ·n)=1×22n. C=[0 0 0 0 ... 0 0 0 1]
D=0D=0
图7是任意分叉互连线RLCG电路模型。Figure 7 is an arbitrary bifurcated interconnect RLCG circuit model.
同4级多分叉电路,在主干电路的起始端接信号源Vs,信号源内阻为Rs;在每条分叉支路的末端分别接负载阻抗。输出端设于最下方一个分叉支路的末端。The same as the 4-level multi-fork circuit, the signal source Vs is connected at the beginning of the main circuit, and the internal resistance of the signal source is Rs; the load impedance is respectively connected at the end of each branch circuit. The output terminal is arranged at the end of the lowermost branch branch.
根据图7所构成的任意分叉互连线RLCG电路模型,分别求得该电路模型的主干电路的级联数和分支电路的级联数。According to the RLCG circuit model of any bifurcated interconnection line constituted in Fig. 7, the cascading numbers of the main circuit and the cascading numbers of the branch circuits of the circuit model are obtained respectively.
任意分叉互连线RLCG电路模型的时域状态空间的数学模型可对于电路各节点,根据克希霍夫(Kirchhoff)电压定律和克希霍夫电流定律得到,其形式和4级多分叉的互连线电路的时域状态空间的数学模型一致,其矩阵构成可依2级2分叉电路和4级多分叉的互连线电路类推为:The mathematical model of the time-domain state space of the RLCG circuit model of any bifurcated interconnection line can be obtained for each node of the circuit according to Kirchhoff's voltage law and Kirchhoff's current law. The mathematical model of the time-domain state space of the interconnection circuit is consistent, and its matrix composition can be analogized according to the 2-level 2-fork circuit and the 4-level multi-fork interconnection circuit:
A矩阵构成:大小为2m行2m列,m为主干和各支路电路的级联数的和;主干和每一分叉支路各组成大小为2n×2n的子矩阵,n为各主干电路或每一分叉电路的级联数,各子矩阵的级联数n可以不等。主干电路的子矩阵采用带信号源的单根互连线RLCG模型的A矩阵,中间分叉支路的子矩阵采用不带信号源和负载的单根互连线RLCG模型的A矩阵,末端分叉支路的子矩阵采用带负载的单根互连线RLCG模型的A矩阵;A矩阵大小为2m×2m,A矩阵大小与主干和支路的数目成正比,各子矩阵按对角线排列组成对角子矩阵,子矩阵排列顺序的原则同4级多分叉电路,即按电路图中从左到右、从上到下,左右先于上下选取分叉支路(包括主干)的原则。每一父干子矩阵的最后一行与子干子矩阵的第1列的交叉点增加元素C为支路k中的电容,k为支路下标;每一子干矩阵的第一行与父干矩阵的最后一列的交叉点增加元素L为支路k中的电感,k为支路下标,其他元素都为0;A matrix composition: the size is 2m rows and 2m columns, m is the sum of the cascading numbers of the trunk and each branch circuit; the trunk and each branch branch form a sub-matrix with a size of 2n×2n, and n is each trunk circuit Or the number of cascades of each branch circuit, the number n of cascades of each sub-matrix may be different. The sub-matrix of the main circuit adopts the A matrix of the RLCG model of a single interconnection line with a signal source, the sub-matrix of the middle bifurcated branch adopts the A matrix of a single interconnection line RLCG model without a signal source and load, and the terminal sub-matrix The sub-matrix of the fork branch adopts the A matrix of the RLCG model of a single interconnection line with load; the size of the A matrix is 2m×2m, and the size of the A matrix is proportional to the number of trunks and branches, and each sub-matrix is arranged diagonally To form a diagonal sub-matrix, the principle of sub-matrix arrangement order is the same as that of the 4-level multi-fork circuit, that is, according to the principle of selecting the fork branch (including the trunk) from left to right and from top to bottom in the circuit diagram, left and right before up and down. Add elements at the intersection of the last row of each parent-stem-sub-matrix and the first column of the child-stem-sub-matrix C is the capacitor in branch k, and k is the subscript of the branch; add elements at the intersection of the first row of each sub-stem matrix and the last column of the parent-stem matrix L is the inductance in the branch k, k is the subscript of the branch, and all other elements are 0;
B矩阵大小为2m×1,
C矩阵大小为1×2m,C[0 0 0 0 … 0 0 0 1];The size of C matrix is 1×2m, C[0 0 0 0 … 0 0 0 1];
D=0。D=0.
对于得到的A矩阵、B矩阵、C矩阵可通过作矩阵的相似变换或作降阶,得到新的矩阵形式。For the obtained A matrix, B matrix, and C matrix, a new matrix form can be obtained by similar transformation or order reduction of the matrix.
图8是一个用于实际运算的实施例的芯片版图,如图8所示:虚线为网格,单位为1μm×1μm。FIG. 8 is a chip layout of an embodiment used for actual operation, as shown in FIG. 8: the dotted line is a grid, and the unit is 1 μm×1 μm.
G0为信号发送端,0-1为主干l,后接一2分叉分支:1-2为分支l1;1-3为分支l2,,l2后又有分叉:3-4为分支l21,l21终端G21;3-5为分支l22,l22终端G22。G0 is the signal sending end, 0-1 is the trunk l, followed by a 2-fork branch: 1-2 is the branch l1 ; 1-3 is the branch l2 , and after l2 there is another fork: 3-4 is Branch l21 , l21 terminal G21 ; 3-5 is branch l22 , l22 terminal G22 .
图9是建立图8中实施例的π型RLCG的电路模型,主干和支路电路模型的级联数n取100。FIG. 9 is a circuit model for establishing the π-type RLCG of the embodiment in FIG. 8, and the cascading number n of the trunk and branch circuit models is 100.
由图8可知,主干和分支的长度分别为l=3μm,l1=2μm,l2=3μm,l21=1μm,l22=4μm。It can be known from FIG. 8 that the lengths of the trunk and branches are l=3 μm, l1 =2 μm, l2 =3 μm, l21 =1 μm, and l22 =4 μm.
信号源内阻RS=500Ω,接收端负载电容CL=0.15Pf,负载电阻RL=∞。Signal source internal resistance RS =500Ω, receiving end load capacitance CL =0.15Pf, load resistance RL =∞.
互连线单位长度的电学参数为:r0=0.067Ω/μm,l0=0.70pH/μm,c0=0.062fF/μm,g0=0。得到:The electrical parameters per unit length of the interconnection line are: r0 =0.067Ω/μm, l0 =0.70pH/μm, c0 =0.062fF/μm, g0 =0. get:
R0=0.00201Ω,L0=0.021pH,C0=0.00186fF,G0=0;R0 =0.00201Ω, L0 =0.021pH, C0 =0.00186fF, G0 =0;
R1=0.00134Ω,L1=0.014pH,C1=0.00124fF,G1=0;R1 =0.00134Ω, L1 =0.014pH, C1 =0.00124fF, G1 =0;
R2=0.00201Ω,L2=0.021pH,C2=0.00186fF,G2=0;R2 =0.00201Ω, L2 =0.021pH, C2 =0.00186fF, G2 =0;
R21=0.00067Ω,L21=0.007pH,C21=0.00062fF,G21=0;R21 =0.00067Ω, L21 =0.007pH, C21 =0.00062fF, G21 =0;
R22=0.00268Ω,L22=0.028pH,C22=0.00248fF,G22=0。R22 =0.00268Ω, L22 =0.028pH, C22 =0.00248fF, G22 =0.
对于电路各节点,根据克希霍夫(Kirchhoff)电压定律和克希霍夫电流定律得到本时域的状态空间模型:For each node of the circuit, according to Kirchhoff's voltage law and Kirchhoff's current law, the state-space model of this time domain is obtained:
y(t)=Cx(t)+Du(t)y(t)=Cx(t)+Du(t)
式中In the formula
x(t)=[I0,1V0,1I0,2V0,2…I0,99 V0,99I0,100V0,100I1,1V1,1I1,2V1,2…I1,99V1,99I1,100V1,100I2,1V2,1I2,2V2,2…I2,99V2,99I2,100V2,100I21,1V21,1I21,2 V21,2…I21,99 V21,99I21,100V21,100I22,1V22,1I22,2V22,2…I22,99V22,99I22,100V22,100]T(Iij、Vij为主干和各分叉支干中各节点对地电容的电流和各节点的电压。i=0、1、2、21、22;j=1、2、…99、100)x(t)=[I0, 1 V0 , 1 I0 , 2 V0 , 2 ... I 0,99 V 0,99 I 0,100 V 0,100 I 1,1 V1 , 1 I1, 2 V1, 2 ... I 1,99
为x(和t)向量对时间t求导。Take the derivative with respect to time t for the x (and t) vectors.
u(t)=VS;y(t)=Voutu(t)=VS ; y(t)=Vout
A矩阵大小为1000×1000,有下列元素组成:A matrix is 1000×1000 in size and consists of the following elements:
a31=0;
……...
a198,1=0;……a198,196=0;
a199,1=0;……a199,197=0;
a200,1=0;……a200,198=0;
a201,1=0;……a201,199=0;
a202,1=0;……a202,200=0;
a203,1=0;……a203,201=0;
……...
a398,1=0;……a398,396=0;
a399,1=0;……a399,397=0;
a400,1=0;……a400,398=0;
a401,1=0;……a401,199=0;
a402,1=0;……a402,400=0;
a403,1=0;……a403,401=0;
……...
a598,1=0;……a598,596=0;
a599,1=0;……a599,597=0;
a600,1=0;……a600,598=0;
a600,802=0;……a600,1000=0a600, 802 = 0; ... a600, 1000 = 0
a601,1=0;……a601,599=0;
a602,1=0;……a602,600=0;
a603,1=0;……a603,601=0;
……...
a798,1=0;……a798,796=0;
a799,1=0;……a799,797=0;
a800,1=0;……a800,798=0;
a801,1=0;……a801,599=0;
a802,1=0;……a802,800=0;
a803,1=0;……a803,801=0;
……...
a998,1=0;……a998,996=0;
a999,1=0;……a999,997=0;
a1000,1=0;……a1000,998=0;
B矩阵大小为1000×1,
C矩阵大小为1×1000,C=[0 0 0 … 0 0 1],除了第1000列元素C1000,1=1外,其余都为0。The size of the C matrix is 1×1000, C=[0 0 0 .
D矩阵为0。D matrix is 0.
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| CNB2006100295234ACN100405380C (en) | 2006-07-28 | 2006-07-28 | Method for building RLCG circuit model |
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| CN106569978A (en)* | 2016-11-09 | 2017-04-19 | 深圳国泰安教育技术股份有限公司 | Method for calculating current flowing through electrical appliance in circuit |
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| CN102915385A (en)* | 2011-08-03 | 2013-02-06 | 复旦大学 | Interconnection line model reduction method based on time-domain trapezoidal method difference |
| CN103226166A (en)* | 2013-03-21 | 2013-07-31 | 天津大学 | Shielded twisted pair RLCG model and computational method of transfer characteristic thereof |
| CN103226166B (en)* | 2013-03-21 | 2015-05-27 | 天津大学 | Computational method of transfer characteristic of shielded twisted pair RLCG |
| CN106569978A (en)* | 2016-11-09 | 2017-04-19 | 深圳国泰安教育技术股份有限公司 | Method for calculating current flowing through electrical appliance in circuit |
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