CN1960242B - Method, device, system for implementing clock synchronization, and distribution system - Google Patents
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- 238000000034methodMethods0.000titleclaimsabstractdescription39
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Abstract
Translated fromChinese
Description
Translated fromChinese技术领域technical field
本发明涉及分布式控制技术，尤其涉及时钟同步技术。The invention relates to distributed control technology, in particular to clock synchronization technology.
背景技术Background technique
在工业自动化、运动控制、电力或电信等分布式系统中，实时时钟的同步技术有着广泛的应用。In distributed systems such as industrial automation, motion control, power or telecommunications, the synchronization technology of real-time clocks has a wide range of applications.
图1为目前的一种时钟同步系统的结构示意图。如图1所示，CPU12将数据包写入MAC(Media Access Control，介质访问控制)Controller(控制器)13的缓存之后，再命令MAC Controller13发送数据包，MAC Controller13接收到命令后，根据网络中的数据流动情况，选择合适的时间将数据包发送给PHY(Physical Layer Device，物理层设备)Transceiver(收发器)14，PHYTransceiver14完成信号转换后，将数据包发送到网络中。FIG. 1 is a schematic structural diagram of a current clock synchronization system. As shown in Figure 1, after CPU12 writes the data packet into the cache of MAC (Media Access Control, Media Access Control) Controller (controller) 13, order MAC Controller13 to send data packet again, after MAC Controller13 receives order, according to the Select the appropriate time to send the data packet to the PHY (Physical Layer Device, physical layer device) Transceiver (transceiver) 14. After the PHYTransceiver 14 completes the signal conversion, the data packet is sent to the network.
为了实现精度较高的时钟同步，MAC Controller13接收到CPU12发出的发送命令后，应该立即发出数据包，以保证由MAC Controller13引入的网络传输延迟波动最小，这就进一步要求，MAC Controller13发出数据包时，网络为空闲状态，即，没有其它数据包正在发送，而且网络上的其它节点也不会在一定时间内发出数据包，以免引起碰撞。所以，CPU12需要调度网络通讯以满足上述要求。此外，当MAC Controller13从网络上接收到一个数据包并向CPU12发出中断请求信号时，CPU12必须立即响应，使得由CPU12响应中断请求引入的网络传输延迟波动最小。In order to achieve clock synchronization with high precision, after receiving the sending command from CPU12, MAC Controller 13 should send out data packets immediately, so as to ensure that the network transmission delay fluctuation introduced by MAC Controller 13 is minimal, which further requires that when MAC Controller 13 sends out data packets , the network is idle, that is, no other data packets are being sent, and other nodes on the network will not send data packets within a certain period of time to avoid collisions. Therefore, the CPU 12 needs to schedule network communication to meet the above requirements. In addition, when MAC Controller 13 receives a data packet from the network and sends an interrupt request signal to CPU 12, CPU 12 must respond immediately, so that the fluctuation of network transmission delay introduced by CPU 12 in response to the interrupt request is minimal.
另外，在CPU12与MAC Controller13之间获取数据包的发送和接收的时间戳，再使用可调的振荡信号源调节时钟计数器的计数速度，力求达到时钟的同步，即主从时钟计数器的计数速度相同、计数值相等。在此过程中，记录CPU12向MAC Controller13发出发送命令的时刻作为发送时间戳，记录CPU12响应MAC Controller13的中断请求的时刻作为接收时间戳，获取时间戳的目的就是为了计算时钟计数器之间计数值的偏差，所以，时间戳的精准度直接影响计算出的偏差结果，从而间接影响校正的效果。但是，MACController13接收到CPU12发出的命令后，一般会选择在网络合适的状态时将数据包发出，所以，CPU12发出命令的时刻不一定是MAC Controller13发出数据包的时刻，此外，MAC Controller13向CPU12发出中断请求后，CPU12并不一定立即响应，CPU12响应该中断请求的真实时刻与CPU12当前的运行状态有关。因此，在CPU12与MAC Controller13之间获取的时间戳的精准度不高，从而导致这种方法实现的时钟同步的精度无法达到亚微秒级。In addition, the time stamps of sending and receiving data packets are obtained between CPU12 and MAC Controller13, and then an adjustable oscillation signal source is used to adjust the counting speed of the clock counter, and strive to achieve clock synchronization, that is, the counting speed of the master and slave clock counters is the same , the count value is equal. During this process, record the time when CPU12 sends a command to MAC Controller13 as the sending time stamp, and record the time when CPU12 responds to the interrupt request of MAC Controller13 as the receiving time stamp. The purpose of obtaining the time stamp is to calculate the count value between clock counters Therefore, the accuracy of the time stamp directly affects the calculated deviation result, which indirectly affects the correction effect. However, after MACController13 receives the command sent by CPU12, it will generally choose to send the data packet when the network is in a suitable state. Therefore, the time when CPU12 sends the command is not necessarily the time when MAC Controller13 sends the data packet. In addition, MAC Controller13 sends the data packet to CPU12. After the interrupt request, the CPU 12 does not necessarily respond immediately, and the real moment when the CPU 12 responds to the interrupt request is related to the current running state of the CPU 12 . Therefore, the accuracy of the time stamp obtained between the CPU 12 and the MAC Controller 13 is not high, so that the accuracy of clock synchronization achieved by this method cannot reach the sub-microsecond level.
因此，目前的时钟同步技术还没有实现高精度的时钟同步。Therefore, the current clock synchronization technology has not yet achieved high-precision clock synchronization.
发明内容Contents of the invention
本发明要解决的技术问题在于提供一种实现时钟同步的方法、装置、系统及分布式系统，以提高时钟同步的精度。The technical problem to be solved by the present invention is to provide a method, device, system and distributed system for realizing clock synchronization, so as to improve the precision of clock synchronization.
为解决上述问题，本发明提供一种实现时钟同步的方法，包括：在介质访问控制器与物理层设备收发器之间获取主机发出SYNC的本地发送时间戳和从机接收SYNC的本地接收时间戳，并获取从机发出DELAY_REQ的本地发送时间戳和主机接收DELAY_REQ的本地接收时间戳，利用获取的主机发出SYNC的本地发送时间戳、从机接收SYNC的本地接收时间戳、从机发出DELAY_REQ的本地发送时间戳和主机接收DELAY_REQ的本地接收时间戳，计算SYNC从主机传播到从机时的网络传输延迟；根据主机发出SYNC的本地发送时间戳、从机接收SYNC的本地接收时间戳和SYNC从主机传播到从机时的网络传输延迟，计算时钟计数器之间计数值的偏差；对所述偏差进行校正。In order to solve the above problems, the present invention provides a method for realizing clock synchronization, including: obtaining the local sending timestamp of the master sending SYNC and the local receiving timestamp of the slave receiving the SYNC between the media access controller and the physical layer device transceiver , and obtain the local sending timestamp of DELAY_REQ sent by the slave and the local receiving timestamp of DELAY_REQ received by the master, and use the acquired local sending timestamp of SYNC sent by the master, the local receiving timestamp of SYNC received by the slave, and the local receiving timestamp of DELAY_REQ sent by the slave The sending timestamp and the local receiving timestamp of the host receiving DELAY_REQ calculate the network transmission delay when SYNC propagates from the host to the slave; according to the local sending timestamp of the host sending SYNC, the local receiving timestamp of the slave receiving SYNC and the SYNC from the host The network transmission delay when propagating to the slave machine, calculating the deviation of the count value between the clock counters; correcting for said deviation.
获取主机发出SYNC的本地发送时间戳和从机接收SYNC的本地接收时间戳的过程由下述步骤实现：接收到SYNC后，记录所述SYNC的序号及从机接收SYNC的本地接收时间戳；接收到携带时间戳的FOLLOW_UP后，记录所述FOLLOW_UP的序号及所述时间戳，如果所述FOLLOW_UP的序号与所述SYNC的序号相同，则所述时间戳即为所述主机发出SYNC的本地发送时间戳。The process of obtaining the local sending timestamp of the host computer sending SYNC and the local receiving timestamp of the slave receiving the SYNC is realized by the following steps: after receiving the SYNC, record the sequence number of the SYNC and the local receiving timestamp of the slave receiving the SYNC; After the FOLLOW_UP carrying the timestamp, record the sequence number of the FOLLOW_UP and the timestamp, if the sequence number of the FOLLOW_UP is the same as the sequence number of the SYNC, then the timestamp is the local sending time of the SYNC sent by the host stamp.
按照如下公式计算时钟计数器之间计数值的偏差：The deviation of the count value between the clock counters is calculated according to the following formula:
Offset＝TxSyncTime-RxSyncTime+OneWayDelay，Offset=TxSyncTime-RxSyncTime+OneWayDelay,
其中，Offset为时钟计数器之间计数值的偏差，TxSyncTime为所述主机发出SYNC的本地发送时间戳，RxSyncTime为所述从机接收SYNC的本地接收时间戳，OneWayDelay为所述SYNC从主机传播到从机时的网络传输延迟。Among them, Offset is the deviation of the count value between the clock counters, TxSyncTime is the local sending timestamp of the SYNC sent by the master, RxSyncTime is the local receiving timestamp of the SYNC received by the slave, and OneWayDelay is the propagation of the SYNC from the master to the slave. The network transmission delay of the machine time.
获取从机发出DELAY_REQ的本地发送时间戳和主机接收DELAY_REQ的本地接收时间戳的过程由下述步骤实现：发出DELAY_REQ；记录所述DELAY_REQ的序号及从机发出DELAY_REQ的本地发送时间戳；接收携带时间戳的DELAY_RESP；记录所述DELAY_RESP的序号及所述时间戳，如果所述DELAY_RESP的序号与所述DELAY_REQ的序号相同，则所述时间戳即为所述主机接收DELAY_REQ的本地接收时间戳。The process of obtaining the local sending timestamp of the DELAY_REQ sent by the slave and the local receiving timestamp of the master receiving the DELAY_REQ is realized by the following steps: sending out the DELAY_REQ; recording the sequence number of the DELAY_REQ and the local sending timestamp of the DELAY_REQ sent by the slave; receiving the carrying time Stamped DELAY_RESP; record the sequence number of the DELAY_RESP and the timestamp, if the sequence number of the DELAY_RESP is the same as the sequence number of the DELAY_REQ, the timestamp is the local receiving timestamp of the host receiving the DELAY_REQ.
由下述公式计算所述第一数据包的网络传输延迟OneWayDelay：Calculate the network transmission delay OneWayDelay of the first data packet by the following formula:
OneWayDelay＝(RxReqTime-TxReqTime)/2-(TxSyncTime -RxSyncTime)/2，OneWayDelay＝(RxReqTime-TxReqTime)/2-(TxSyncTime-RxSyncTime)/2,
其中，RxReqTime为所述主机接收DELAY_REQ的本地接收时间戳，TxReqTime为所述从机发出DELAY_REQ的本地发送时间戳。Wherein, RxReqTime is the local receiving time stamp of the master receiving the DELAY_REQ, and TxReqTime is the local sending time stamp of the slave sending the DELAY_REQ.
对连续多次计算出的所述SYNC从主机传播到从机时的网络传输延迟OneWayDelay求平均值，将所述平均值作为计算Offset所使用的OneWayDelay。Calculate the average of the network transmission delay OneWayDelay when the SYNC is propagated from the master to the slave calculated multiple times in a row, and use the average as the OneWayDelay used for calculating the Offset.
对所述偏差进行校正的过程由下述步骤实现：根据所述偏差计算频率补偿值；调节所述频率补偿值，以使时钟计数器之间计数值的偏差为零。The process of correcting the deviation is realized by the following steps: calculating a frequency compensation value according to the deviation; adjusting the frequency compensation value so that the deviation of counting values between the clock counters is zero.
本发明还提供一种实现时钟同步的装置，包括：接收捕获器，用于在介质访问控制器与物理层设备收发器之间获取从机接收SYNC的本地接收时间戳、主机发出SYNC的本地发送时间戳及主机接收DELAY_REQ的本地接收时间戳；发送捕获器，用于在介质访问控制器与物理层设备收发器之间获取从机发出DELAY_REQ的本地发送时间戳；控制器，用于利用主机发出SYNC的本地发送时间戳、从机接收SYNC的本地接收时间戳、从机发出DELAY_REQ的本地发送时间戳和主机接收DELAY_REQ的本地接收时间戳，计算SYNC从主机传播到从机时的网络传输延迟，并根据所述从机接收SYNC的本地接收时间戳、主机发出SYNC的本地发送时间戳和SYNC从主机传播到从机时的网络传输延迟，计算时钟计数器之间计数值的偏差及根据所述偏差计算频率补偿值；频率补偿时钟，用于根据晶振频率及所述频率补偿值，调整计数速度。The present invention also provides a device for realizing clock synchronization, including: a receiving capture device, used to obtain the local reception time stamp of the SYNC received by the slave, and the local transmission time stamp of the SYNC sent by the master, between the media access controller and the physical layer device transceiver. Timestamp and local reception timestamp of DELAY_REQ received by the host; sending capturer, used to obtain local sending timestamp of DELAY_REQ sent by the slave between the media access controller and the physical layer device transceiver; controller, used to use the host to send The local sending timestamp of SYNC, the local receiving timestamp of SYNC received by the slave, the local sending timestamp of DELAY_REQ sent by the slave, and the local receiving timestamp of DELAY_REQ received by the master, calculate the network transmission delay when SYNC propagates from the master to the slave, And according to the local receiving timestamp of the slave receiving SYNC, the local sending timestamp of the master sending SYNC and the network transmission delay when SYNC propagates from the master to the slave, calculate the deviation of the count value between the clock counters and according to the deviation Calculate the frequency compensation value; the frequency compensation clock is used to adjust the counting speed according to the frequency of the crystal oscillator and the frequency compensation value.
所述时钟计数器为频率补偿时钟。The clock counter is a frequency compensated clock.
本发明还提供一种实现时钟同步的系统，包括：CPU，用于处理数据包；介质访问控制器，用于缓存数据包；物理层设备收发器，用于将数据包进行信号转换；其中，所述介质访问控制器根据所述CPU的命令将所述缓存的数据包发送到所述物理层设备收发器，和/或，将所述缓存的数据包发送到所述CPU；所述系统还包括：时钟同步器，用于在所述介质访问控制器与所述物理层设备收发器之间获取主机发出SYNC的本地发送时间戳和从机接收SYNC的本地接收时间戳，并获取从机发出DELAY_REQ的本地发送时间戳和主机接收DELAY_REQ的本地接收时间戳，利用获取的主机发出SYNC的本地发送时间戳、从机接收SYNC的本地接收时间戳、从机发出DELAY_REQ的本地发送时间戳和主机接收DELAY_REQ的本地接收时间戳，计算SYNC从主机传播到从机时的网络传输延迟，根据主机发出SYNC的本地发送时间戳、从机接收SYNC的本地接收时间戳和SYNC从主机传播到从机时的网络传输延迟，计算时钟计数器之间计数值的偏差，以及对所述偏差进行校正。The present invention also provides a system for implementing clock synchronization, including: a CPU for processing data packets; a media access controller for buffering data packets; a physical layer device transceiver for performing signal conversion on data packets; wherein, The media access controller sends the buffered data packet to the physical layer device transceiver according to a command of the CPU, and/or sends the buffered data packet to the CPU; the system further Including: a clock synchronizer, used to obtain the local sending timestamp of SYNC sent by the master and the local receiving timestamp of receiving SYNC sent by the slave between the medium access controller and the physical layer device transceiver, and obtain the time stamp sent by the slave The local sending timestamp of DELAY_REQ and the local receiving timestamp of the host receiving DELAY_REQ, using the obtained local sending timestamp of the master sending SYNC, the local receiving timestamp of the slave receiving SYNC, the local sending timestamp of the slave sending DELAY_REQ and the host receiving The local receiving timestamp of DELAY_REQ calculates the network transmission delay when SYNC propagates from the master to the slave, based on the local sending timestamp of the master sending SYNC, the local receiving timestamp of the slave receiving SYNC and the time when SYNC propagates from the master to the slave Network transmission delay, calculation of deviation of count values between clock counters, and correction of said deviation.
所述时钟同步器为现场可编程门阵列FPGA。The clock synchronizer is a field programmable gate array FPGA.
本发明还提供一种分布式系统，包括至少一个主机及至少一个从机，所述主机及从机分别包括：CPU，用于处理数据包；介质访问控制器，用于缓存数据包；物理层设备收发器，用于将数据包进行信号转换；所述从机还包 括：时钟同步器，用于在所述介质访问控制器与所述物理层设备收发器之间获取主机发出SYNC的本地发送时间戳和从机接收SYNC的本地接收时间戳，并获取从机发出DELAY_REQ的本地发送时间戳和主机接收DELAY_REQ的本地接收时间戳，利用获取的主机发出SYNC的本地发送时间戳、从机接收SYNC的本地接收时间戳、从机发出DELAY_REQ的本地发送时间戳和主机接收DELAY_REQ的本地接收时间戳，计算SYNC从主机传播到从机时的网络传输延迟，根据主机发出SYNC的本地发送时间戳、从机接收SYNC的本地接收时间戳和SYNC从主机传播到从机时的网络传输延迟，计算时钟计数器之间计数值的偏差，以及对所述偏差进行校正。The present invention also provides a distributed system, including at least one host and at least one slave, the host and slave respectively include: a CPU for processing data packets; a media access controller for caching data packets; a physical layer The device transceiver is used to perform signal conversion on the data packet; the slave also includes: a clock synchronizer, used to obtain the local SYNC sent by the master between the media access controller and the physical layer device transceiver. Send the timestamp and the local receiving timestamp of SYNC received by the slave, and obtain the local sending timestamp of DELAY_REQ sent by the slave and the local receiving timestamp of DELAY_REQ received by the master, and use the acquired local sending timestamp of SYNC issued by the master, and the slave receives The local receiving timestamp of SYNC, the local sending timestamp of DELAY_REQ sent by the slave, and the local receiving timestamp of DELAY_REQ received by the master, calculate the network transmission delay when SYNC propagates from the master to the slave, according to the local sending timestamp of SYNC sent by the master, The slave machine receives the local reception time stamp of SYNC and the network transmission delay when SYNC propagates from the master machine to the slave machine, calculates the deviation of count values between the clock counters, and corrects the deviation.
所述主机还包括：时钟同步器，用于监听介质访问控制器与物理层设备收发器之间的所有信号。The host also includes: a clock synchronizer, configured to monitor all signals between the media access controller and the transceiver of the physical layer device.
与现有技术相比，本发明具有以下优点：Compared with the prior art, the present invention has the following advantages:
在本发明中，时间戳的获取点在介质访问控制器与物理层设备收发器之间，由于数据包需要依次经过CPU、介质访问控制器及物理层设备收发器才能发送到网络中，一般情况下，介质访问控制器在接到CPU发送命令后不会立即将数据包发出，所以，如果在CPU与介质访问控制器之间获取时间戳，则后续计算出的偏差不是很准，因此，本发明获取的时间戳可以为后续处理提供更为准确的依据，从而更合适的校正偏差，提高时钟同步的精度。In the present invention, the acquisition point of the time stamp is between the media access controller and the physical layer device transceiver. Since the data packet needs to pass through the CPU, the media access controller and the physical layer device transceiver in order to be sent to the network, in general Under the circumstances, the media access controller will not send the data packet immediately after receiving the command sent by the CPU. Therefore, if the time stamp is obtained between the CPU and the media access controller, the subsequent calculated deviation is not very accurate. Therefore, this The time stamp obtained by the invention can provide more accurate basis for subsequent processing, thereby correcting the deviation more appropriately and improving the precision of clock synchronization.
在本发明中，可以使用频率补偿时钟调节频率补偿值，频率补偿时钟是一种硬件实现的高分辨率、高精度的时钟计数器，它的存在使得，即使使用普通的不可调有源或无源晶振作时钟信号源，仍然可以实现时钟的精确调节，由于使用不可调晶振成本较低，所以，使用频率补偿时钟可以降低成本。In the present invention, the frequency compensation value can be adjusted using the frequency compensation clock, which is a high-resolution, high-precision clock counter implemented by hardware, and its existence makes it possible to use ordinary non-adjustable active or passive Using a crystal oscillator as a clock signal source can still achieve precise clock adjustment. Since the cost of using a non-adjustable crystal oscillator is low, using a frequency compensated clock can reduce costs.
在本发明中，对网络传输延迟可以求平均值，以平均值作为计算偏差的数据，降低了网络传输延迟的波动对同步精度的影响。In the present invention, the network transmission delay can be averaged, and the average value is used as the data for calculating the deviation, which reduces the influence of the fluctuation of the network transmission delay on the synchronization accuracy.
附图说明Description of drawings
图1为目前的一种时钟同步系统的结构示意图；FIG. 1 is a schematic structural diagram of a current clock synchronization system;
图2是本发明方法的一种流程图；Fig. 2 is a kind of flowchart of the inventive method;
图3是本发明装置的一种结构示意图；Fig. 3 is a kind of structural representation of device of the present invention;
图4为频率补偿时钟的结构示意图；FIG. 4 is a schematic structural diagram of a frequency compensation clock;
图5为本发明的时钟同步系统的一种结构示意图。FIG. 5 is a schematic structural diagram of the clock synchronization system of the present invention.
具体实施方式Detailed ways
下面我们将结合附图，对本发明的最佳实施方案进行详细描述。首先要指出的是，本发明中用到的术语、字词及权利要求的含义不能仅仅限于其字面和普通的含义去理解，还包括进而与本发明的技术相符的含义和概念，这是因为我们作为发明者，要适当地给出术语的定义，以便对我们的发明进行最恰当的描述。因此，本说明和附图中给出的配置，只是本发明的首选实施方案，而不是要列举本发明的所有技术特性。我们要认识到，还有各种各样的可以取代我们方案的同等方案或修改方案。Below we will describe in detail the best implementation of the present invention with reference to the accompanying drawings. First of all, it should be pointed out that the meanings of the terms, words and claims used in the present invention should not be limited to their literal and ordinary meanings, but also include meanings and concepts that are consistent with the technology of the present invention. This is because It is up to us, as inventors, to define terms appropriately in order to best describe our inventions. Therefore, the configurations given in this specification and the accompanying drawings are only preferred implementations of the present invention, rather than enumerating all technical characteristics of the present invention. We need to recognize that there are various equivalents or modifications that could replace ours.
首先，对本发明提供的方法的整体技术方案进行说明。本发明的方法包括：在介质访问控制器与物理层设备收发器之间获取第一数据包的本地发送时间戳和本地接收时间戳；根据所述第一数据包的本地发送时间戳和本地接收时间戳计算时钟计数器之间计数值的偏差；对所述偏差进行校正。First, the overall technical solution of the method provided by the present invention is described. The method of the present invention includes: obtaining the local sending timestamp and the local receiving timestamp of the first data packet between the medium access controller and the physical layer device transceiver; according to the local sending timestamp and the local receiving timestamp of the first data packet, The time stamp counts the deviation of the count value between the clock counters; the deviation is corrected for.
本发明提供的方法可以应用在分布式系统中，进一步的，应用在分布式系统中的主机和/或从机中的时钟同步系统，时钟同步系统应该包含一个时钟同步装置。The method provided by the present invention can be applied in a distributed system, and further applied to a clock synchronization system in a master and/or a slave in a distributed system, and the clock synchronization system should include a clock synchronization device.
现在对本发明的方法进行详细说明。The method of the present invention will now be described in detail.
图2是实施本发明方法的一种流程图。如图2所示：Figure 2 is a flow chart for implementing the method of the present invention. as shown in picture 2:
步骤S201：主机每隔一定时间发出SYNC(第一数据包)，并记录SYNC的序号TxSyncSeq及本地发送时间戳TxSyncTime。Step S201: The host sends SYNC (the first data packet) at regular intervals, and records the serial number TxSyncSeq of the SYNC and the local sending time stamp TxSyncTime.
主机每次发出SYNC的时间间隔应该相同，例如，可以固定为1秒，但这个时间间隔允许有±10％的误差。The time interval for the host to send SYNC each time should be the same, for example, it can be fixed at 1 second, but this time interval is allowed to have an error of ±10%.
SYNC以PTP(Precision Time Protocol，精确时间协议)的格式进行封装，作为MAC子层的广播帧或多播帧发出，网络中的所有从机都可以接收到这个帧。SYNC is encapsulated in the format of PTP (Precision Time Protocol, Precision Time Protocol), and sent as a broadcast frame or multicast frame of the MAC sublayer, and all slaves in the network can receive this frame.
主机发出SYNC时，主机的时钟同步装置会探测到SYNC的发出，并记录SYNC的序号TxSyncSeq及本地发送时间戳TxSyncTime。主机的时钟同步装置对SYNC携带的数据可以忽略。When the host sends out SYNC, the clock synchronization device of the host will detect the sending of SYNC, and record the sequence number TxSyncSeq of SYNC and the local sending time stamp TxSyncTime. The host's clock synchronization device can ignore the data carried by SYNC.
步骤S202：从机记录所述SYNC的序号RxSyncSeq和本地接收时间戳RxSyncTime。Step S202: the slave device records the sequence number RxSyncSeq of the SYNC and the local reception time stamp RxSyncTime.
从机的时钟同步装置探测到SYNC时，只记录所述SYNC的序号RxSyncSeq和本地接收时间戳RxSyncTime，对所述SYNC携带的数据可以忽略。When the clock synchronization device of the slave machine detects the SYNC, it only records the serial number RxSyncSeq of the SYNC and the local reception time stamp RxSyncTime, and the data carried by the SYNC can be ignored.
步骤S203：主机将记录的SYNC的序号TxSyncSeq及本地发送时间戳TxSyncTime封装成FOLLOW UP(第二数据包)发出。Step S203: The host encapsulates the recorded SYNC serial number TxSyncSeq and the local transmission time stamp TxSyncTime into a FOLLOW UP (second data packet) and sends it out.
主机发出SYNC后，主机的CPU立即从主机的时钟同步装置中取出SYNC的序号TxSyncSeq及本地发送时间戳TxSyncTime，将TxSyncSeq作为序号， TxSyncTime作为数据，封装成一个新的数据包FOLLOW_UP发出，FOLLOW_UP也是作为MAC子层的广播帧或多播帧发出，网络中的所有从机都可以接收到这个帧。After the host sends SYNC, the CPU of the host immediately takes out the serial number TxSyncSeq of SYNC and the local transmission time stamp TxSyncTime from the clock synchronization device of the host, and uses TxSyncSeq as the serial number and TxSyncTime as data, and encapsulates it into a new data packet FOLLOW_UP and sends it out, and FOLLOW_UP is also sent as The broadcast frame or multicast frame of the MAC sublayer is sent out, and all slaves in the network can receive this frame.
步骤S204：从机记录FOLLOW_UP的序号RxFollowSeq和携带的数据TxSyncTime，获得TxSyncTime-RxSyncTime时间戳对。Step S204: The slave records the serial number RxFollowSeq of FOLLOW_UP and the carried data TxSyncTime, and obtains a TxSyncTime-RxSyncTime timestamp pair.
从机接收到FOLLOW_UP后，从机的时钟同步装置不但可以记录FOLLOW_UP的序号RxFollowSeq，还可以获取FOLLOW_UP中携带的数据TxSyncTime，并记录TxSyncTime。从机还可以进一步判断RxSyncSeq和RxFollowSeq是否相同，如果是，则获得了一个TxSyncTime-RxSyncTime时间戳对。After the slave machine receives FOLLOW_UP, the clock synchronization device of the slave machine can not only record the serial number RxFollowSeq of FOLLOW_UP, but also obtain the data TxSyncTime carried in FOLLOW_UP, and record TxSyncTime. The slave can further determine whether RxSyncSeq and RxFollowSeq are the same, and if so, a TxSyncTime-RxSyncTime timestamp pair is obtained.
步骤S205：从机向主机发出DELAY_REQ，并记录DELAY_REQ(第三数据包)的序号TxReqSeq和本地发送时间戳TxReqTime。Step S205: the slave sends a DELAY_REQ to the master, and records the serial number TxReqSeq of the DELAY_REQ (the third data packet) and the local transmission time stamp TxReqTime.
从机接收到SYNC或FOLLOW_UP时，就获得了主机的物理地址。接收到FOLLOW_UP之后，从机主动向主机发出DELAY_REQ，DELAY_REQ是一个MAC子层的单播帧，只有主机才能收到。从机的时钟同步装置探测到DELAY_REQ的发出，记录DELAY_REQ的序号TxReqSeq和本地发送时间戳TxReqTime。When the slave receives SYNC or FOLLOW_UP, it obtains the physical address of the master. After receiving FOLLOW_UP, the slave actively sends DELAY_REQ to the master. DELAY_REQ is a MAC sublayer unicast frame, which can only be received by the master. The clock synchronization device of the slave detects the sending of DELAY_REQ, and records the serial number TxReqSeq of DELAY_REQ and the local sending time stamp TxReqTime.
步骤S206：主机记录DELAY_REQ的源物理地址SlavePhyAddr、序号RxReqSeq和本地接收时间戳RxReqTime。Step S206: The host records the source physical address SlavePhyAddr of the DELAY_REQ, the sequence number RxReqSeq and the local receiving time stamp RxReqTime.
DELAY_REQ到达主机时，主机的时钟同步装置探测到DELAY_REQ的到来，记录DELAY_REQ的源物理地址SlavePhyAddr、序号RxReqSeq和本地接收时间戳RxReqTime。When the DELAY_REQ arrives at the host, the clock synchronization device of the host detects the arrival of the DELAY_REQ, and records the source physical address SlavePhyAddr of the DELAY_REQ, the serial number RxReqSeq and the local receiving time stamp RxReqTime.
由于可能存在多个从机同时向主机发出DELAY_REQ而主机不能迅速处理完所有DELAY_REQ的情况，所以主机可以使用队列来保存SlavePhyAddr、RxReqSeq和RxReqTime，按照FIFO(First-In First-Out，先进先出)原则依序处理所有的DELAY_REQ。主机的时钟同步装置在探测到一个新的数据帧到来时，备份当前队列的写指针，随着数据的不断接收，将接收数据流中对应于DELAY_REQ中的SlavePhyAddr、RxReqSeq和RxReqTime位置的数据存入队列，并将RxReqTime位置的数据替换为主机记录的这个帧的本地接收时间戳。当这个帧接收完毕的同时，主机的时钟同步装置就已经识别出它是 否为DELAY_REQ，如果不是，则将队列的写指针恢复为刚开始接收这个帧时备份的那个值，如果是，则不做任何操作。为了防止在意外情况下，主机的CPU对接收帧的解析结果不同于时钟同步装置对同一个接收帧的解析结果，导致上一个同步周期的RxReqTime等信息留在队列中未被读取而造成不良影响，主机的时钟同步装置在每次探测到SYNC发出时，都将队列的读指针设定为当前的写指针的值。Since there may be multiple slaves sending DELAY_REQ to the host at the same time and the host cannot quickly process all DELAY_REQs, the host can use the queue to save SlavePhyAddr, RxReqSeq and RxReqTime, according to FIFO (First-In First-Out, first-in-first-out) The principle is to process all DELAY_REQs sequentially. When the host’s clock synchronization device detects the arrival of a new data frame, it backs up the write pointer of the current queue, and as the data is continuously received, it stores the data corresponding to the SlavePhyAddr, RxReqSeq and RxReqTime positions in the DELAY_REQ in the received data stream into queue, and replace the data at the RxReqTime position with the local reception timestamp of this frame recorded by the host. When this frame is received completely, the clock synchronization device of the host computer has just identified whether it is DELAY_REQ, if not, then restores the write pointer of the queue to the value that was backed up when the frame was just received, if yes, then no do anything. In order to prevent unexpected situations, the analysis result of the received frame by the CPU of the host is different from the analysis result of the same received frame by the clock synchronization device, resulting in information such as RxReqTime of the previous synchronization cycle being left in the queue without being read, resulting in bad As a result, the clock synchronization device of the host will set the read pointer of the queue to the value of the current write pointer every time it detects that SYNC is sent.
步骤S207：主机将SlavePhyAddr、RxReqSeq、RxReqTime封装成DELAY_RESP(第四数据包)并发送给从机。Step S207: The host encapsulates SlavePhyAddr, RxReqSeq, and RxReqTime into a DELAY_RESP (fourth data packet) and sends it to the slave.
主机收到从机发出的DELAY_REQ之后，从时钟同步装置中取出SlavePhyAddr、RxReqSeq、RxReqTime，封装成DELAY_RESP并发出，其中，SlavePhyAddr作为目标物理地址，RxReqSeq作为序号，RxReqTime作为普通数据。After receiving the DELAY_REQ sent by the slave, the host takes out SlavePhyAddr, RxReqSeq, and RxReqTime from the clock synchronization device, encapsulates it into DELAY_RESP and sends it out, wherein SlavePhyAddr is used as the target physical address, RxReqSeq is used as the sequence number, and RxReqTime is used as ordinary data.
步骤S208：从机记录DELAY_RESP的序号及DELAY_RESP携带的数据RxReqTime，获得一个TxReqTime-RxReqTime时间戳对。Step S208: the slave records the serial number of DELAY_RESP and the data RxReqTime carried by DELAY_RESP, and obtains a TxReqTime-RxReqTime timestamp pair.
DELAY_RESP到达从机时，从机记录DELAY_RESP的序号RxRespSeq和DELAY_RESP携带的数据RxReqTime，如果TxReqSeq和RxRespSeq相同，则获得了一个TxReqTime-RxReqTime时间戳对。When DELAY_RESP arrives at the slave, the slave records the sequence number RxRespSeq of DELAY_RESP and the data RxReqTime carried by DELAY_RESP. If TxReqSeq and RxRespSeq are the same, a TxReqTime-RxReqTime timestamp pair is obtained.
步骤S209：利用获得的TxSyncTime-RxSyncTime时间戳对及TxReqTime-RxReqTime时间戳对计算SYNC从主机传播到从机时的网络传输延迟。Step S209: Use the obtained TxSyncTime-RxSyncTime timestamp pair and TxReqTime-RxReqTime timestamp pair to calculate the network transmission delay when SYNC propagates from the master to the slave.
按如下公式即可计算出网络传输延迟OneWayDelay的值：The value of the network transmission delay OneWayDelay can be calculated according to the following formula:
OneWayDelay＝(RxReqTime-TxReqTime)/2-(TxSyncTime-RxSyncTime)/2，OneWayDelay=(RxReqTime-TxReqTime)/2-(TxSyncTime-RxSyncTime)/2,
其中，TxSyncTime-RxSyncTime是获得RxReqTime-TxReqTime之前最近一次获得的时间戳对。Wherein, TxSyncTime-RxSyncTime is the last time stamp pair obtained before obtaining RxReqTime-TxReqTime.
为了减小网络传输延迟的波动对后续计算的影响，可以使用均值滤波的方法，即，对最近多次计算出的OneWayDelay求平均值，这个平均值作为SYNC从主机传播到从机时的网络传输延迟的值。实验表明，将最近16次OneWayDelay求得的平均值作为SYNC从主机传播到从机时的网络传输延迟的值比较理想。In order to reduce the impact of network transmission delay fluctuations on subsequent calculations, the mean filtering method can be used, that is, to average the recently calculated OneWayDelay multiple times, and this average value is used as the network transmission when SYNC propagates from the master to the slave The value of the delay. Experiments show that it is ideal to use the average value obtained by the last 16 OneWayDelays as the value of the network transmission delay when SYNC propagates from the master to the slave.
步骤S210：利用获得的TxSyncTime-RxSyncTime时间戳对及SYNC从 主机传播到从机时的网络传输延迟的值计算主机时钟计数器与从机时钟计数器之间计数值的偏差。Step S210: Using the obtained TxSyncTime-RxSyncTime timestamp pair and the value of the network transmission delay when SYNC propagates from the master to the slave, calculate the deviation of the count value between the clock counter of the master and the clock counter of the slave.
按如下公式即可计算出从机时钟计数器与主机时钟计数器之间计数值的偏差Offset：The offset of the count value offset between the slave clock counter and the master clock counter can be calculated according to the following formula:
Offset＝TxSyncTime-RxSyncTime+OneWayDelay，Offset=TxSyncTime-RxSyncTime+OneWayDelay,
其中，当主机时钟比从机时钟快时，Offset大于零，主机时钟比从机时钟慢时，Offset小于零。Wherein, when the master clock is faster than the slave clock, the Offset is greater than zero, and when the master clock is slower than the slave clock, the Offset is less than zero.
步骤S211：根据主机时钟计数器与从机时钟计数器之间的计数值的偏差计算频率补偿值。Step S211: Calculate the frequency compensation value according to the deviation of the count value between the master clock counter and the slave clock counter.
步骤S212：调节频率补偿值，以使主机时钟计数器与从机时钟计数器之间的计数值的偏差在一定时间内逐渐变为零。Step S212: Adjust the frequency compensation value so that the deviation of the count value between the master clock counter and the slave clock counter gradually becomes zero within a certain period of time.
假设上一次同步时计算出的偏差为Offset0，当前一次同步时计算出的偏差为Offset1，则可以预测，下一次同步时计算出的偏差将是Offset2＝2*Offset1 -Offset0。因此，应当调节频率补偿值，使得从机时钟在当前这个同步周期内时钟计数器的值的增加量比上一个同步周期多Offset2，于是，下一次同步时计算出的偏差将是零。Assuming that the offset calculated in the last synchronization is Offset0 and the offset calculated in the previous synchronization is Offset1 , it can be predicted that the offset calculated in the next synchronization will be Offset2 =2*Offset1 -Offset0 . Therefore, the frequency compensation value should be adjusted so that the increment of the clock counter value of the slave clock in the current synchronization period is Offset2 more than the previous synchronization period, so the calculated deviation in the next synchronization will be zero.
在获得了Offset的条件下，计算出新的频率补偿值，实现对时钟计数器计数速度的微量调节，使得主机时钟计数器之间与从机时钟计数器之间的计数速度一致，消除计数值的偏差，达到时钟同步的目的。Under the condition that the Offset is obtained, a new frequency compensation value is calculated to realize the micro-adjustment of the counting speed of the clock counter, so that the counting speed between the master clock counter and the slave clock counter is consistent, and the deviation of the count value is eliminated. To achieve the purpose of clock synchronization.
需要说明的是，SYNC、FOLLOW_UP、DELAY_REQ及DELAY_RESP都是UDP(User Datagram Protocol，用户数据报文协议)帧，在UDP帧的字段payload中包含着PTP帧的序号和时间戳，其中，FOLLOW_UP和DELAY_RESP中的时间戳的数值是有意义的，而SYNC和DELAY_REQ中的时间戳的数值是可以任意填写的。It should be noted that SYNC, FOLLOW_UP, DELAY_REQ, and DELAY_RESP are all UDP (User Datagram Protocol, User Datagram Protocol) frames, and the field payload of the UDP frame contains the serial number and timestamp of the PTP frame, where FOLLOW_UP and DELAY_RESP The value of the timestamp in is meaningful, and the value of the timestamp in SYNC and DELAY_REQ can be filled in arbitrarily.
无论是主机还是从机识别出正在发出的数据帧的前导码(preamble)之后的帧起始标志位(Start Frame Delimiter)时，都可以记录这个帧的本地发送时间戳。如果主机识别出这个帧为SYNC，则保存这个时间戳供主机的CPU读取；如果从机识别出这个帧为DELAY_REQ，则保存这个时间戳用于计算频率补偿值。When the host or the slave recognizes the frame start flag (Start Frame Delimiter) after the preamble of the data frame being sent, it can record the local sending timestamp of this frame. If the master recognizes that the frame is SYNC, it saves the time stamp for the CPU of the master to read; if the slave recognizes that the frame is DELAY_REQ, it saves the time stamp for calculating the frequency compensation value.
无论是主机还是从机识别出正在接收的数据帧的前导码(preamble)之后 的帧起始标志位(Start Frame Delimiter)时，都可以记录这个帧的本地接收时间戳。如果主机识别出这个帧为DELAY_REQ，则保存这个时间戳供主机的CPU读取；如果从机识别出这个帧为SYNC，则保存这个时间戳用于计算频率补偿值。When the host or the slave recognizes the frame start flag (Start Frame Delimiter) after the preamble of the data frame being received, it can record the local reception timestamp of this frame. If the master recognizes that the frame is DELAY_REQ, it saves the time stamp for the CPU of the master to read; if the slave recognizes that the frame is SYNC, it saves the time stamp for calculating the frequency compensation value.
现在对本发明的时钟同步装置及其工作原理进行说明。Now, the clock synchronization device of the present invention and its working principle will be described.
图3是本发明装置的一种结构示意图。如图3所示，时钟同步装置31包括：发送捕获器(transmit capture)311，用于监听从介质访问控制器流向物理层设备收发器的数据，并判断当前流过的数据帧是否为PTP帧；接收捕获器(receive capture)312，用于监听从物理层设备收发器流向介质访问控制器的数据，并判断当前流过的数据帧是否为PTP帧；CPU接口(CPU interface)313，用于与CPU交互数据及控制信息，对于CPU来说，这个接口等效于一个RAM(Random Access Memory，随机存取存储器)；控制器(controller)314，用于计算时钟计数器的频率补偿值；频率补偿时钟(frequencycompensation clock)315，为一个64位可调时钟计数器，用于根据晶振频率及所述频率补偿值进行计数以计量时间。Fig. 3 is a schematic structural view of the device of the present invention. As shown in Figure 3, the clock synchronization device 31 includes: a transmit capture device (transmit capture) 311, which is used to monitor the data flowing from the media access controller to the physical layer device transceiver, and judge whether the current data frame flowing through is a PTP frame ; Receive capture device (receive capture) 312, be used to monitor the data that flows to medium access controller from physical layer device transceiver, and judge whether the data frame that current flows through is PTP frame; CPU interface (CPU interface) 313, is used for Interact data and control information with CPU, for CPU, this interface is equivalent to a RAM (Random Access Memory, random access memory); Controller (controller) 314, is used for calculating the frequency compensation value of clock counter; Frequency compensation The clock (frequency compensation clock) 315 is a 64-bit adjustable clock counter, used for counting according to the crystal oscillator frequency and the frequency compensation value to measure time.
需要说明的是，主机与从机均可具有时钟同步装置31。It should be noted that both the master and the slave can have a clock synchronization device 31 .
主机每隔一定时间发出SYNC，主机的发送捕获器311会探测到SYNC的发出，并记录SYNC的序号TxSyncSeq及本地发送时间戳TxSyncTime。主机的发送捕获器311对SYNC携带的数据可以忽略。从机的接收捕获器312探测到SYNC时，只记录所述SYNC的序号RxSyncSeq和本地接收时间戳RxSyncTime，对所述SYNC携带的数据也可以忽略。The host sends out SYNC at regular intervals, and the sending capture device 311 of the host will detect the sending of the SYNC, and record the sequence number TxSyncSeq of the SYNC and the local sending time stamp TxSyncTime. The data carried by the SYNC can be ignored by the sending catcher 311 of the host. When the reception capture unit 312 of the slave machine detects a SYNC, it only records the sequence number RxSyncSeq of the SYNC and the local reception time stamp RxSyncTime, and the data carried by the SYNC can also be ignored.
主机发出SYNC后，主机的CPU立即通过主机的CPU接口313从主机的时钟同步装置31中取出SYNC的序号TxSyncSeq及本地发送时间戳TxSyncTime，将TxSyncSeq作为序号，TxSyncTime作为数据，封装成一个新的数据包FOLLOW_UP发出。从机接收到FOLLOW_UP后，从机的接收捕获器312不但可以记录FOLLOW_UP的的序号RxFollowSeq，还可以获取FOLLOW_UP中携带的数据TxSyncTime，并记录TxSyncTime。从机还可以进一步判断RxSyncSeq和RxFollowSeq是否相同，如果是，则获得了一个TxSyncTime-RxSyncTime时间戳对。After the host sends SYNC, the CPU of the host immediately takes out the sequence number TxSyncSeq of SYNC and the local transmission time stamp TxSyncTime from the clock synchronization device 31 of the host through the CPU interface 313 of the host, and uses TxSyncSeq as the sequence number and TxSyncTime as data, and encapsulates it into a new data The package FOLLOW_UP is emitted. After the slave machine receives the FOLLOW_UP, the receiver 312 of the slave machine can not only record the serial number RxFollowSeq of the FOLLOW_UP, but also obtain the data TxSyncTime carried in the FOLLOW_UP, and record the TxSyncTime. The slave can further determine whether RxSyncSeq and RxFollowSeq are the same, and if so, a TxSyncTime-RxSyncTime timestamp pair is obtained.
从机接收到SYNC或FOLLOW_UP时，就获得了主机的物理地址。接收 到FOLLOW_UP之后，从机主动向主机发出DELAY_REQ，从机的发送捕获器311探测到DELAY_REQ的发出，记录DELAY_REQ的序号TxReqSeq和本地发送时间戳TxReqTime。DELAY_REQ到达主机时，主机的接收捕获器312探测到DELAY_REQ的到来，记录DELAY_REQ的源物理地址SlavePhyAddr、序号RxReqSeq和本地接收时间戳RxReq_Time。When the slave receives SYNC or FOLLOW_UP, it obtains the physical address of the master. After receiving FOLLOW_UP, the slave actively sends DELAY_REQ to the master, and the sender 311 of the slave detects the sending of DELAY_REQ, records the sequence number TxReqSeq of DELAY_REQ and the local sending time stamp TxReqTime. When the DELAY_REQ arrives at the host, the reception capturer 312 of the host detects the arrival of the DELAY_REQ, and records the source physical address SlavePhyAddr of the DELAY_REQ, the serial number RxReqSeq and the local receiving time stamp RxReq_Time.
由于可能存在多个从机同时向主机发出DELAY_REQ而主机不能迅速处理完所有DELAY_REQ的情况，所以主机可以使用队列来保存SlavePhyAddr、RxReqSeq和RxReqTime，按照FIFO(First-In First-Out，先进先出)原则依序处理所有的DELAY_REQ。主机的接收捕获器312在探测到一个新的数据帧到来时，备份当前队列的写指针，随着数据的不断接收，将接收数据流中对应于DELAY_REQ中的SlavePhyAddr、RxReqSeq和RxReqTime位置的数据存入队列，并将RxReqTime位置的数据替换为主机记录的这个帧的本地接收时间戳。当这个帧接收完毕的同时，主机的接收捕获器312就已经识别出它是否为DELAY_REQ，如果不是，则将队列的写指针恢复为刚开始接收这个帧时备份的那个值，如果是，则不做任何操作。为了防止在意外情况下，主机的CPU对接收帧的解析结果不同于接收捕获器312对同一个接收帧的解析结果，导致上一个同步周期的RxReqTime等信息留在队列中未被读取而造成不良影响，主机的发送捕获器311每次探测到SYNC发出时，主机都将队列的读指针设定为当前的写指针的值。Since there may be multiple slaves sending DELAY_REQ to the host at the same time and the host cannot quickly process all DELAY_REQs, the host can use the queue to save SlavePhyAddr, RxReqSeq and RxReqTime, according to FIFO (First-In First-Out, first-in-first-out) The principle is to process all DELAY_REQs sequentially. The receiving catcher 312 of the main frame detects the arrival of a new data frame, backs up the write pointer of the current queue, and along with the continuous reception of data, stores the data corresponding to the SlavePhyAddr, RxReqSeq and RxReqTime positions in the receiving data stream in the DELAY_REQ Enter the queue, and replace the data at the RxReqTime position with the local reception timestamp of this frame recorded by the host. When this frame has been received completely, the receiving catcher 312 of the main frame has just identified whether it is DELAY_REQ, if not, then the write pointer of the queue is restored to the value backed up when just beginning to receive this frame, if so, then no do anything. In order to prevent that under unexpected circumstances, the analysis result of the received frame by the CPU of the host is different from the analysis result of the same received frame by the receiver capturer 312, resulting in information such as RxReqTime of the last synchronization cycle remaining in the queue and not being read. As a bad effect, every time the send capture device 311 of the host detects that SYNC is sent, the host sets the read pointer of the queue to the value of the current write pointer.
主机收到从机发出的DELAY_REQ之后，通过主机的CPU接口313从时钟同步装置31中取出SlavePhyAddr、RxReqSeq、RxReqTime，封装成DELAY_RESP并发出，其中，SlavePhyAddr作为目标物理地址，RxReqSeq作为序号，RxReqTime作为普通数据。DELAY_RESP到达从机时，从机的接收捕获器312记录DELAY_RESP的序号RxRespSeq和DELAY_RESP携带的数据RxReqTime，如果TxReqSeq和RxRespSeq相同，则获得了一个TxReqTime-RxReqTime时间戳对。After receiving the DELAY_REQ sent by the slave, the host takes out SlavePhyAddr, RxReqSeq, and RxReqTime from the clock synchronization device 31 through the CPU interface 313 of the host, encapsulates them into DELAY_RESP and sends it out, wherein SlavePhyAddr is used as the target physical address, RxReqSeq is used as the sequence number, and RxReqTime is used as the common data. When the DELAY_RESP arrives at the slave, the receiving capturer 312 of the slave records the sequence number RxRespSeq of the DELAY_RESP and the data RxReqTime carried by the DELAY_RESP. If the TxReqSeq and RxRespSeq are the same, a TxReqTime-RxReqTime timestamp pair is obtained.
控制器314利用获得的TxSyncTime-RxSyncTime时间戳对及TxReqTime-RxReqTime时间戳对计算SYNC从主机传播到从机时的网络传输延迟。The controller 314 uses the obtained TxSyncTime-RxSyncTime timestamp pair and TxReqTime-RxReqTime timestamp pair to calculate the network transmission delay when SYNC propagates from the master to the slave.
可以按如下公式即可计算出网络传输延迟OneWayDelay的值：The value of the network transmission delay OneWayDelay can be calculated according to the following formula:
OneWayDelay＝(RxReqTime-TxReqTime)/2-(TxSyncTime -RxSyncTime)/2，OneWayDelay＝(RxReqTime-TxReqTime)/2-(TxSyncTime-RxSyncTime)/2,
其中，RxReqTime-TxReqTime是获得TxSyncTime-RxSyncTime后最近一次获得的时间戳。Among them, RxReqTime-TxReqTime is the latest obtained timestamp after obtaining TxSyncTime-RxSyncTime.
为了减小网络传输延迟的波动对后续计算的影响，可以使用均值滤波的方法，即，对最近多次计算出的OneWayDelay求平均值，这个平均值作为SYNC从主机传播到从机时的网络传输延迟的值。实验表明，将最近16次OneWayDelay求得的平均值作为SYNC从主机传播到从机时的网络传输延迟的值比较理想。In order to reduce the impact of network transmission delay fluctuations on subsequent calculations, the mean filtering method can be used, that is, to average the recently calculated OneWayDelay multiple times, and this average value is used as the network transmission when SYNC propagates from the master to the slave The value of the delay. Experiments show that it is ideal to use the average value obtained by the last 16 OneWayDelays as the value of the network transmission delay when SYNC propagates from the master to the slave.
控制器314再利用获得的TxSyncTime-RxSyncTime时间戳对及SYNC从主机传播到从机时的网络传输延迟的值计算主机的频率补偿时钟315与从机的频率补偿时钟315之间计数值的偏差。The controller 314 then uses the obtained TxSyncTime-RxSyncTime time stamp pair and the value of the network transmission delay when SYNC propagates from the master to the slave to calculate the count value deviation between the frequency compensation clock 315 of the master and the frequency compensation clock 315 of the slave.
可以按如下公式即可计算出主机的频率补偿时钟315与从机的频率补偿时钟315之间计数值的偏差Offset：The offset of the count value offset between the frequency compensation clock 315 of the master and the frequency compensation clock 315 of the slave can be calculated according to the following formula:
Offset＝TxSyncTime-RxSyncTime+OneWayDelay，Offset=TxSyncTime-RxSyncTime+OneWayDelay,
其中，当主机时钟比从机时钟快时，Offset大于零，主机时钟比从机时钟慢时，Offset小于零。Wherein, when the master clock is faster than the slave clock, the Offset is greater than zero, and when the master clock is slower than the slave clock, the Offset is less than zero.
控制器314根据主机的频率补偿时钟315与从机的频率补偿时钟315之间计数值的偏差计算频率补偿值。The controller 314 calculates the frequency compensation value according to the deviation of the count value between the frequency compensation clock 315 of the master and the frequency compensation clock 315 of the slave.
频率补偿时钟315接受新的频率补偿值，以使主机的频率补偿时钟315与从机的频率补偿时钟315之间计数值的偏差在一定时间内逐渐变为零。The frequency compensation clock 315 accepts a new frequency compensation value, so that the deviation of the count value between the frequency compensation clock 315 of the master and the frequency compensation clock 315 of the slave gradually becomes zero within a certain period of time.
频率补偿时钟315的结构如图4所示，包括一个p位时钟计数器(p-bitClock Counter)、一个q位累加器(q-bit Accumulator)和一个r位加数寄存器(r-bit Addend Register)组成，Tx/Rx Signals表示发送/接收信号，MessageDetection表示信息检测，Time Stamping Logic表示获取时间戳的逻辑，Frequency Compensaion Value表示频率补偿值，Frequency CompensationClock表示频率补偿时钟。r位加数寄存器中保存的数值即是当前正在使用的频率补偿值。每隔一个时钟周期，频率补偿值被加到q位累加器中一次，如果q位累加器溢出，则p位时钟计数器的值增加一个固定值，这个值就是时钟的分辨率，如果q位累加器没有溢出，则p位时钟计数器保持原值。因此，p位时钟计数器的计数速度是由晶振频率和频率补偿值共同决定的，对频率补 偿值进行微调即可校正主机与从机晶振频率之间的微小偏差。The structure of the frequency compensation clock 315 is as shown in Figure 4, including a p-bit clock counter (p-bitClock Counter), a q-bit accumulator (q-bit Accumulator) and an r-bit addend register (r-bit Addend Register) Composition, Tx/Rx Signals indicates sending/receiving signals, MessageDetection indicates information detection, Time Stamping Logic indicates the logic of obtaining time stamps, Frequency Compensaion Value indicates frequency compensation value, and Frequency CompensationClock indicates frequency compensation clock. The value saved in the r-bit addend register is the frequency compensation value currently in use. Every other clock cycle, the frequency compensation value is added to the q-bit accumulator once. If the q-bit accumulator overflows, the value of the p-bit clock counter will increase by a fixed value. This value is the resolution of the clock. If the q-bit accumulator If the register does not overflow, the p-bit clock counter maintains its original value. Therefore, the counting speed of the p-bit clock counter is determined by the frequency of the crystal oscillator and the frequency compensation value. Fine-tuning the frequency compensation value can correct the slight deviation between the master and slave crystal oscillator frequencies.
假设上一次同步时计算出的偏差为Offset0，当前一次同步时计算出的偏差为Offset1，则可以预测，下一次同步时计算出的偏差将是Offset2＝2*Offset1 -Offset0。因此，应当调节频率补偿值，使得从机时钟在当前这个同步周期内时钟计数器的值的增加量比上一个同步周期多Offset2，于是，下一次同步时计算出的偏差将是零。Assuming that the offset calculated in the last synchronization is Offset0 and the offset calculated in the previous synchronization is Offset1 , it can be predicted that the offset calculated in the next synchronization will be Offset2 =2*Offset1 -Offset0 . Therefore, the frequency compensation value should be adjusted so that the increment of the clock counter value of the slave clock in the current synchronization period is Offset2 more than the previous synchronization period, so the calculated deviation in the next synchronization will be zero.
在获得了Offset的条件下，计算出新的频率补偿值，实现对频率补偿时钟计数速度的微量调节，使得主机的频率补偿时钟315的计数速度与从机的频率补偿时钟315的计数速度一致，消除计数值的偏差，达到时钟同步的目的。Under the condition that the Offset is obtained, a new frequency compensation value is calculated to realize micro-adjustment of the counting speed of the frequency compensation clock, so that the counting speed of the frequency compensation clock 315 of the master is consistent with the counting speed of the frequency compensation clock 315 of the slave, Eliminate the deviation of the count value to achieve the purpose of clock synchronization.
需要说明的是，SYNC、FOLLOW_UP、DELAY_REQ及DELAY_RESP都是UDP(User Datagram Ptorocol，用户数据报文协议)帧，在UDP帧的字段payload中包含着PTP帧的序号和时间戳，其中，FOLLOW_UP和DELAY_RESP中的时间戳的数值是有意义的，而SYNC和DELAY_REQ中的时间戳的数值是可以任意填写的。It should be noted that SYNC, FOLLOW_UP, DELAY_REQ, and DELAY_RESP are all UDP (User Datagram Ptorocol, User Datagram Protocol) frames, and the field payload of the UDP frame contains the sequence number and timestamp of the PTP frame, where FOLLOW_UP and DELAY_RESP The value of the timestamp in is meaningful, and the value of the timestamp in SYNC and DELAY_REQ can be filled in arbitrarily.
无论是主机的发送捕获器311还是从机的发送捕获器311识别出正在发出的数据帧的前导码(preamble)之后的帧起始标志位(Start Frame Delimiter)时，都可以记录这个帧的本地发送时间戳。如果主机的发送捕获器311识别出这个帧为SYNC，则保存这个时间戳供主机的CPU读取；如果从机的发送捕获器311识别出这个帧为DELAY_REQ，则保存这个时间戳用于计算频率补偿时钟315的频率补偿值。Whether it is the sending catcher 311 of the master or the sending catcher 311 of the slave recognizes the frame start flag (Start Frame Delimiter) after the preamble (preamble) of the data frame being sent out, the local frame of this frame can be recorded. Send timestamp. If the sending capturer 311 of the master recognizes that this frame is SYNC, then save this time stamp for the CPU of the master to read; if the sending catcher 311 of the slave recognizes that this frame is DELAY_REQ, then save this time stamp for calculating the frequency The frequency compensation value of the compensation clock 315 .
无论是主机的接收捕获器312还是从机的接收捕获器312识别出正在接收的数据帧的前导码(preamble)之后的帧起始标志位(Start Frame Delimiter)时，都可以记录这个帧的本地接收时间戳。如果主机的接收捕获器312识别出这个帧为DELAY_REQ，则保存这个时间戳供主机的CPU读取；如果从机的接收捕获器312识别出这个帧为SYNC，则保存这个时间戳用于计算频率补偿时钟315的频率补偿值。Whether it is the receiving capturer 312 of the master or the receiving capturer 312 of the slave recognizes the frame start flag (Start Frame Delimiter) after the preamble (preamble) of the data frame being received, the local frame of this frame can be recorded. Receive timestamp. If the reception capture device 312 of the master machine recognizes that this frame is DELAY_REQ, then save this time stamp for the CPU of the master machine to read; if the reception capture device 312 of the slave machine recognizes that this frame is SYNC, then save this time stamp for calculating the frequency The frequency compensation value of the compensation clock 315 .
本发明还提供了一种实现时钟同步的系统。系统的结构如图5所示，包括：CPU52，用于处理数据包；介质访问控制器(MAC Controller)53，用于缓存数据包；物理层设备收发器(PHY Transceiver)54，用于将数据包进行信 号转换；FPGA(Field Programmable Gate Array，现场可编程门阵列)51，用于监听介质访问控制器53与物理层设备收发器54之间的所有信号，FPGA51可进一步包括图3所示的时钟同步装置中的各个实体。其中，介质访问控制器53根据CPU52的命令将缓存的数据包发送到物理层设备收发器54，和/或，将缓存的数据包发送到CPU52。The invention also provides a system for realizing clock synchronization. The structure of the system is as shown in Figure 5, including: CPU52, for processing data packets; Media Access Controller (MAC Controller) 53, for buffering data packets; physical layer device transceiver (PHY Transceiver) 54, for data Packet carries out signal conversion; FPGA (Field Programmable Gate Array, Field Programmable Gate Array) 51, is used for monitoring all signals between medium access controller 53 and physical layer device transceiver 54, and FPGA51 can further include as shown in Fig. 3 The clock synchronizes the various entities in the device. Wherein, the media access controller 53 sends the buffered data packet to the physical layer device transceiver 54 according to the command of the CPU52, and/or, sends the buffered data packet to the CPU52.
FPGA51通过总线与CPU52交互数据和控制信息。CPU52通过总线分别连接到介质访问控制器53和FPGA51。CPU52、介质访问控制器53、物理层设备收发器54共同构成一个完整的数据通讯通道，实现时钟同步的系统与其它设备的交互信息全部由此通道传送，包括PTP帧。介质访问控制器53实现以太网协议中MAC子层的功能，通过MII(Media Independent Interface，介质独立接口)与物理层设备收发器54相连，还通过总线与CPU52相连，同CPU52交互发送、接收的数据及控制信息。物理层设备收发器54实现通讯线路上的模拟信号和电路板上数字信号之间的转换，一方面通过网络变压器、RJ-45(一种双绞线以太网接口)连接到交换设备，如HUB(集线器)、专用SWITCH(交换机)等，另一方面通过MII接口(IEEE802.3-1998中定义)连接到介质访问控制器53。FPGA51 exchanges data and control information with CPU52 through the bus. The CPU 52 is connected to the media access controller 53 and the FPGA 51 via a bus, respectively. The CPU 52, the media access controller 53, and the physical layer device transceiver 54 together form a complete data communication channel, and all interactive information between the clock synchronization system and other devices is transmitted through this channel, including PTP frames. The media access controller 53 realizes the function of the MAC sublayer in the Ethernet protocol, is connected with the physical layer device transceiver 54 by MII (Media Independent Interface, medium independent interface), is also connected with the CPU52 by the bus, and interacts with the CPU52 to send and receive Data and Control Information. The physical layer device transceiver 54 realizes the conversion between the analog signal on the communication line and the digital signal on the circuit board. On the one hand, it is connected to the switching device, such as HUB, through a network transformer and RJ-45 (a kind of twisted pair Ethernet interface). (hub), dedicated SWITCH (switch), etc., on the other hand, are connected to the media access controller 53 through the MII interface (defined in IEEE802.3-1998).
需要说明的是，无论是主机还是从机，都可具有图5所示的时钟同步系统。It should be noted that both the master and the slave can have the clock synchronization system shown in FIG. 5 .
现在对图5所示的时钟同步系统的运行原理进行说明。The operating principle of the clock synchronization system shown in Fig. 5 will now be described.
主机CPU52每隔一定时间主动发出SYNC，主机FPGA51在介质访问控制器53与物理层设备收发器54之间探测到SYNC的发出，记录这个SYNC的序号TxSyncSeq和本地发送时间戳TxSyncTime。SYNC到达从机时，从机FPGA51在介质访问控制器53与物理层设备收发器54之间探测到SYNC的到来，记录这个SYNC的序号RxSyncSeq和本地接收时间戳RxSyncTime。The host CPU 52 actively sends SYNC at regular intervals, and the host FPGA 51 detects the sending of SYNC between the media access controller 53 and the physical layer device transceiver 54, and records the sequence number TxSyncSeq of the SYNC and the local transmission time stamp TxSyncTime. When SYNC arrives at the slave, the slave FPGA 51 detects the arrival of SYNC between the media access controller 53 and the physical layer device transceiver 54, and records the sequence number RxSyncSeq of this SYNC and the local receiving time stamp RxSyncTime.
主机发出SYNC后，主机CPU52立即从FPGA51中取出TxSyncSeq和TxSyncTime，封装成一个新的数据包FOLLOW_UP并发出，其中TxSyncSeq作为序号，TxSyncTime作为普通数据。FOLLOW_UP到达从机时，从机FPGA51在介质访问控制器53与物理层设备收发器54之间探测到FOLLOW_UP的到来，记录这个FOLLOW_UP的序号RxFollowSeq和帧中包含的数据TxSyncTime。如果RxSyncSeq和RxFollowSeq相同，则获得了一个 TxSyncTime-RxSyncTime时间戳对。After the host sends the SYNC, the host CPU52 immediately takes out TxSyncSeq and TxSyncTime from the FPGA51, encapsulates them into a new data packet FOLLOW_UP and sends it out, wherein TxSyncSeq is used as a serial number, and TxSyncTime is used as ordinary data. When FOLLOW_UP arrives at the slave, the slave FPGA 51 detects the arrival of FOLLOW_UP between the medium access controller 53 and the physical layer device transceiver 54, and records the serial number RxFollowSeq of the FOLLOW_UP and the data TxSyncTime contained in the frame. If RxSyncSeq and RxFollowSeq are the same, a TxSyncTime-RxSyncTime timestamp pair is obtained.
从机接收到SYNC或FOLLOW_UP时，就获得了主机的物理地址。接收到FOLLOW_UP之后，从机CPU52主动向主机发出DELAY_REQ，从机FPGA51在介质访问控制器53与物理层设备收发器54之间探测到DELAY_REQ的发出，记录这个DELAY_REQ的序号TxReqSeq和本地发送时间戳TxReqTime。DELAY_REQ到达主机时，主机FPGA51在介质访问控制器53与物理层设备收发器54之间探测到DELAY_REQ的到来，记录这个DELAY_REQ的源物理地址SlavePhyAddr、序号RxReqSeq和本地接收时间戳RxReqTime。需要说明的是，从机CPU52在接收到FOLLOW_UP之后，立即主动向主机发出DELAY_REQ是比较合适的，当然，从机可以在获得主机的物理地址后的任意时间主动向主机发出DELAY_REQ。When the slave receives SYNC or FOLLOW_UP, it obtains the physical address of the master. After receiving FOLLOW_UP, the slave CPU52 actively sends a DELAY_REQ to the master, and the slave FPGA51 detects the sending of the DELAY_REQ between the media access controller 53 and the physical layer device transceiver 54, and records the serial number TxReqSeq of the DELAY_REQ and the local sending time stamp TxReqTime . When the DELAY_REQ arrives at the host, the host FPGA 51 detects the arrival of the DELAY_REQ between the media access controller 53 and the physical layer device transceiver 54, and records the source physical address SlavePhyAddr, serial number RxReqSeq, and local reception timestamp RxReqTime of the DELAY_REQ. It should be noted that it is appropriate for the slave CPU52 to actively send DELAY_REQ to the master immediately after receiving FOLLOW_UP. Of course, the slave can send DELAY_REQ to the master at any time after obtaining the physical address of the master.
由于可能存在多个从机同时向主机发出DELAY_REQ而主机不能迅速处理完所有DELAY_REQ的情况，所以主机可以使用队列来保存SlavePhyAddr、RxReqSeq和RxReq_Time，按照FIFO(First-In First-Out，先进先出)原则依序处理所有的DELAY_REQ。主机的FPGA51在探测到一个新的数据帧到来时，备份当前队列的写指针，随着数据的不断接收，将接收数据流中对应于DELAY_REQ中的SlavePhyAddr、RxReqSeq和RxReqTime位置的数据存入队列，并将RxReqTime位置的数据替换为主机记录的这个帧的本地接收时间戳。当这个帧接收完毕的同时，主机的FPGA51就已经识别出它是否为DELAY_REQ，如果不是，则将队列的写指针恢复为刚开始接收这个帧备份的那个值，如果是，则不做任何操作。为了防止在意外情况下，主机的CPU52对接收帧的解析结果不同于FPGA51对同一个接收帧的解析结果，导致上一个同步周期的RxReqTime等信息留在队列中未被读取而造成不良影响，主机的FPGA51每次探测到SYNC发出时，主机都将队列的读指针设定为当前的写指针的值。Since there may be multiple slaves sending DELAY_REQ to the host at the same time and the host cannot quickly process all DELAY_REQs, the host can use the queue to save SlavePhyAddr, RxReqSeq and RxReq_Time, according to FIFO (First-In First-Out, first-in-first-out) The principle is to process all DELAY_REQs sequentially. When the FPGA51 of the host computer detects the arrival of a new data frame, it backs up the write pointer of the current queue, and as the data is continuously received, it stores the data corresponding to the positions of SlavePhyAddr, RxReqSeq and RxReqTime in the received data stream into the queue, And replace the data at the RxReqTime position with the local reception timestamp of this frame recorded by the host. When this frame has been received completely, the FPGA51 of the main frame has just identified whether it is DELAY_REQ, if not, then the write pointer of the queue is restored to the value that just started receiving this frame backup, if so, then no operation is performed. In order to prevent that under unexpected circumstances, the analysis result of the received frame by the CPU52 of the host is different from the analysis result of the same received frame by the FPGA51, causing the information such as RxReqTime of the previous synchronization cycle to remain in the queue without being read and cause adverse effects, Every time the FPGA51 of the host computer detects that SYNC is sent out, the host computer sets the read pointer of the queue as the value of the current write pointer.
主机收到从机发来的DELAY_REQ之后，要立即回复一个DELAY_RESP。主机CPU52从FPGA51中取出SlavePhyAddr、RxReqSeq、RxReqTime，封装一个新的DELAY_RESP并发出，其中，SlavePhyAddr作为目标物理地址，RxReqSeq作为序号，RxReqTime作为普通数据。DELAY_RESP到达从机时，从机FPGA51在介质访问控制器53与物理层设备收发器54之间探测到 DELAY_RESP的到来，记录这个DELAY_RESP的序号RxRespSeq和帧中包含的数据RxReqTime。如果TxReqSeq和RxRespSeq相同，则获得了一个TxReqTime-RxReqTime时间戳对。After the master receives the DELAY_REQ from the slave, it must reply a DELAY_RESP immediately. The host CPU52 takes out SlavePhyAddr, RxReqSeq, and RxReqTime from the FPGA51, encapsulates a new DELAY_RESP and sends it out, wherein SlavePhyAddr is used as the target physical address, RxReqSeq is used as the serial number, and RxReqTime is used as common data. When DELAY_RESP arrives at slave, slave FPGA51 detects the arrival of DELAY_RESP between media access controller 53 and physical layer device transceiver 54, records the sequence number RxRespSeq of this DELAY_RESP and the data RxReqTime contained in the frame. If TxReqSeq and RxRespSeq are the same, a TxReqTime-RxReqTime timestamp pair is obtained.
需要说明的是，FPGA51是被动设备，所有PTP帧都是CPU52命令介质访问控制器53发出的，FPGA51的工作是监听和解析，CPU52无法直接通知FPGA51它在发送或者接收PTP帧。It should be noted that FPGA51 is a passive device, and all PTP frames are issued by CPU52 instructing the media access controller 53. The work of FPGA51 is to monitor and analyze, and CPU52 cannot directly notify FPGA51 that it is sending or receiving PTP frames.
对于主机，发送FOLLOW_UP和DELAY_RESP时，FPGA51不作任何操作，事实上，FPGA51将这两种帧当作普通的数据帧来处理，并不能识别出这两种帧。收到DELAY_REQ时，CPU52从介质访问控制器53接收并解析出DELAY_REQ后，从FPGA51中取出SlavePhyAddr、RxReqSeq和RxReqTime，并封装DELAY_RESP发出。For the host, FPGA51 does not perform any operation when sending FOLLOW_UP and DELAY_RESP. In fact, FPGA51 treats these two frames as ordinary data frames and cannot recognize these two frames. When receiving DELAY_REQ, CPU52 receives and parses DELAY_REQ from media access controller 53, takes out SlavePhyAddr, RxReqSeq and RxReqTime from FPGA51, and encapsulates DELAY_RESP to send out.
对于从机，收到SYNC时，CPU52从介质访问控制器53接收并解析出SYNC后，直接将它丢弃，不作任何附加的操作。收到FOLLOW_UP后，从机CPU52立即主动发出DELAY_REQ，并将FOLLOW_UP丢弃。收到DELAY_RESP时，CPU52也是直接将它丢弃。For the slave, when receiving the SYNC, the CPU 52 directly discards the SYNC after receiving and parsing the SYNC from the media access controller 53 without any additional operation. After receiving FOLLOW_UP, slave CPU52 sends DELAY_REQ actively immediately, and discards FOLLOW_UP. When receiving DELAY_RESP, CPU52 also discards it directly.
从机获得TxSyncTime-RxSyncTime时间戳对及TxReqTime-RxReqTime时间戳对后，从机的FPGA51这两个时间戳对计算SYNC从主机传播到从机时的网络传输延迟。After the slave machine obtains the TxSyncTime-RxSyncTime time stamp pair and the TxReqTime-RxReqTime time stamp pair, the FPGA51 of the slave machine calculates the network transmission delay when SYNC propagates from the master machine to the slave machine with these two time stamp pairs.
可以按如下公式即可计算出网络传输延迟OneWayDelay的值：The value of the network transmission delay OneWayDelay can be calculated according to the following formula:
OneWayDelay＝(RxReqTime-TxReqTime)/2-(TxSyncTime-RxSyncTime)/2，OneWayDelay=(RxReqTime-TxReqTime)/2-(TxSyncTime-RxSyncTime)/2,
其中，RxReqTime-TxReqTime是获得TxSyncTime-RxSyncTime后最近一次获得的时间戳。Among them, RxReqTime-TxReqTime is the latest obtained timestamp after obtaining TxSyncTime-RxSyncTime.
为了减小网络传输延迟的波动对后续计算的影响，可以使用均值滤波的方法，即，对最近多次计算出的OneWayDelay求平均值，这个平均值作为SYNC从主机传播到从机时的网络传输延迟的值。实验表明，将最近16次OneWayDelay求得的平均值作为SYNC从主机传播到从机时的网络传输延迟的值比较理想。In order to reduce the impact of network transmission delay fluctuations on subsequent calculations, the mean filtering method can be used, that is, to average the recently calculated OneWayDelay multiple times, and this average value is used as the network transmission when SYNC propagates from the master to the slave The value of the delay. Experiments show that it is ideal to use the average value obtained by the last 16 OneWayDelays as the value of the network transmission delay when SYNC propagates from the master to the slave.
从机的FPGA51再利用获得的TxSyncTime-RxSyncTime时间戳对及SYNC从主机传播到从机时的网络传输延迟的值计算主机的时钟计数器与从 机的时钟计数器之间计数值的偏差。The FPGA51 of the slave uses the obtained TxSyncTime-RxSyncTime timestamp pair and the value of the network transmission delay when SYNC propagates from the master to the slave to calculate the deviation of the count value between the clock counter of the master and the clock counter of the slave.
可以按如下公式即可计算出主机的时钟计数器与从机的时钟计数器之间计数值的偏差Offset：The offset of the count value offset between the clock counter of the master and the clock counter of the slave can be calculated according to the following formula:
Offset＝TxSyncTime-RxSyncTime+OneWayDelay，Offset=TxSyncTime-RxSyncTime+OneWayDelay,
其中，当主机时钟比从机时钟快时，Offset大于零，主机时钟比从机时钟慢时，Offset小于零。Wherein, when the master clock is faster than the slave clock, the Offset is greater than zero, and when the master clock is slower than the slave clock, the Offset is less than zero.
从机的FPGA51根据主机的时钟计数器与从机的时钟计数器之间计数值的偏差计算频率补偿值。The FPGA51 of the slave calculates the frequency compensation value according to the deviation of the count value between the clock counter of the master and the clock counter of the slave.
时钟计数器接受新的频率补偿值，以使主机的时钟计数器与从机的时钟计数器之间计数值的偏差在一定时间内逐渐变为零。The clock counter accepts a new frequency compensation value, so that the deviation of the count value between the clock counter of the master and the clock counter of the slave becomes zero gradually within a certain period of time.
假设上一次同步时计算出的偏差为Offset0，当前一次同步时计算出的偏差为Offset1，则可以预测，下一次同步时计算出的偏差将是Offset2＝2*Offset1 -Offset0。因此，应当调节频率补偿值，使得从机时钟在当前这个同步周期内时钟计数器的值的增加量比上一个同步周期多Offset2，于是，下一次同步时计算出的偏差将是零。Assuming that the offset calculated in the last synchronization is Offset0 and the offset calculated in the previous synchronization is Offset1 , it can be predicted that the offset calculated in the next synchronization will be Offset2 =2*Offset1 -Offset0 . Therefore, the frequency compensation value should be adjusted so that the increment of the clock counter value of the slave clock in the current synchronization period is Offset2 more than the previous synchronization period, so the calculated deviation in the next synchronization will be zero.
在获得了Offset的条件下，计算出新的频率补偿值，实现对频率补偿时钟计数速度的微量调节，使得主机的时钟计数器的计数速度与从机的时钟计数器的计数速度一致，消除计数值的偏差，达到时钟同步的目的。Under the condition that the Offset is obtained, a new frequency compensation value is calculated, and the micro-adjustment of the counting speed of the frequency compensation clock is realized, so that the counting speed of the clock counter of the master is consistent with the counting speed of the clock counter of the slave, and the discrepancy of the count value is eliminated. Deviation, to achieve the purpose of clock synchronization.
需要说明的是，SYNC、FOLLOW_UP、DELAY_REQ及DELAY_RESP都是UDP(User Datagram Ptorocol，用户数据报文协议)帧，在UDP帧的字段payload中包含着PTP帧的序号和时间戳，其中，FOLLOW_UP和DELAY_RESP中的时间戳的数值是有意义的，而SYNC和DELAY_REQ中的时间戳的数值是可以任意填写的。It should be noted that SYNC, FOLLOW_UP, DELAY_REQ, and DELAY_RESP are all UDP (User Datagram Ptorocol, User Datagram Protocol) frames, and the field payload of the UDP frame contains the sequence number and timestamp of the PTP frame, where FOLLOW_UP and DELAY_RESP The value of the timestamp in is meaningful, and the value of the timestamp in SYNC and DELAY_REQ can be filled in arbitrarily.
无论是主机的FPGA51还是从机的FPGA51识别出正在发出的数据帧的前导码(preamble)之后的帧起始标志位(Start Frame Delimiter)时，都可以记录这个帧的本地发送时间戳。如果主机的FPGA51识别出这个帧为SYNC，则保存这个时间戳供主机的CPU读取；如果从机的FPGA51识别出这个帧为DELAY_REQ，则保存这个时间戳用于计算频率补偿时钟的频率补偿值。When the FPGA51 of the master or the FPGA51 of the slave recognizes the frame start flag (Start Frame Delimiter) after the preamble of the data frame being sent, the local transmission time stamp of this frame can be recorded. If the FPGA51 of the master recognizes that this frame is SYNC, then save this time stamp for the CPU of the master to read; if the FPGA51 of the slave recognizes that this frame is DELAY_REQ, then save this time stamp for calculating the frequency compensation value of the frequency compensation clock .
无论是主机的FPGA51还是从机的FPGA51识别出正在接收的数据帧的前导码(preamble)之后的帧起始标志位(Start Frame Delimiter)时，都可以 记录这个帧的本地接收时间戳。如果主机的FPGA51识别出这个帧为DELAY_REQ，则保存这个时间戳供主机的CPU读取；如果从机的FPGA51识别出这个帧为SYNC，则保存这个时间戳用于计算频率补偿时钟的频率补偿值。When the FPGA51 of the master or the FPGA51 of the slave recognizes the frame start flag (Start Frame Delimiter) after the preamble of the data frame being received, the local reception time stamp of this frame can be recorded. If the FPGA51 of the master recognizes that this frame is DELAY_REQ, then save this time stamp for the CPU of the master to read; if the FPGA51 of the slave recognizes that this frame is SYNC, then save this time stamp for calculating the frequency compensation value of the frequency compensation clock .
本发明还提供了一种分布式系统，所述分布式系统包括至少一个主机及从机，所述主机及从机分别包括：CPU，用于处理数据包；介质访问控制器，用于缓存数据包；物理层设备收发器，用于将数据包进行信号转换；所述从机还包括：时钟同步器，用于在所述介质访问控制器与所述物理层设备收发器之间获取主机发出的第一数据包的本地接收时间戳及主机发出第一数据包的本地发送时间戳，根据所述第一数据包的本地接收时间戳及本地发送时间戳计算时钟计数器之间计数值的偏差，以及对所述偏差进行校正。The present invention also provides a distributed system, the distributed system includes at least one host and slave, the host and slave respectively include: CPU, used to process data packets; media access controller, used to cache data packet; a physical layer device transceiver, used to perform signal conversion on the data packet; the slave also includes: a clock synchronizer, used to acquire the host computer between the media access controller and the physical layer device transceiver The local receiving time stamp of the first data packet and the local sending time stamp of the first data packet sent by the host, and calculate the deviation of the count value between the clock counters according to the local receiving time stamp and the local sending time stamp of the first data packet, and correcting for the deviation.
所述主机还包括：时钟同步器，用于监听介质访问控制器与物理层设备收发器之间的所有信号。The host also includes: a clock synchronizer, configured to monitor all signals between the media access controller and the transceiver of the physical layer device.
分布式系统中的主机及从机均可包括图5所示的时钟同步系统，时钟同步系统还可进一步包括图3所示的时钟同步装置，分布式系统的运行原理可以参照上述关于图5及图3涉及到的工作原理的说明，这里不再赘述。Both the master and the slave in the distributed system can include the clock synchronization system shown in Figure 5, and the clock synchronization system can further include the clock synchronization device shown in Figure 3, the operating principle of the distributed system can refer to the above-mentioned about Figure 5 and The description of the working principle involved in FIG. 3 will not be repeated here.
需要说明的是，在上述实施方式中，频率补偿值的计算都是在FPGA中实现，但如果对FPGA中的CPU接口逻辑稍做修改，就可以将频率补偿值的计算转移到CPU中实现，这种情况下，CPU将计算得到的频率补偿值写入FPGA供时钟计数器使用即可。It should be noted that in the above embodiments, the calculation of the frequency compensation value is implemented in the FPGA, but if the CPU interface logic in the FPGA is slightly modified, the calculation of the frequency compensation value can be transferred to the CPU for implementation. In this case, the CPU writes the calculated frequency compensation value into the FPGA for use by the clock counter.
现在对本发明如何防止数据包的丢失和重复对时钟同步的影响再进行说明。Now, how the present invention prevents the loss and repetition of data packets from affecting the clock synchronization will be described again.
由于SYNC-FOLLOW_UP数据包对及DELAY_REQ-DELAY_RESP数据包对分别具有相同的序号，而CPU在每次发出新的SYNC-FOLLOW_UP对和DELAY_REQ-DELAY_RESP对时都会使用不同的序号，所以，如果丢失了SYNC，则随后的FOLLOW_UP的序号因和前一个有效的SYNC的序号不同而变成无效的FOLLOW_UP，如果丢失了FOLLOW_UP，下一个有效的SYNC会重置即将接收的FOLLOW_UP的序号，DELAY_REQ-DELAY_RESP对的情况亦相同。Since the SYNC-FOLLOW_UP data packet pair and the DELAY_REQ-DELAY_RESP data packet pair have the same sequence number respectively, and the CPU will use a different sequence number each time a new SYNC-FOLLOW_UP pair and DELAY_REQ-DELAY_RESP pair are issued, so if the SYNC , the serial number of subsequent FOLLOW_UP becomes invalid FOLLOW_UP because it is different from the serial number of the previous valid SYNC. If FOLLOW_UP is lost, the next valid SYNC will reset the serial number of FOLLOW_UP to be received. In the case of DELAY_REQ-DELAY_RESP pair Also the same.
从机的时钟计数器采用的是频率补偿时钟，系统正常运行时，从机时钟 计数器的计数速度和主机时钟计数器的计数速度几乎是相同的，所以偶尔丢失几个SYNC-FOLLOW_UP对，即偶尔几次没有同步，对同步精度的影响是非常小的。丢失DELAY_REQ-DELAY_RESP对的情况对同步精度的影响几乎为零，因为系统正常运行时，网络传输延迟是比较稳定的，只有一些正态分布的随机误差，偶尔一次没有更新网络传输延迟，旧的数值仍然是准确的。The clock counter of the slave machine uses a frequency compensation clock. When the system is running normally, the counting speed of the clock counter of the slave machine is almost the same as that of the clock counter of the master machine, so occasionally a few SYNC-FOLLOW_UP pairs are lost, that is, a few times Without synchronization, the impact on synchronization accuracy is very small. The loss of the DELAY_REQ-DELAY_RESP pair has almost zero impact on the synchronization accuracy, because when the system is running normally, the network transmission delay is relatively stable, and there are only some random errors in the normal distribution. Occasionally, the network transmission delay is not updated once, and the old value is still accurate.
如果网络上同一个PTP帧连续出现了两次或多次，就有可能导致严重的后果，所以要采取措施来应对这种情况的发生。在SYNC-FOLLOW_UP对的发送接收过程中，从机接收到SYNC时，启动一个定时器，如果在定时器超时之前相同的SYNC又被接收到，则这个重复的SYNC将被视为无效。在启动定时器的同时，还将一个标志位置位，等到接收到相应的FOLLOW_UP时，再将标志位复位，如果相同的FOLLOW_UP又一次被接收到，由于标志位为零，表示相同的FOLLOW_UP已经被接收到了，则这个后来的FOLLOW_UP将被视为无效。在DELAY_REQ-DELAY_RESP对的发送接收过程中，从机发出DELAY_REQ时，将一个标志位置位，等到接收到相应的DELAY_RESP时，再将标志位复位，如果相同的DELAY_RESP又被接收到，由于标志位为零，表示相同的DELAY_RESP已经被接收到了，则这个重复的DELAY_RESP将被视为无效。主机收到重复到来的DELAY_REQ时，将这个DELAY_REQ当作正常的DELAY_REQ来处理，即回复一个DELAY_RESP，这个DELAY_RESP相当于一个重复的DELAY_RESP，从机能够正确的处理。If the same PTP frame appears twice or more consecutively on the network, it may cause serious consequences, so measures should be taken to deal with this situation. During the sending and receiving process of the SYNC-FOLLOW_UP pair, when the slave receives SYNC, a timer is started. If the same SYNC is received again before the timer expires, the repeated SYNC will be considered invalid. When the timer is started, a flag will be set. When the corresponding FOLLOW_UP is received, the flag will be reset. If the same FOLLOW_UP is received again, since the flag is zero, it means that the same FOLLOW_UP has been received. received, this subsequent FOLLOW_UP will be considered invalid. During the sending and receiving process of DELAY_REQ-DELAY_RESP pair, when the slave sends DELAY_REQ, it will set a flag bit, and then reset the flag bit when it receives the corresponding DELAY_RESP. If the same DELAY_RESP is received again, because the flag bit is Zero, indicating that the same DELAY_RESP has already been received, then this duplicate DELAY_RESP will be considered invalid. When the master receives the repeated DELAY_REQ, it treats the DELAY_REQ as a normal DELAY_REQ, that is, it replies with a DELAY_RESP. This DELAY_RESP is equivalent to a repeated DELAY_RESP, and the slave can handle it correctly.
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。The above is only a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications should also be It is regarded as the protection scope of the present invention.
Claims (13)
Translated fromChinesePriority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101409425ACN1960242B (en) | 2006-10-17 | 2006-10-17 | Method, device, system for implementing clock synchronization, and distribution system |
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