CN1908885A - Static memorizer interface device and data transmitting method thereof - Google Patents
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Abstract
Translated fromChinese
Description
Translated fromChinese技术领域technical field
本发明涉及电子技术领域中的数字ASIC(专用集成电路)设计与SOC(System-On-Chip，片上系统)领域，尤其涉及一种静态存储器接口装置及其数据传输方法。The invention relates to digital ASIC (application-specific integrated circuit) design and SOC (System-On-Chip, system on chip) field in the field of electronic technology, in particular to a static memory interface device and a data transmission method thereof.
背景技术Background technique
AHB总线(Advanced High-performance bus，先进高性能总线)是AMBA(Advanced Microcontroller Bus Architecture，先进微处理器总线架构)规范中的一种高效的基于流水线架构的总线，用于连接高性能系统模块。它支持single(单个数据传送)方式及burst(突发数据传送)方式，AHB总线的所有时序都以单一时钟的周期为基准。AHB bus (Advanced High-performance bus, advanced high-performance bus) is an efficient bus based on pipeline architecture in the AMBA (Advanced Microcontroller Bus Architecture, advanced microprocessor bus architecture) specification, which is used to connect high-performance system modules. It supports single (single data transmission) mode and burst (burst data transmission) mode, and all timings of the AHB bus are based on the cycle of a single clock.
在大规模集成电路中为了利用SRAM(Static Random AccessMemory，静态存储器)可以被高速访问的特点，往往会在芯片内部集成静态存储器。但是对静态存储器的访问通常只支持单个数据访问方式，不支持突发数据访问方式。因此类似AHB的流水线总线若仅以单个数据访问方式对静态存储器进行操作，会降低总线的访问效率，影响系统的整体性能。这种总线利用率低的现象在片内总线访问片外静态存储器时也同样存在。In large-scale integrated circuits, in order to take advantage of the high-speed access characteristics of SRAM (Static Random Access Memory, static memory), static memory is often integrated inside the chip. However, the access to the static memory usually only supports a single data access mode, and does not support a burst data access mode. Therefore, if a pipeline bus like AHB only operates on static memory in a single data access mode, it will reduce the access efficiency of the bus and affect the overall performance of the system. This phenomenon of low bus utilization also exists when the on-chip bus accesses the off-chip static memory.
现有技术中一种访问静态存储器的方法为：采用AHB的单个数据访问方式访问静态存储器。在该方法中，静态存储器的写时序示意图如图1所示，在进行写操作时，写使能、片选、写地址、写数据对齐，数据在一个时钟内写入相应地址；静态存储器的读时序示意图如图2所示，在进行读操作时，读使能、片选、读地址对齐，相应地址的数据延迟一个时钟周期后送出，因此SRAM接口延迟一个时钟周期后才能读到正确数据。A method for accessing the static memory in the prior art is: accessing the static memory in a single data access mode of the AHB. In this method, the write timing diagram of the static memory is shown in Figure 1. During the write operation, the write enable, chip select, write address, and write data are aligned, and the data is written to the corresponding address within one clock; the static memory The read timing diagram is shown in Figure 2. During the read operation, the read enable, chip select, and read address are aligned, and the data of the corresponding address is sent out after a delay of one clock cycle. Therefore, the SRAM interface can only read the correct data after a delay of one clock cycle. .
上述现有技术的访问静态存储器的方法的缺点为：The shortcoming of the method for accessing static memory of above-mentioned prior art is:
1、该方法降低了读操作的性能。1. This method reduces the performance of read operations.
在该方法中，在single方式下IMI(internal memory interface，内部存储器接口)模块向SRAM模块写数据的时序示意图如图3所示，其中共发生了5次写操作，有1次为无效写操作。haddr分别发出了地址A1至A5，在地址的下一周期hwdata分别发出数据D1-D5，地址A经过锁存与数据D一起输出至IMI接口的imi_addr和imi_hwdata，hreadyout信号在imi_hwdata数据写周期为高，hresp此时为有效。第五次写操作时，hsize不符合要求产生错误，wren信号无效，hreadyout拉低一个时钟周期，hresp变为Error持续两周期。In this method, the timing diagram of IMI (internal memory interface, internal memory interface) module writing data to the SRAM module in single mode is shown in Figure 3, in which 5 write operations occurred, and 1 was an invalid write operation . Haddr sends addresses A1 to A5 respectively, and hwdata sends data D1-D5 respectively in the next cycle of the address, address A is output to imi_addr and imi_hwdata of the IMI interface through latching and data D, and the hreadyout signal is high during the imi_hwdata data write cycle , hresp is valid at this time. In the fifth write operation, hsize does not meet the requirements and an error occurs, the wren signal is invalid, hreadyout is pulled down for one clock cycle, and hresp becomes Error for two cycles.
single方式下IMI模块从SRAM模块中读数据的时序示意图如图4所示，其中共发生了5次读操作，有1次为无效读操作。haddr的A1地址发出后，直通到imi_addr，imi_rdata经过2拍后给出D1。D1直通到hrdata，hreadyout在imi_addr的A1有效的下一个时钟周期被拉低，直到imi_rdata的D1有效被置高，图4中hreadyout等待了一个时钟周期。hreadyout有效时haddr发生变化，A2地址发出至静态存储器的SRAM，重复读过程。imi_rden是组合逻辑，在hwrite为低、hready和hsel(hready和hsel为AHB总线送过来的信号，图4中没有表达出来)都为高时，给出高电平。由于读操作处于single模式下，每次读命令发出后hreadyout均要延迟一个时钟周期，等待数据从静态存储器的SRAM中读出。A5地址读操作时，由于给出了IMI不支持的字节操作，因此imi_rden无效，读出数据无效(图4中的×所示部分)，hresp回应2周期的error。The timing diagram of the IMI module reading data from the SRAM module in the single mode is shown in Figure 4, in which there are 5 read operations in total, and 1 is an invalid read operation. After the A1 address of haddr is sent out, it goes directly to imi_addr, and imi_rdata gives D1 after 2 beats. D1 is passed directly to hrdata, and hreadyout is pulled low in the next clock cycle when A1 of imi_addr is valid, until D1 of imi_rdata is effectively set high, and hreadyout waits for one clock cycle in Figure 4. Haddr changes when hreadyout is valid, and the A2 address is sent to the SRAM of the static memory, and the read process is repeated. imi_rden is combination logic, when hwrite is low, hready and hsel (hready and hsel are the signals sent by the AHB bus, not expressed in Figure 4) are high, it gives a high level. Because the read operation is in the single mode, hreadyout will delay one clock cycle after each read command is issued, waiting for the data to be read from the SRAM of the static memory. During the read operation of the A5 address, since a byte operation not supported by IMI is given, imi_rden is invalid, and the read data is invalid (the part shown by × in Figure 4), and hresp responds with an error of 2 cycles.
因此可见，在该方法中，对于读SRAM操作而言，single方式在每次读操作时，都会产生一个周期的等待时间；对于写操作而言，没有这方面的影响。当系统发生频繁读SRAM的内容操作的时候，AHB总线将会多花费一倍的时间用于等待数据从SRAM中读出，严重影响了系统性能。Therefore, it can be seen that in this method, for the read operation of the SRAM, the single mode will generate a waiting time of one cycle for each read operation; for the write operation, there is no influence in this respect. When the system frequently reads the content of the SRAM, the AHB bus will spend twice as long waiting for the data to be read from the SRAM, which seriously affects the system performance.
2、对于某些特定的模块如基带处理模块等，往往是寄存器堆与静态存储器统一编址，静态存储器的数据位宽在生产时就已经固定，但是寄存器堆的数据位宽要求可动态配置，例如一个接口既要能够进行16位访问，又要能够进行32位访问，对于32位数据的访问，既要能单独访问32位的高16位，又要能单独访问低16位。这样，单一的静态存储器接口就不能满足这种需求。2. For some specific modules such as baseband processing modules, etc., the register file and the static memory are often addressed uniformly. The data bit width of the static memory is fixed at the time of production, but the data bit width of the register file can be dynamically configured. For example, an interface must be able to perform 16-bit access and 32-bit access. For 32-bit data access, it must be able to independently access the upper 16 bits of 32 bits and the lower 16 bits. Thus, a single static memory interface cannot meet this requirement.
发明内容Contents of the invention
本发明的目的是提供一种静态存储器接口装置及其数据传输方法，从而可以在静态存储器接口装置内部计算出当前静态存储器的访问地址，实现流水线架构的总线以突发数据传送方式访问静态存储器。The object of the present invention is to provide a static memory interface device and a data transmission method thereof, so that the access address of the current static memory can be calculated inside the static memory interface device, and the bus of the pipeline architecture can access the static memory in a burst data transmission mode.
本发明的目的是通过以下技术方案实现的：The purpose of the present invention is achieved through the following technical solutions:
一种静态存储器接口装置，流水线架构的总线通过该静态存储器接口装置与静态存储器进行数据交互，所述的静态存储器接口装置具体包括：A static memory interface device, through which the bus of the pipeline architecture performs data interaction with the static memory, the static memory interface device specifically includes:
控制逻辑模块：监控流水线架构的总线的读写状态并进行判断处理，产生流水线架构的总线与静态存储器进行交互所需要的读写控制信号，并将产生的读写控制信号传递给地址译码模块；Control logic module: monitor the read and write status of the bus of the pipeline architecture and perform judgment processing, generate the read and write control signals required for the interaction between the bus of the pipeline architecture and the static memory, and pass the generated read and write control signals to the address decoding module ;
地址译码模块：根据流水线架构的总线的地址状态和控制逻辑模块传递过来的读写控制信号，产生与静态存储器进行交互的数据流的地址信号。Address decoding module: According to the address state of the bus of the pipeline architecture and the read and write control signals transmitted by the control logic module, generate the address signal of the data stream interacting with the static memory.
所述的静态存储器接口装置还包括：The static memory interface device also includes:
字节选择模块：根据地址译码模块产生的地址信号和与静态存储器进行交互的数据流的总字节数据位宽输出字节选择标志给静态存储器。Byte selection module: output the byte selection flag to the static memory according to the address signal generated by the address decoding module and the total byte data bit width of the data flow interacting with the static memory.
所述的数据流的总字节数据位宽为：8位或16位或32位或64位或128位。The total byte data bit width of the data stream is: 8 bits or 16 bits or 32 bits or 64 bits or 128 bits.
所述的静态存储器接口装置还包括读写使能模块和数据传输模块，The static memory interface device also includes a read-write enabling module and a data transmission module,
读写使能模块：根据控制逻辑模块传递过来的读写控制信号，产生流水线架构的总线与静态存储器进行交互的读使能信号或写使能信号，将该读使能信号或写使能信号传递给静态存储器与数据传输模块；Read and write enable module: According to the read and write control signals transmitted by the control logic module, generate a read enable signal or write enable signal for the bus of the pipeline architecture to interact with the static memory, and use the read enable signal or write enable signal passed to the static memory and data transfer module;
数据传输模块：根据读写使能模块传递过来的读使能信号，从静态存储器输出数据到流水线架构的总线；或者，根据读写使能模块传递过来的写使能信号，从流水线架构的总线输出数据到静态存储器。Data transmission module: output data from the static memory to the bus of the pipeline architecture according to the read enable signal passed by the read-write enable module; or, according to the write enable signal passed by the read-write enable module, output data from the bus of the pipeline architecture Output data to static memory.
所述的静态存储器接口装置还包括：The static memory interface device also includes:
响应反馈模块：根据控制逻辑模块产生并传递过来的冲突控制信号，向流水线架构的总线反馈相应的冲突信号，使流水线架构的总线不执行当前周期的读操作；根据控制逻辑模块产生并传递过来的错误控制信号，向流水线架构的总线反馈相应的错误信号。Response feedback module: According to the conflict control signal generated and transmitted by the control logic module, the corresponding conflict signal is fed back to the bus of the pipeline architecture, so that the bus of the pipeline architecture does not perform the read operation of the current cycle; according to the conflict control signal generated and transmitted by the control logic module The error control signal feeds back the corresponding error signal to the bus of the pipeline architecture.
所述的控制逻辑模块包括：Described control logic module comprises:
传送类型错误判别模块：当流水线架构的总线发送完一个写操作后，在紧接着的下一个时钟周期发送一个读操作时，向响应反馈模块发送冲突控制信号；和/或，当流水线架构的总线发生传输错误时，向响应反馈模块发送错误控制信号。Transmission type error judgment module: when the bus of the pipeline architecture sends a write operation and sends a read operation in the next clock cycle immediately after, send a conflict control signal to the response feedback module; and/or, when the bus of the pipeline architecture When a transmission error occurs, an error control signal is sent to the response feedback module.
所述的地址译码模块：The address decoding module:
计算模块，根据流水线架构的总线传递过来的首地址和控制逻辑模块传递过来的读写控制信号，利用地址计数器、地址加法器，计算出与静态存储器进行交互的数据流的当前地址并输出给静态存储器；或者The computing module calculates the current address of the data flow interacting with the static memory by using the address counter and address adder according to the first address transmitted by the bus of the pipeline architecture and the read-write control signal transmitted by the control logic module, and outputs it to the static memory storage; or
传送模块，直接将流水线架构总线传递过来的首地址输出至静态存储器。The transfer module directly outputs the first address transferred from the pipeline architecture bus to the static memory.
所述的静态存储器接口装置适用于突发数据传送方式或单个数据传送方式。The static memory interface device is suitable for burst data transmission mode or single data transmission mode.
所述的静态存储器接口装置挂接在流水线架构的总线上或嵌入到静态存储器内部。The static memory interface device is connected to the bus of the pipeline architecture or embedded in the static memory.
所述的流水线架构的总线为：先进高性能AHB总线或先进可扩展接口AXI总线或AHB总线的子集。The bus of the pipeline architecture is: an advanced high-performance AHB bus or an advanced extensible interface AXI bus or a subset of the AHB bus.
所述的控制逻辑子模块和所述的响应反馈子模块组成总线状态机，所述的地址译码子模块和所述的读写使能子模块组成地址和读写控制状态机。The control logic sub-module and the response feedback sub-module form a bus state machine, and the address decoding sub-module and the read-write enable sub-module form an address and read-write control state machine.
一种静态存储器接口装置的数据传输方法，包括：A data transmission method of a static memory interface device, comprising:
静态存储器接口装置监控流水线架构的总线的读写状态和地址状态产生相应的地址信号；根据所述地址信号所述流水线架构的总线按照设定数据传送方式与静态存储器进行数据交互。The static memory interface device monitors the read/write status and address status of the bus of the pipeline architecture to generate corresponding address signals; according to the address signals, the bus of the pipeline architecture performs data interaction with the static memory according to the set data transmission mode.
所述方法具体包括：Described method specifically comprises:
当AHB总线以突发数据传送方式与所述静态存储器进行数据交互时，AHB总线发送的读首地址的数据接收比读地址发送晚两个时钟周期，以后，AHB总线发送的读数据接收比读地址发送晚一个时钟周期；AHB总线发送的写数据比写地址晚一个时钟周期。When the AHB bus carried out data interaction with the static memory in a burst data transfer mode, the data reception of the read head address sent by the AHB bus was sent two clock cycles later than the read address, and later, the read data sent by the AHB bus was received faster than the read address. The address is sent one clock cycle later; the write data sent by the AHB bus is one clock cycle later than the write address.
所述方法还包括：The method also includes:
当在AHB总线上发送完一个写操作后，在紧接着的下一个时钟周期发送一个读操作时，将AHB总线设置为繁忙状态，将响应反馈模块向AHB总线输出的任务完成hreadyout信号置位一个时钟周期，该时钟周期内读写使能模块产生的读使能信号无效，在该时钟周期结束后，将AHB总线和hreadyout信号设置为正常状态。When a write operation is sent on the AHB bus, when a read operation is sent in the next clock cycle, the AHB bus is set to a busy state, and the response feedback module outputs the task to the AHB bus to complete the hreadyout signal. Clock cycle, the read enable signal generated by the read and write enable module is invalid in this clock cycle, after the end of this clock cycle, the AHB bus and hreadyout signal are set to a normal state.
由上述本发明提供的技术方案可以看出，本发明设计了一种多功能静态存储器接口装置，在多功能静态存储器接口装置内部通过地址自增机制计算出当前静态存储器的访问地址，实现了AHB等流水线架构的总线以突发数据传送方式访问静态存储器。和现有技术相比，具有如下优点：It can be seen from the above-mentioned technical solution provided by the present invention that the present invention designs a multifunctional static memory interface device, and calculates the access address of the current static memory through the address self-increment mechanism inside the multifunctional static memory interface device, realizing AHB The bus of the pipeline architecture accesses the static memory in a burst data transfer mode. Compared with the prior art, it has the following advantages:
1、静态存储器接口读数据接收比读地址发送(及读控制信号)晚两个时钟周期；写数据与写地址同拍发送，静态存储器接口的写地址比AHB接口的写地址晚一个时钟周期发送。在burst方式下，读首地址的数据接收比读地址发送(及读控制信号)晚两个时钟周期，以后均连续读出；写数据比写地址晚一个时钟周期；这样减少了burst读操作时，流水线架构总线(如AHB总线)访问静态存储器的读等待时间，提高总线访问效率。1. The read data reception of the static memory interface is two clock cycles later than the read address transmission (and read control signal); the write data is sent at the same time as the write address, and the write address of the static memory interface is sent one clock cycle later than the write address of the AHB interface . In the burst mode, the data reception of the read first address is two clock cycles later than the sending of the read address (and the read control signal), and will be read continuously afterwards; the write data is one clock cycle later than the write address; this reduces the burst read operation time , The pipeline architecture bus (such as AHB bus) accesses the read waiting time of the static memory, and improves the bus access efficiency.
2、对读写转换作了专门处理，可以消除写后读带来的一个额外时钟周期的等待，提高了流水线架构总线(如AHB总线)对于静态存储器的访问效率。2. The read-write conversion is specially processed, which can eliminate the waiting of an extra clock cycle caused by the read-after-write, and improve the access efficiency of the pipeline architecture bus (such as the AHB bus) to the static memory.
3、在静态存储器接口装置的输出信号中增加了字节选择信号，从而使该静态存储器接口装置可以同时支持多数据位访问，支持用户自定义的数据访问，使静态存储器接口装置的适应面更广。3. A byte selection signal is added to the output signal of the static memory interface device, so that the static memory interface device can support multi-data bit access at the same time, support user-defined data access, and make the static memory interface device more adaptable wide.
4、作为一个IP单元的设计，本发明的地址线和数据线都可以按需要配置或扩展，可以外接多种类型的静态存储器，静态存器可以位于芯片内部，可以位于芯片外部。4. As an IP unit design, the address lines and data lines of the present invention can be configured or expanded as required, and various types of static memory can be externally connected, and the static memory can be located inside or outside the chip.
附图说明Description of drawings
图1为现有技术中同步SRAM的写时序示意图；FIG. 1 is a schematic diagram of write timing of a synchronous SRAM in the prior art;
图2为现有技术中同步SRAM的读时序示意图；FIG. 2 is a schematic diagram of read timing of a synchronous SRAM in the prior art;
图3为现有技术中single方式下IMI模块接口的写操作时序示意图；FIG. 3 is a schematic diagram of the write operation sequence of the IMI module interface in the single mode in the prior art;
图4为现有技术中single方式下IMI模块接口的读操作时序示意图；4 is a schematic diagram of the read operation sequence of the IMI module interface in the single mode in the prior art;
图5为应用了本发明所述静态存储器接口装置的系统结构示意图；FIG. 5 is a schematic structural diagram of a system to which the static memory interface device of the present invention is applied;
图6为本发明所述静态存储器接口装置的实施例的接口示意图；FIG. 6 is a schematic diagram of an interface of an embodiment of the static memory interface device of the present invention;
图7为本发明所述静态存储器接口装置的实施例的结构示意图；7 is a schematic structural diagram of an embodiment of the static memory interface device of the present invention;
图8为本发明所述静态存储器接口装置的内部读写交替时序示意图；Fig. 8 is a schematic diagram of the internal read and write alternate timing of the static memory interface device according to the present invention;
图9为本发明所述静态存储器接口装置的连接交替读写时序示意图；FIG. 9 is a schematic diagram of the connection alternate read and write sequence of the static memory interface device of the present invention;
图10为在burst方式下本发明所述静态存储器接口装置向静态存储器写入数据的时序示意图；10 is a schematic diagram of the timing of writing data to the static memory by the static memory interface device of the present invention in the burst mode;
图11为无地址计数器时burst方式下本发明所述静态存储器接口装置的从静态存储器读出数据时的时序示意图；FIG. 11 is a schematic diagram of the timing sequence when the static memory interface device of the present invention reads data from the static memory in the burst mode when there is no address counter;
图12为有地址计数器时burst方式下本发明所述静态存储器接口装置从静态存储器读出数据时的时序示意图；FIG. 12 is a schematic diagram of the timing sequence when the static memory interface device of the present invention reads data from the static memory in the burst mode when there is an address counter;
图13为在burst方式下本发明所述静态存储器接口装置内部的一个写时序示意图；FIG. 13 is a schematic diagram of a write sequence inside the static memory interface device of the present invention in the burst mode;
图14为在burst方式下本发明所述静态存储器接口装置内部的一个读时序示意图。FIG. 14 is a schematic diagram of a read sequence inside the static memory interface device of the present invention in the burst mode.
具体实施方式Detailed ways
本发明提供了一种静态存储器接口装置及其数据传输方法，本发明的核心为：在多功能静态存储器接口装置内部根据流水线架构的总线的地址状态和相应的读写控制信号计算出当前静态存储器的访问地址。The present invention provides a static memory interface device and a data transmission method thereof. The core of the present invention is: in the multifunctional static memory interface device, the current static memory is calculated according to the address state of the bus of the pipeline architecture and the corresponding read and write control signals. access address.
下面结合附图来详细描述本发明，本方法所述静态存储器接口装置具有多种功能，应用了本发明所述静态存储器接口装置的系统的典型结构如图5所示。该多功能静态存储器接口装置可以和ARM处理器、其它设备(比如设备0、设备1和设备2)一起挂接在系统的AHB总线上，再与SRAM与寄存器堆相连。AHB总线通过该多功能静态存储器接口装置来访问SRAM与寄存器堆。在实际应用中，上述AHB总线可以用AXI(先进可扩展接口)总线或AHB总线的任何子集，如AHB Lite总线来代替。The present invention will be described in detail below in conjunction with the accompanying drawings. The static memory interface device described in this method has multiple functions. The typical structure of a system using the static memory interface device described in the present invention is shown in FIG. 5 . The multifunctional static memory interface device can be connected to the AHB bus of the system together with the ARM processor and other devices (such as
本发明所述静态存储器接口装置的实施例的接口示意图如图6所示。AHB Slave总线接口信号与AHB总线相连，用于AHB总线对该静态存储器接口装置进行读写访问，SRAM与寄存器堆接口信号用于该模块访问SRAM或者寄存器堆。Imi_addr信号是地址信号，Imi_rdata信号和Imi_wdata信号分别是读数据信号和写数据信号，Imi_rden信号和Imi_wren信号分别是读使能信号和写使能信号，Imi_hwls信号是字节选择信号，用于选择读写数据中的有效字节，Imi_hwls信号对于固定数据位宽的静态存储器无效。The interface schematic diagram of the embodiment of the static memory interface device of the present invention is shown in FIG. 6 . The AHB Slave bus interface signal is connected to the AHB bus, which is used for the AHB bus to read and write access to the static memory interface device, and the SRAM and register file interface signal is used for the module to access the SRAM or register file. The Imi_addr signal is the address signal, the Imi_rdata signal and the Imi_wdata signal are the read data signal and the write data signal respectively, the Imi_rden signal and the Imi_wren signal are the read enable signal and the write enable signal respectively, and the Imi_hwls signal is the byte select signal for selecting the read Valid byte in write data, Imi_hwls signal is invalid for static memory with fixed data bit width.
本发明所述静态存储器接口装置的实施例的结构如图7所示，具体包括：控制逻辑模块、地址译码模块、字节选择模块、读写使能模块、响应反馈模块和数据传输模块，下面分别介绍上述各个模块的功能。The structure of the embodiment of the static memory interface device of the present invention is shown in Figure 7, specifically including: a control logic module, an address decoding module, a byte selection module, a read and write enabling module, a response feedback module and a data transmission module, The functions of the above modules are introduced respectively below.
1、控制逻辑模块。1. Control logic module.
控制逻辑模块包括：传送类型错误判别模块、总线监控逻辑模块、比较器等模块。在AHB总线通过上述静态存储器接口装置与静态存储器进行数据交互时，控制逻辑模块主要监控AHB总线的读写状态，通过burst结束比较器进行判断处理，产生AHB总线与静态存储器进行交互所需要的读写控制信号，并将产生的数据流控制信号传递给地址译码模块。控制逻辑模块还根据AHB总线当前周期和上一个周期的读写状态，产生冲突控制信号，并传递给响应反馈模块。控制逻辑模块还产生错误控制信号，并传递给响应反馈模块。The control logic module includes: transmission type error judgment module, bus monitoring logic module, comparator and other modules. When the AHB bus performs data interaction with the static memory through the above-mentioned static memory interface device, the control logic module mainly monitors the read and write status of the AHB bus, and judges and processes through the burst end comparator to generate the read data required for the interaction between the AHB bus and the static memory. Write the control signal, and pass the generated data flow control signal to the address decoding module. The control logic module also generates a conflict control signal according to the current cycle of the AHB bus and the read/write status of the previous cycle, and transmits it to the response feedback module. The control logic module also generates an error control signal and passes it to the response feedback module.
传送类型错误判别模块：当AHB总线发生读写冲突时，即当AHB总线发送完一个写操作后，在紧接着的下一个时钟周期发送一个读操作时，将所述AHB总线设置为繁忙状态，并设置相应的读使能信号为无效，向响应反馈模块发送冲突控制信号；当读写冲突结束后，设置相应的读使能信号为有效；Transmission type error discrimination module: when a read-write conflict occurs on the AHB bus, that is, when the AHB bus sends a write operation and then sends a read operation in the next clock cycle, the AHB bus is set to a busy state, And set the corresponding read enable signal to be invalid, and send a conflict control signal to the response feedback module; when the read and write conflict is over, set the corresponding read enable signal to be valid;
当AHB总线发生传输错误时，向响应反馈模块发送错误控制信号。错误控制信号产生的条件为，AHB总线发出了上述静态存储器接口装置不支持的突发传送类型和不支持的数据位宽。When a transmission error occurs on the AHB bus, an error control signal is sent to the response feedback module. The condition for generating the error control signal is that the AHB bus sends out a burst transfer type and an unsupported data bit width that are not supported by the static memory interface device.
在上述图7所示的静态存储器接口装置中，控制逻辑模块的具体处理过程如下：In the static memory interface device shown in FIG. 7 above, the specific processing process of the control logic module is as follows:
本发明所述静态存储器接口装置的内部读写交替时序图如图8所示。首先，控制逻辑模块中的总线监控逻辑模块判断AHB总线的当前周期是否开始进行一次新的有效读写操作，若符合读写传送条件，则new_read或new_write有效。若符合传输类型出错条件，则error有效。The internal read and write alternate timing diagram of the static memory interface device of the present invention is shown in FIG. 8 . First, the bus monitoring logic module in the control logic module judges whether the current cycle of the AHB bus starts to perform a new effective read and write operation. If the read and write transmission conditions are met, new_read or new_write is valid. If the transmission type error condition is met, error is valid.
在上述new_read或new_write有效的同时，总线监控逻辑模块同时产生读起始信号read_start，表示当前AHB为burst读起始地址操作(或者single读操作)。如果上一个周期为写操作(write_busy有效)，而紧接着这一周期为读操作，则这一周期发生了读写冲突，读写同时read_during_write信号被置位，任务完成hreadyout信号需要等一个时钟周期，读起始信号read_start信号无效；等到下一周期read_during_write无效，而读接着写read_after_write信号有效时，才能将imi_rden置位，此时read_start变为有效。While the above-mentioned new_read or new_write is valid, the bus monitoring logic module simultaneously generates a read start signal read_start, indicating that the current AHB is a burst read start address operation (or a single read operation). If the previous cycle is a write operation (write_busy is valid), and the next cycle is a read operation, then a read-write conflict occurs in this cycle, and the read_during_write signal is set at the same time as the read and write, and the task needs to wait for a clock cycle for the hreadyout signal , the read start signal read_start signal is invalid; wait until the next cycle read_during_write is invalid, and when the read and then write read_after_write signal is valid, the imi_rden can be set, and read_start becomes valid at this time.
Burst读写标志控制逻辑产生burst状态标志burst_proc、读burst状态标志burst_rdproc、写burst状态标志burst_wrproc。由于single方式可以看成burst方式对首地址的操作，因此single方式也被当成一种特殊的burst操作进行处理。Burst结束比较器产生burst结束标志burst_end，用以控制burst操作是否结束。Burst结束条件为burst计数器burst_cnt等于计数器满值标志burst_cntmax。Burst read and write flag control logic generates burst state flag burst_proc, read burst state flag burst_rdproc, write burst state flag burst_wrproc. Since the single mode can be regarded as the operation of the first address in the burst mode, the single mode is also treated as a special burst operation. The burst end comparator generates the burst end flag burst_end to control whether the burst operation ends. The Burst end condition is that the burst counter burst_cnt is equal to the counter full value flag burst_cntmax.
本发明所述静态存储器接口装置的连接交替读写的时序示意图如图9所示。A1至A2、A4至A5皆为静态存储器接口装置写到读的时序切换。由于写操作时，写数据要延迟一拍给出，此时静态存储器接口的地址及控制信号属于写操作所有，因此hreadyout信号在下一周期发出一拍无效(由于hreadyout为寄存器输出，所以只能在下一周期才给出无效信号)，表明此时总线忙，正在进行上一拍的写操作，紧接着的第二个数据的读操作须延迟一拍，最后导致imi_rden延迟一拍。The schematic diagram of the timing sequence of the connection and alternate reading and writing of the static memory interface device of the present invention is shown in FIG. 9 . All of A1 to A2 and A4 to A5 are timing switches from writing to reading of the static memory interface device. Since the write data is delayed by one beat during the write operation, the address and control signal of the static memory interface belong to the write operation at this time, so the hreadyout signal is invalid for one beat in the next cycle (since the hreadyout is a register output, it can only be used in the next cycle) An invalid signal is given in one cycle), indicating that the bus is busy at this time, and the write operation of the previous beat is in progress, and the read operation of the second data must be delayed by one beat, which finally causes imi_rden to be delayed by one beat.
A2至A3为静态存储器接口装置读到写的时序切换。由于读时序中从imi_addr地址发出至静态存储器接口，到数据自静态存储器接口读出本身有两拍的延迟，因此hreadyout在imi_rden有效后继续拉低一拍，以留出时间从静态存储器读取数据。此时AHB总线保持A3的地址和控制信号不变，待到hreadyout再次为高时将D3写入，并读取A4。A4为写操作，A5、A6为读操作，工作原理同A1、A2、A3。A2 to A3 are timing switching from reading to writing of the static memory interface device. Since there is a two-beat delay in the read sequence from when the imi_addr address is sent to the static memory interface, and when the data is read from the static memory interface, hreadyout continues to be pulled down for one beat after imi_rden is valid to allow time to read data from the static memory . At this time, the AHB bus keeps the address and control signal of A3 unchanged, and when hreadyout is high again, write D3 and read A4. A4 is write operation, A5, A6 are read operation, the working principle is the same as A1, A2, A3.
2、地址译码模块。2. Address decoding module.
地址译码模块主要根据控制逻辑子模块传递过来的读写控制信号，通过地址预取机制和地址自增功能产生与静态存储器进行交互的数据流的地址信号并传递给静态存储器。地址预取机制的过程为，当产生一个读起始信号read_start后，MUX将总线上的地址直接输出，以节省一个时钟周期。地址自增机制的过程为，每当产一个新的读写信号时(即new_read/new_write信号有效)，总线上的地址被载入到起始地址寄存器start_addr。地址计数器根据流水线架构的总线传递过来的首地址和控制逻辑模块传递过来的数据流控制信号，计算出当前操作地址的偏移量burst_cnt；地址加法器将起始地址start_addr和地址偏移量burst_cnt相加，得到与静态存储器进行交互的数据流的当前地址并传输给静态存储器。地址译码模块还将产生的地址信号传递给字节选择模块。The address decoding module mainly generates the address signal of the data stream interacting with the static memory through the address prefetching mechanism and the address self-increment function according to the read and write control signals transmitted by the control logic sub-module, and transmits it to the static memory. The process of the address prefetching mechanism is that when a read start signal read_start is generated, the MUX directly outputs the address on the bus to save a clock cycle. The process of the address self-increment mechanism is that whenever a new read/write signal is generated (that is, the new_read/new_write signal is valid), the address on the bus is loaded into the start address register start_addr. The address counter calculates the offset burst_cnt of the current operating address according to the first address transmitted by the bus of the pipeline architecture and the data flow control signal transmitted by the control logic module; the address adder compares the start address start_addr with the address offset burst_cnt Add, get the current address of the data stream interacting with the static memory and transmit it to the static memory. The address decoding module also transmits the generated address signal to the byte selection module.
在上述图7所示的静态存储器接口装置中，地址译码模块的地址预取机制和地址自增功能的具体处理过程如下：In the above-mentioned static memory interface device shown in FIG. 7 , the address prefetch mechanism and the address auto-increment function of the address decoding module are specifically processed as follows:
地址预取机制：为满足最大计数条件(hsize＝WORD，burst次数为16；hsize＝INCR，INCR表示不规定长度的数据。，burst次数最大与地址界限相同，为1K)，burst计数器burst_cnt应为一个10位宽的计数器。当new_write或read_during_write有效时，burst计数器清零(read_during_write有效即读写冲突时，读操作地址应该提前一个时钟周期载入，以便当read_after_write有效时输出前一个时钟周期的读地址A2，而不是当前AHB总线的地址，此时haddr已经改变成下一个时钟周期的地址A3了)。当new_read有效时载入读操作初值，hsize为WORD时为2，hsize为HWORD时为1。burst_cnt在WORD时计数累进值为2，在HWORD时计数累进值为1，htrans为BUSY时不计数。Address prefetching mechanism: In order to meet the maximum counting condition (hsize=WORD, the number of bursts is 16; hsize=INCR, INCR means data with an unspecified length. The maximum number of bursts is the same as the address limit, which is 1K), the burst counter burst_cnt should be A 10-bit wide counter. When new_write or read_during_write is valid, the burst counter is cleared (read_during_write is valid, that is, when read and write conflicts, the read operation address should be loaded one clock cycle in advance, so that when read_after_write is valid, the read address A2 of the previous clock cycle is output instead of the current AHB The address of the bus, at this time haddr has been changed to the address A3 of the next clock cycle). When new_read is valid, load the initial value of the read operation, when hsize is WORD, it is 2, and when hsize is HWORD, it is 1. When burst_cnt is WORD, the cumulative counting value is 2, when it is HWORD, the counting cumulative value is 1, and when htrans is BUSY, it does not count.
由于静态存储器接口装置的读操作会延迟两个时钟周期，因此读起始信号read_start有效时，直接将haddr地址发出，以减少一个时钟周期等待周期；当进行写burst第二拍操作，或者写操作时才将burst_addr发出。burst_addr在时钟边沿改变，因此写操作时的burst_addr总是为总线上延迟一个时钟周期的地址。也正因为要提早一个时钟周期进行读操作，burst_cnt在读burst第一个时钟周期时载入值应为1或2，以在第二拍时直接将1或2输出。Since the read operation of the static memory interface device will be delayed by two clock cycles, when the read start signal read_start is valid, the haddr address is directly issued to reduce the waiting period of one clock cycle; when performing the second beat operation of the write burst, or the write operation The burst_addr will be issued only when. The burst_addr changes on the clock edge, so the burst_addr in the write operation is always the address delayed by one clock cycle on the bus. It is also because the read operation is performed one clock cycle earlier, the load value of burst_cnt should be 1 or 2 when reading the first clock cycle of burst, so that 1 or 2 can be output directly at the second beat.
地址自增机制：起始地址产生逻辑产生burst操作的起始地址start_addr，在new_read或new_write有效时从AHB载入地址haddr，其余时候保持不变。地址加法器将burst_cnt与起始地址start_addr的低位相加，得到当前burst操作访问内存的地址burst_addr。为了保证地址不越出1K范围，以及满足WRAP操作要求，burst_cnt左移一位后与start_addr的加法规则如下：Address self-increment mechanism: the start address generation logic generates the start address start_addr of the burst operation, and loads the address haddr from AHB when new_read or new_write is valid, and remains unchanged for other times. The address adder adds burst_cnt to the low bits of the start address start_addr to obtain the address burst_addr of the memory accessed by the current burst operation. In order to ensure that the address does not exceed the 1K range and meet the WRAP operation requirements, the addition rules of burst_cnt and start_addr are as follows:
hburst＝xx1，低10相加(INCR，范围1K)hburst=xx1, add low 10 (INCR, range 1K)
hburst＝000，single方式，burst_cnt始终为0hburst=000, single mode, burst_cnt is always 0
hburst＝010，低4位相加(WRAP4，范围4*HSIZE/8)hburst=010, add the lower 4 bits (WRAP4, range 4*HSIZE/8)
hburst＝100，低5位相加(WRAP8，范围8*HSIZE/8)hburst=100, add the lower 5 bits (WRAP8,
hburst＝110，低6位相加(WRAP16，范围16*HSIZE/8)hburst=110, add the lower 6 bits (WRAP16, range 16*HSIZE/8)
为了提高效率，burst方式时，在模块内增加地址计数器，根据hburst信号进行累进计数或循环计数。在首地址给出时需要根据haddr、hburst信号和hsize信号来判断其合法性。In order to improve efficiency, in the burst mode, add an address counter in the module, and perform incremental counting or circular counting according to the hburst signal. When the first address is given, its legality needs to be judged according to haddr, hburst signal and hsize signal.
在burst方式下本发明所述静态存储器接口装置向静态存储器写入数据的时序示意图如图10所示。该模式与single方式操作类似，这是因为写操作无需额外的等待周期，地址计数器的作用没有发挥。The timing diagram of writing data into the static memory by the static memory interface device of the present invention in the burst mode is shown in FIG. 10 . This mode is similar to the operation of the single mode, because the write operation does not need an additional waiting cycle, and the role of the address counter is not played.
无地址计数器时burst方式下静态存储器接口装置从静态存储器读出数据时的时序示意图如图11所示。burst读操作时，由于地址需要由AHB总线给出，尽管imi_rden已经在第2和5个时钟提前有效以读取数据，但是此时hreadyout还是必须要插入1个等待周期，以等待A3地址到来，并读数D1和D3。burst次数越多，插入的等待周期也多(第8个周期也将插入等待周期)。这样每读取两次数据，中间就会有一个等待周期，操作时间＝burst次数*1.5+1。而single方式下，每读取一次数据，就会有一个等待周期，操作时间＝burst次数*2+1。When there is no address counter, the timing diagram of the static memory interface device reading data from the static memory in the burst mode is shown in FIG. 11 . During the burst read operation, since the address needs to be given by the AHB bus, although imi_rden has been valid in advance at the 2nd and 5th clocks to read data, but at this time hreadyout still has to insert a wait cycle to wait for the arrival of the A3 address. And read D1 and D3. The more burst times, the more waiting cycles are inserted (the 8th cycle will also insert waiting cycles). In this way, every time data is read twice, there will be a waiting period in the middle, and the operation time = burst times * 1.5 + 1. In the single mode, each time data is read, there will be a waiting period, and the operation time = burst times * 2 + 1.
有地址计数器时burst方式下静态存储器接口装置从静态存储器读出数据时的时序示意图如图12所示。由于读地址由静态存储器接口装置内部产生，因此hreadyout只需要在读数D1时插入等待周期，其它时间均能连续读数据，这样burst次数越多，效率也就越高。操作周期＝burst次数+2。静态存储器接口装置采用此种方式。当burst次数为16时，原IMI模块操作周期为33，无地址计数器的静态存储器接口装置操作周期为25，有地址计数器的IMI模块静态存储器接口装置操作周期为18，比原来提高83.3％。现有IMI模块、不含Burst计数器的静态存储器接口装置和含有Burst计数器的静态存储器接口装置读Burst操作效率比较如表1所示。When there is an address counter, the timing diagram of when the static memory interface device reads data from the static memory in the burst mode is shown in FIG. 12 . Since the read address is internally generated by the static memory interface device, hreadyout only needs to insert a waiting period when reading D1, and can read data continuously at other times, so the more burst times, the higher the efficiency. Operation period = burst times + 2. The static memory interface device adopts this method. When the number of bursts is 16, the operating cycle of the original IMI module is 33, the operating cycle of the static memory interface device without address counter is 25, and the operating cycle of the IMI module static memory interface device with address counter is 18, which is 83.3% higher than the original. Table 1 shows the comparison of the read Burst operation efficiency of the existing IMI module, the static memory interface device without the Burst counter, and the static memory interface device with the Burst counter.
表1：IMI模块读Burst操作效率比较
3、字节选择模块。3. Byte selection module.
字节选择模块：根据地址译码模块产生的地址信号和与静态存储器进行交互的数据流的总字节数据位宽输出字节选择标志给静态存储器，该字节选择标志用以确定所述数据流的有效字节。所述的数据流的总字节数据位宽为：8位或16位或32位或64位或128位。Byte selection module: output the byte selection flag to the static memory according to the address signal generated by the address decoding module and the total byte data bit width of the data stream interacting with the static memory, and the byte selection flag is used to determine the data Valid bytes of the stream. The total byte data bit width of the data stream is: 8 bits or 16 bits or 32 bits or 64 bits or 128 bits.
在上述图7所示的静态存储器接口装置中，字节选择模块的具体处理过程如下：In the above static memory interface device shown in Figure 7, the specific processing of the byte selection module is as follows:
字节选择逻辑根据hsize和imi_addr输出字节选择标志imi_hwls，用于标志当前读写操作的数据中哪些字节是有效的。imi_hwls与读写使能信号同相位，信号定义可根据具体应用要求有所改变。例如，如果IMI仅要求支持16位或32位，imi_hwls可以按如下规则定义：The byte selection logic outputs the byte selection flag imi_hwls according to hsize and imi_addr, which is used to mark which bytes in the data of the current read and write operation are valid. imi_hwls is in the same phase as the read/write enable signal, and the signal definition can be changed according to specific application requirements. For example, if IMI only requires support for 16-bit or 32-bit, imi_hwls can be defined as follows:
1、hsize为WORD时(表示数据为32位)：imi_hwls[1:0]输出为11；1. When hsize is WORD (indicates that the data is 32 bits): imi_hwls[1:0] outputs 11;
2、hsize为HWORD时(表示数据为16位)：2. When hsize is HWORD (indicates that the data is 16 bits):
当系统为小端模式时：When the system is in little endian mode:
如果总线上的地址信号第1位imi_addr[1]＝1，则imi_hwls[1:0]输出为10(表示数据总线上的内容为上半字有效)；If the first bit of the address signal imi_addr[1]=1 on the bus, the output of imi_hwls[1:0] is 10 (indicating that the content on the data bus is valid for the upper half word);
如果总线上的地址信号第1位imi_addr[1]＝0，则imi_hwls[1:0]输出为01(表示数据总线上的内容为下半字有效)；If the first bit of the address signal imi_addr[1]=0 on the bus, the output of imi_hwls[1:0] is 01 (indicating that the content on the data bus is valid for the lower half word);
当系统为大端模式时：When the system is in big-endian mode:
如果总线上的地址信号第1位imi_addr[1]＝1时，则imi_hwls[1:0]＝01(表示数据总线上的内容为下半字有效)；If the first bit imi_addr[1]=1 of the address signal on the bus, then imi_hwls[1:0]=01 (representing that the content on the data bus is valid for the lower half word);
如果总线上的地址信号第1位imi_addr[1]＝0时，则imi_hwls[1:0]＝10(表示数据总线上的内容为上半字有效)；If the first bit imi_addr[1]=0 of the address signal on the bus, then imi_hwls[1:0]=10 (representing that the content on the data bus is valid for the upper half word);
3、hsize为其他值时：imi_hwls[1:0]输出00(表示数据总线上的内容一直为无效)。3. When hsize is other values: imi_hwls[1:0] outputs 00 (indicating that the content on the data bus is always invalid).
对于8位，64位，或者更高数据位宽如128位，可以仿照上述例子做出不同的规定，但基本原理都一样，采用相关信号表示一个读写数据中哪一个或几个字节是有效的。For 8-bit, 64-bit, or higher data bit width such as 128-bit, different regulations can be made according to the above example, but the basic principles are the same, using related signals to indicate which one or several bytes in a read-write data is Effective.
4、读写使能模块。4. Read and write enable module.
读写使能模块主要根据控制逻辑模块产生的读写控制信号，产生访问静态存储器的读使能信号或写使能信号，将该读使能信号或写使能信号传递给静态存储器和数据传输模块。The read-write enable module mainly generates the read-enable signal or write-enable signal for accessing the static memory according to the read-write control signal generated by the control logic module, and transmits the read-enable signal or write-enable signal to the static memory and data transmission module.
在上述图7所示的静态存储器接口装置中，读写使能模块的具体处理过程如下：In the static memory interface device shown in FIG. 7 above, the specific processing process of the read-write enable module is as follows:
写使能在AHB发出写信号后延迟一个时钟周期产生，与hwdata对齐，在burst过程中一直保持有效，且当htrans为BUSY时写使能无效(延迟给出)。The write enable is generated with a delay of one clock cycle after the AHB sends the write signal, aligned with hwdata, and remains valid during the burst process, and the write enable is invalid when htrans is BUSY (the delay is given).
读使能与写使能产生不同，在burst读开始，即new_read有效时读使能应立即产生，在读burst过程中一直保持有效。每当产生一次new_read，hreadyout信号就要拉低一个时钟周期，以保证静态存储器接口装置的双周期响应。需要注意的是，当read_during_wirte有效时，读写冲突，读使能imi_rden无效，要等到read_after_write有效时，读使能才能有效。The read enable is different from the write enable. When the burst read starts, that is, the read enable should be generated immediately when new_read is valid, and it will remain valid during the burst read process. Whenever a new_read is generated, the hreadyout signal will be pulled down for one clock cycle to ensure the double-cycle response of the static memory interface device. It should be noted that when read_during_write is valid, read and write conflicts, and the read enable imi_rden is invalid, and the read enable will not be valid until read_after_write is valid.
5、响应反馈模块。5. Response feedback module.
响应反馈模块根据传送类型错误判别模块传递过来的冲突控制信号，向流水线架构的总线反馈相应的冲突信号，使流水线架构的总线不执行当前周期的读操作；根据传送类型错误判别模块传递过来的错误控制信号，向流水线架构的总线反馈相应的错误信号。The response feedback module feeds back the corresponding conflict signal to the bus of the pipeline architecture according to the conflict control signal passed by the transfer type error judgment module, so that the bus of the pipeline architecture does not perform the read operation of the current cycle; the error passed by the judgment module according to the transfer type error The control signal feeds back the corresponding error signal to the bus of the pipeline architecture.
在上述图7所示的静态存储器接口装置中，响应反馈模块的具体处理过程如下：In the static memory interface device shown in FIG. 7 above, the specific processing process of the response feedback module is as follows:
响应反馈模块主要产生hresp和hreadyout信号，该hresp和hreadyout信号应符合AHB协议，并将该hresp和hreadyout信号传递给AHB总线接口。The response feedback module mainly generates hresp and hreadyout signals, the hresp and hreadyout signals should conform to the AHB protocol, and transmits the hresp and hreadyout signals to the AHB bus interface.
hreadyout在读起始信号发生时，在下一个时钟周期被拉低，以满足静态存储器接口装置双周期响应条件。因此每当new_read被置位时，hreadyout均被置位，并在下一周期清零。同时，为解决写后读产生的冲突，每当正在进行写操作即imi_wren有效时，如果此时紧接的周期为读操作，那么此时hreadyout信号应被置位，表明模块正忙于处理上一个周期的写操作，当前周期的读操作不能立即执行，以保证地址线不被冲突。可由read_during_write和read_after_write控制，当它们有效时，hreadyout皆为等待状态。When the read start signal occurs, hreadyout is pulled low in the next clock cycle to meet the double-cycle response condition of the static memory interface device. So whenever new_read is set, hreadyout is set and cleared in the next cycle. At the same time, in order to solve the conflict caused by read after write, whenever a write operation is in progress, that is, when imi_wren is valid, if the next cycle is a read operation, then the hreadyout signal should be set at this time, indicating that the module is busy processing the last The write operation of the cycle, the read operation of the current cycle cannot be executed immediately, so as to ensure that the address lines are not conflicted. It can be controlled by read_during_write and read_after_write. When they are valid, hreadyout is in a waiting state.
当产生错误时，error标志被置位，此时产生一个双周期的hresp＝ERROR响应。error产生条件为发生静态存储器接口装置也不支持的字节操作，可根据实际情况改变，如8位数据操作或64位及其以上数据位宽的操作。When an error occurs, the error flag is set, and a two-cycle hresp=ERROR response is generated at this time. The error generation condition is byte operation that is not supported by the static memory interface device, which can be changed according to the actual situation, such as 8-bit data operation or 64-bit and above data bit width operation.
6、数据传输模块。6. Data transmission module.
数据传输模块主要根据读写使能模块传递过来的读使能信号，从静态存储器读出数据并输出到流水线架构的总线；根据读写使能模块传递过来的写使能信号，从流水线架构的总线读出数据并输出到静态存储器。The data transmission module mainly reads the data from the static memory and outputs it to the bus of the pipeline architecture according to the read enable signal transmitted by the read and write enable module; Data is read from the bus and output to static memory.
本发明还提供了一个按照Burst数据传送方式访问上述静态存储器接口装置的实施例。The present invention also provides an embodiment of accessing the above-mentioned static memory interface device according to the Burst data transmission mode.
在burst方式下静态存储器接口装置内部的一个写时序示意图如图13所示。AHB发出一个INCR4的写HWORD信号，控制逻辑检测到有burst写信号产生，在时钟边沿产生一个burst_wrproc，该burst_wrproc表明开始一个写burst操作。起始地址产生逻辑锁存了起始地址4Ch，并在burst_wrproc有效时保持其不变，同时使imi_wren有效，开始向静态存储器接口装置写数据。Burst操作开始时，计数器burst_cnt载入了00，以后按照HWORD规律依次递增。burst_cnt与start_addr相加，依次输出4C、4E、50、52。当计数至06时，产生burst_end信号表示burst结束，因此在下一周期burst_wrproc和imi_wren均为无效。A schematic diagram of a write sequence inside the static memory interface device in the burst mode is shown in FIG. 13 . AHB sends an INCR4 write HWORD signal, and the control logic detects that a burst write signal is generated, and generates a burst_wrproc on the clock edge, and the burst_wrproc indicates the start of a write burst operation. The start address generation logic latches the start address 4Ch, and keeps it unchanged when burst_wrproc is valid, and at the same time makes imi_wren valid, and starts to write data to the static memory interface device. At the beginning of the Burst operation, the counter burst_cnt is loaded with 00, and then increments according to the HWORD rule. Add burst_cnt and start_addr, and
可见，burst写操作的时序与连续的single写操作时序相同，所有的AHB写数据均延迟一个时钟周期给出，除非总线有额外要求(如图13中在第3拍AHB插入了一个等待周期，延迟一个时钟周期后，imi_wren无效，计数器停止计数)。It can be seen that the timing of the burst write operation is the same as that of the continuous single write operation, and all AHB write data is given with a delay of one clock cycle, unless the bus has additional requirements (as shown in Figure 13, a wait cycle is inserted in the third beat AHB, After a delay of one clock cycle, imi_wren is invalid and the counter stops counting).
在burst方式下静态存储器接口装置内部的一个读时序示意图如图14所示。AHB发出一个WRAP4的读WORD信号。控制逻辑检测到有读信号产生，置burst_start为1，并在时钟边沿产生一个burst_rdproc，该burst_rdproc表明开始一个读burst操作。起始地址产生逻辑锁存了起始地址44h，并在burst_rdproc有效时其不变，同时使imi_rden有效，开始向静态存储器接口装置模块读数据。Burst操作开始的第一个周期时，read_start有效，因此最终输的地址imi_addr为直通的haddr的44，同时计数器burst_cnt载入了04。在burst操作的第二个周期以后，burst_cnt与start_addr相加，依次输出48、4C、40。当计数至0C时，产生burst_end信号表示burst结束，因此在下一周期burst_rdproc和imi_rden均为无效。A schematic diagram of a read timing inside the static memory interface device in the burst mode is shown in FIG. 14 . AHB sends out a WRAP4 read WORD signal. The control logic detects that a read signal is generated, sets burst_start to 1, and generates a burst_rdproc on the clock edge, and the burst_rdproc indicates the start of a read burst operation. The start address generation logic latches the start address 44h, and it remains unchanged when burst_rdproc is valid, and at the same time makes imi_rden valid, and starts to read data to the static memory interface device module. In the first cycle of the Burst operation, read_start is valid, so the final input address imi_addr is 44 of the through haddr, and the counter burst_cnt is loaded with 04. After the second cycle of the burst operation, burst_cnt is added to start_addr, and 48, 4C, and 40 are output in sequence. When counting to 0C, a burst_end signal is generated to indicate the end of the burst, so both burst_rdproc and imi_rden are invalid in the next cycle.
可见，在burst读操作方式下，静态存储器接口装置所有的读数据均延迟两个时钟周期给出，除非总线有等待的要求(图14中在第3拍AHB插入了一个等待周期，此时imi_rden无效，计数器停止计数)。第一个时钟周期读完以后，hreadyout置低，AHB等待一个时钟周期，在以后的读过程中就不再等待。It can be seen that in the burst read operation mode, all the read data of the static memory interface device are delayed by two clock cycles, unless the bus has a waiting requirement (a waiting cycle is inserted in the third beat AHB in Figure 14, at this time imi_rden invalid, the counter stops counting). After the first clock cycle is read, hreadyout is set low, AHB waits for a clock cycle, and will not wait in the subsequent reading process.
在上述方案中，总线和静态存储器的数据位宽和地址位宽可以根据实际情况扩展或删减：数据位宽可包括8位或16位或32位或64位或128位或者任意的非2N的数据位宽，如10位、12位等；地址位宽根据整个系统和静态存储器的容量而定；字节选择信号imi_hwls根据总线数据位宽和静态存储器数据位宽而定。In the above scheme, the data bit width and address bit width of the bus and static memory can be expanded or reduced according to the actual situation: the data bit width can include 8 bits or 16 bits or 32 bits or 64 bits or 128 bits or any non-2N The data bit width, such as 10 bits, 12 bits, etc.; the address bit width is determined according to the capacity of the entire system and the static memory; the byte selection signal imi_hwls is determined according to the bus data bit width and the static memory data bit width.
在上述方案中，本方法所述静态存储器接口装置是作为一个单独的模块挂接在AHB总线上，在实际应用中，可以将该静态存储器接口装置或者该静态存储器接口装置中的主要模块(控制逻辑模块，地址译码模块等)嵌入到其他模块中。In the above-mentioned scheme, the static memory interface device described in this method is hung on the AHB bus as a separate module. In practical applications, the static memory interface device or the main module (control logic module, address decoding module, etc.) embedded in other modules.
在上述方案中，采用了分离信号完成整个静态存储器接口装置的实现，但是实际上也可以利用状态机来实现本发明所述静态存储器接口装置的核心控制模块。例如，控制逻辑子模块和响应反馈子模块可组成总线状态机、地址译码子模块和读写使能子模块可组成地址和读写控制状态机。状态机的中心思想是用多个状态来表示系统的运行过程，主要的控制状态机可以包含单字节读、单字节写、突发方式读、突发方式写、空闲、数据传送出错等状态；突发方式读可以分为首次读、非首次读、等待等子状态；突发方式写可以分为首次写、非首次写、等待等子状态。用状态机设计控制逻辑也可以达到预期效果。In the above solution, separate signals are used to complete the realization of the entire static memory interface device, but in fact, a state machine can also be used to implement the core control module of the static memory interface device of the present invention. For example, the control logic sub-module and the response feedback sub-module can form a bus state machine, and the address decoding sub-module and the read-write enable sub-module can form an address and read-write control state machine. The central idea of the state machine is to use multiple states to represent the running process of the system. The main control state machine can include single-byte read, single-byte write, burst mode read, burst mode write, idle, data transmission error, etc. State; burst reading can be divided into sub-states such as first reading, non-first reading, and waiting; burst writing can be divided into first writing, non-first writing, waiting and other sub-states. Designing control logic with a state machine can also achieve the desired effect.
在上述方案中，所述的静态存储器可以是内部静态存储器或外部静态存储器，也可以是指具有同步静态存储器接口行为的器件或模块，以及它们的组合，如寄存器堆。并且静态存储器的种类包括：各种单向单端口、双向单端口、单向双端口和双向双端口等各种类型。In the above solution, the static memory may be an internal static memory or an external static memory, and may also refer to a device or module with a synchronous static memory interface behavior, and a combination thereof, such as a register file. And the types of the static memory include: various types of unidirectional single-port, bidirectional single-port, unidirectional dual-port, bidirectional dual-port, and the like.
本发明所述静态存储器接口装置的数据传输方法主要包括：The data transmission method of the static memory interface device according to the present invention mainly includes:
静态存储器接口装置监控流水线架构的总线的读写状态和地址状态产生相应的地址信号；根据所述地址信号所述流水线架构的总线按照设定数据传送方式与静态存储器进行数据交互。The static memory interface device monitors the read/write status and address status of the bus of the pipeline architecture to generate corresponding address signals; according to the address signals, the bus of the pipeline architecture performs data interaction with the static memory according to the set data transmission mode.
上述设定数据传送方式包括：突发数据传送方式或单个数据传送方式。The above-mentioned setting data transmission mode includes: a burst data transmission mode or a single data transmission mode.
当AHB总线以突发数据传送方式与所述静态存储器进行数据交互时，AHB总线发送的读首地址的数据接收比读地址发送晚两个时钟周期，以后，AHB总线发送的读数据接收比读地址发送晚一个时钟周期；AHB总线发送的写数据比写地址晚一个时钟周期。When the AHB bus carried out data interaction with the static memory in a burst data transfer mode, the data reception of the read head address sent by the AHB bus was sent two clock cycles later than the read address, and later, the read data sent by the AHB bus was received faster than the read address. The address is sent one clock cycle later; the write data sent by the AHB bus is one clock cycle later than the write address.
当在AHB总线上发送完一个写操作后，在紧接着的下一个时钟周期发送一个读操作时，将AHB总线设置为繁忙状态，将响应反馈模块向AHB总线输出的任务完成hreadyout信号置位一个时钟周期，该时钟周期内读写使能模块产生的读使能信号无效，在该时钟周期结束后，将AHB总线和hreadyout信号设置为正常状态。When a write operation is sent on the AHB bus, when a read operation is sent in the next clock cycle, the AHB bus is set to a busy state, and the response feedback module outputs the task to the AHB bus to complete the hreadyout signal. Clock cycle, the read enable signal generated by the read and write enable module is invalid in this clock cycle, after the end of this clock cycle, the AHB bus and hreadyout signal are set to a normal state.
以上所述，仅为本发明较佳的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present invention can easily think of changes or Replacement should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.
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