CN1881966A - Scrambler/descrambler of optical synchronous digital transmission system - Google Patents

Abstract

Translated fromChinese

光同步数字传输系统的帧同步加/解扰码器包括比特扰码电路，字节扰码电路，选择器，寄存器组1，寄存器组2，译码器1，译码器2，译码器3。比特扰码电路的输入来自寄存器组2的输出，结果输出到选择器的1端，字节扰码电路的输入来自寄存器组1的输出，结果输出到选择器的0端，选择器控制选择位来自译码器1的输出，其结果输出到寄存器组1，寄存器组1的使能位来自译码器2的输出，寄存器组1的输出就是整个扰码器电路的输出，同时也输出到寄存器组2和字节扰码电路，寄存器组2的使能位来自译码器3的输出。采用本发明所述的加/解扰码器大大降低了处理速率，并简化了逻辑，使得电路的规模大大降低，更易于工艺实现。

The frame synchronous adding/descrambling device of the optical synchronous digital transmission system includes a bit scrambling circuit, a byte scrambling circuit, a selector, a register group 1, a register group 2, a decoder 1, a decoder 2, and a decoder 3. The input of the bit scrambler circuit comes from the output of register group 2, and the result is output to terminal 1 of the selector. The input of the byte scramble circuit comes from the output of register group 1, and the result is output to terminal 0 of the selector, and the selector controls the selection bit The output from decoder 1, the result is output to register group 1, the enable bit of register group 1 comes from the output of decoder 2, the output of register group 1 is the output of the entire scrambler circuit, and it is also output to the register Group 2 and byte scrambling circuit, the enable bit of register group 2 comes from the output of decoder 3. The use of the scrambling/descrambling device of the present invention greatly reduces the processing rate, simplifies the logic, greatly reduces the scale of the circuit, and is easier for process realization.

Description

Translated fromChinese

一种光同步数字传输系统加/解扰码器A Scrambler/Descrambler for Optical Synchronous Digital Transmission System

技术领域technical field

本发明涉及光同步数字传输系统(SDH/SONET)，具体地说，涉及其中的帧同步加/解扰码。The present invention relates to optical synchronous digital transmission system (SDH/SONET), in particular, to frame synchronous scrambling/descrambling codes therein.

背景技术Background technique

同步数字传输系统一般由传输设备和网络节点两种基本设备组成，对于光同步数字传输系统，传输设备就是光缆系统，网络节点则比较复杂，包含终结设备(TM)、交叉连接设备(DXC)、复用设备(ADM)等。光同步数字传输系统中最基本的模块信号是STM-1信号，线速率为155.520Mbit/s，STM-N信号是将基本模块信号STM-1同步复用、经字节间插后的结果，线速率是N×155.520Mbit/s；这些信号在传输过程中都是按比特串行传送信号，但没有传送本节点的时钟信号。各节点的接收端所需的数据接收及后续处理的时钟都是从接收到的数据信号中恢复出来的。根据常用的时钟数据恢复(CDR)原理，时钟恢复是依靠数据信号的变化沿完成，如果接收到的数据流中有长连0或长连1序列出现，则按该原理恢复出的时钟不再精准，用这样恢复出来的时钟处理数据会导致数据信息的丢失或错误，因此为了保证在接收端能精准地进行数据接收和时钟提取，必须杜绝传输的数据流中有长连0或长连1序列出现。A synchronous digital transmission system generally consists of two basic devices, transmission equipment and network nodes. For an optical synchronous digital transmission system, the transmission equipment is an optical cable system, and the network nodes are more complex, including termination equipment (TM), cross-connect equipment (DXC), multiplexing device (ADM), etc. The most basic module signal in the optical synchronous digital transmission system is the STM-1 signal with a line rate of 155.520Mbit/s. The STM-N signal is the result of synchronously multiplexing the basic module signal STM-1 and interleaving bytes. The line rate is N×155.520Mbit/s; these signals are transmitted bit-serially during the transmission process, but the clock signal of the node is not transmitted. Clocks for data reception and subsequent processing required by the receiving end of each node are all recovered from the received data signals. According to the commonly used clock data recovery (CDR) principle, clock recovery is completed by changing the edge of the data signal. If there is a sequence of long consecutive 0s or long consecutive 1s in the received data stream, the clock recovered according to this principle is no longer Precise, using the recovered clock to process data will lead to loss or error of data information, so in order to ensure accurate data reception and clock extraction at the receiving end, it is necessary to prevent long-connected 0s or long-connected 1s in the transmitted data stream sequence appears.

为此国际电联组织(CCITT)在光同步数字传输系统的协议中规定：在发送端对传送的数据要进行加扰，加扰后的数据再经电/光转换后由光缆传送出去；在接收端对从光缆传来的信号进行光/电转换，对转换后的数据信号再进行时钟提取、数据接收、解扰以及后续处理。CCITT在协议G.709中还规定：对STM-N段开销的第一行的9×N个字节不进行扰码；一旦紧随STM-N段开销第一行最后一个字节的那个字节的最高位(MSB)一出现，扰码器应自动设置为“1111111”；扰码器的序列长度为127，工作在线路速率，生成多项式为1+X⁶+X⁷。For this reason, the International Telecommunications Union (CCITT) stipulates in the agreement of the optical synchronous digital transmission system: the transmitted data shall be scrambled at the sending end, and the scrambled data shall be transmitted by the optical cable after electrical/optical conversion; The receiving end performs optical/electrical conversion on the signal transmitted from the optical cable, and performs clock extraction, data reception, descrambling and subsequent processing on the converted data signal. CCITT also stipulates in the protocol G.709: the 9×N bytes of the first line of the STM-N section overhead will not be scrambled; once the word immediately following the last byte of the first line of the STM-N section overhead The scrambler should be automatically set to "1111111" as soon as the MSB of the stanza appears; the sequence length of the scrambler is 127, works at line rate, and the generator polynomial is 1+X⁶ +X⁷ .

ITU-T G.707 SDH网络节点接口中给出了帧同步扰码器的功能图，如图1所示。由图可知，7个D触发器用于移位，D触发器R1、R2、......、R6的输入端分别与上一个D触发器R0、R1、......、R5的输出端相连，CLK为STM-1帧线性时钟信号，Reset为定帧脉冲、置位信号；一个异或门用以实现对D触发器R6和R5的输出进行模2加即异或运算，运算结果反馈至D触发器R0的输入端，D触发器R6的输出即为扰码序列，它与STM-1帧的线速数据(比特格式)进行加/解扰的处理。从上述工作流程可分析得出：在正常处理阶段，每一位比特扰码都是来自7个时钟节拍前的模2加运算结果；在每个线速时钟节拍，R6输出1位比特扰码，在8个线速时钟节拍内，R6依次输出8位扰码。尽管这种扰码器电路结构简单，但由于其工作在线速率下，工作频率高导致生产工艺复杂，生产成本高，甚至在某些高频时钟下无法实现，因而在实际使用中该电路被取代已成为必然。ITU-T G.707 SDH network node interface provides a functional diagram of the frame synchronization scrambler, as shown in Figure 1. It can be seen from the figure that 7 D flip-flops are used for shifting, and the input terminals of D flip-flops R1, R2, ..., R6 are respectively connected with the previous D flip-flops R0, R1, ..., R5 CLK is the STM-1 frame linear clock signal, Reset is the frame-fixing pulse and setting signal; an exclusive OR gate is used to implement the modulo 2 addition or exclusive OR operation on the outputs of D flip-flops R6 and R5, The operation result is fed back to the input terminal of D flip-flop R0, and the output of D flip-flop R6 is the scrambling code sequence, which is added/descrambled with the wire-speed data (bit format) of the STM-1 frame. From the above workflow, it can be concluded that: in the normal processing stage, each bit scrambling code is the result of modulo 2 addition operation 7 clock beats ago; at each line speed clock beat, R6 outputs 1 bit scrambling code , within 8 line-speed clock beats, R6 outputs 8-bit scrambling codes in sequence. Although this kind of scrambler circuit has a simple structure, its production process is complicated and its production cost is high due to its high operating frequency at the line rate, and it cannot even be realized under certain high-frequency clocks, so the circuit is replaced in actual use. has become inevitable.

专利号为00114086.8的中国专利“光同步数字传输系统中的并行帧同步加/解扰码器”提供了一种并行帧同步加/解扰码器。该加/解扰码器由8个D触发器和8个异或门组成，1个带有复位端R的D触发器R0和7个带有置位端S的D触发器R1、......、R7，按序与8个两输入的异或门间插串联，D触发器R0的输入信号是D触发器R7和R6的输入信号经过异或门后的输出信号，D触发器R0的输出信号与R7的输入信号经过异或门后，作为D触发器R1的输入信号；D触发器R1与R0的输出信号经过异或门后，作为D触发器R2的输入信号；这样一直下去，D触发器R6与R5的输出信号经过异或门后，作为D触发器R7的输入信号；如此构成了一个反馈式的电路环路。CLKP是系统并行时钟信号，其频率为线速频率的1/8；Reset为定帧脉冲、置位复位信号，8个D触发器的输出端Q0～Q7依次输出相应的一个字节的扰码位(8BIT)。但是它只适用于并行速率比较低的数据。对于更高速率的数据，如STM-16，它的线速率为2.488Gbit/s，并行速率为311Mbit/s，如此之高的时钟速率当前的芯片制造工艺根本无法实现。The Chinese Patent No. 00114086.8 "Parallel Frame Synchronization Scrambler/Descrambler in Optical Synchronous Digital Transmission System" provides a parallel frame synchronization scrambler/descrambler. The scrambler/descrambler is composed of 8 D flip-flops and 8 XOR gates, 1 D flip-flop R0 with reset terminal R and 7 D flip-flops R1 with set terminal S, .. ...., R7, interleaved in series with 8 two-input XOR gates in sequence, the input signal of D flip-flop R0 is the output signal of the input signals of D flip-flop R7 and R6 after passing through the XOR gate, D trigger After the output signal of the device R0 and the input signal of R7 pass through the exclusive OR gate, they are used as the input signal of the D flip-flop R1; after the output signals of the D flip-flop R1 and R0 pass through the exclusive-or gate, they are used as the input signal of the D flip-flop R2; Going on, the output signals of D flip-flops R6 and R5 pass through the XOR gate and then serve as the input signal of D flip-flop R7; thus forming a feedback circuit loop. CLKP is the system parallel clock signal, and its frequency is 1/8 of the line speed frequency; Reset is the frame-setting pulse, reset signal, and the output terminals Q0~Q7 of the 8 D flip-flops output the corresponding one-byte scrambling code in sequence bit (8BIT). But it is only suitable for data with relatively low parallel rate. For higher rate data, such as STM-16, its line rate is 2.488Gbit/s, and its parallel rate is 311Mbit/s. Such a high clock rate cannot be realized by the current chip manufacturing process.

发明内容Contents of the invention

本发明的目的是为了克服现有技术中扰码器电路结构简单，仅允许工作在线速率下，工作频率高导致生产工艺复杂，生产成本高，甚至在某些高频时钟下芯片的制造工业无法实现等缺点，而提出一种SDH加/解扰码器。The purpose of the present invention is to overcome the simple structure of the scrambler circuit in the prior art, which only allows to work at the online rate, the high working frequency leads to complex production process, high production cost, and even the chip manufacturing industry cannot Realization and other shortcomings, and put forward a SDH plus / descrambler.

为了实现上述发明目的，本发明提出的一种SDH加/解扰码器包括：比特扰码电路，字节扰码电路，选择器，寄存器组1，寄存器组2，译码器1，译码器2，译码器3。比特扰码电路的输入来自寄存器组2的输出，结果输出到选择器的1端，字节扰码电路的输入来自寄存器组1的输出，结果输出到选择器的0端，选择器控制选择位来自译码器1的输出，其结果输出到寄存器组1，寄存器组1的使能位来自译码器2的输出，寄存器组1的输出就是整个扰码器电路的输出，同时也输出到寄存器组2和字节扰码电路，寄存器组2的使能位来自译码器3的输出。In order to realize the foregoing invention object, a kind of SDH adding/de-scrambling device that the present invention proposes comprises: bit scrambling code circuit, byte scrambling code circuit, selector, register set 1, register set 2, decoder 1, decoding Device 2, Decoder 3. The input of the bit scrambler circuit comes from the output of register group 2, and the result is output to terminal 1 of the selector. The input of the byte scramble circuit comes from the output of register group 1, and the result is output to terminal 0 of the selector, and the selector controls the selection bit The output from decoder 1, the result is output to register group 1, the enable bit of register group 1 comes from the output of decoder 2, the output of register group 1 is the output of the entire scrambler circuit, and it is also output to the register Group 2 and byte scrambling circuit, the enable bit of register group 2 comes from the output of decoder 3.

采用本发明所述的SDH加/解扰码器大大降低了处理速率，并简化了逻辑，使得的电路的规模大大降低，更易于工艺实现。The adoption of the SDH adding/descrambling device of the present invention greatly reduces the processing rate and simplifies the logic, so that the scale of the circuit is greatly reduced, and the process is easier to realize.

附图说明Description of drawings

图1...帧同步扰码器功能图；Figure 1...Functional diagram of frame synchronization scrambler;

图2...并行帧同步加/解扰码器功能图；Figure 2...Functional diagram of parallel frame synchronization adding/descrambling device;

图3...本发明所述的加/解扰码器功能图；Fig. 3... Functional diagram of the adding/de-scrambling device according to the present invention;

图4...本发明所述的加/解扰码器应用功能图。Fig. 4 ... the application function diagram of the scrambler/descrambler according to the present invention.

具体实施方式Detailed ways

下面结合附图对本发明的具体实施方式作进一步的描述。The specific embodiments of the present invention will be further described below in conjunction with the accompanying drawings.

在SDH中，STM-1(STS-3)、STM-4(STS-12)，都是字节间插的，而STM-16(STS-48)是4字节间插的，它的数据格式如表1所示，分成4路STM-4(STS-12)后如表2所示。这四路可以并行处理，处理方法也是一样的，不同的只是四路的初始值不同。第一路的初始值与一路STM-16的初始值相同，都是8′hfe。第二路的初始值是第一路初始值经过32次比特扰码变化的结果，即8′he4；同理，第三路的初始值是第二路初始值经过32次比特扰码变化的结果，即8′h1c；第四路的初始值是第三路初始值经过32次比特扰码变化的结果，即8′h8d。   0   1   2   3   4   5   6   7   8   9   10   11   12   13   14   15   16   17   18   19   20   21   22   23   24   25   26   27   28   29   30   31   32   33   34   35   36   37   38   39   40   41   42   43   44   45   46   47In SDH, STM-1 (STS-3) and STM-4 (STS-12) are interleaved by bytes, while STM-16 (STS-48) is interleaved by 4 bytes. Its data The format is shown in Table 1, and it is shown in Table 2 after being divided into 4 channels of STM-4 (STS-12). These four paths can be processed in parallel, and the processing method is the same, the only difference is that the initial values of the four paths are different. The initial value of the first path is the same as that of the STM-16 path, both are 8′hfe. The initial value of the second path is the result of the initial value of the first path undergoing 32 bit scrambling changes, that is, 8'he4; similarly, the initial value of the third path is the result of the initial value of the second path undergoing 32 bit scrambling changes The result is 8'h1c; the initial value of the fourth path is the result of 32 bit scrambling changes of the initial value of the third path, namely 8'h8d. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 twenty one twenty two twenty three twenty four 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

                             表1、STM-16字节数据格式   STM-4#1：   0   1   2   3   16   17   18   19   32   33   34   35   STM-4#2：   4   5   6   7   20   21   22   23   36   37   38   39   STM-4#3：   8   9   10   11   24   25   26   27   40   41   42   43   STM-4#4：   12   13   14   15   28   29   30   31   44   45   46   47Table 1, STM-16 byte data format STM-4#1: 0 1 2 3 16 17 18 19 32 33 34 35 STM-4#2: 4 5 6 7 20 twenty one twenty two twenty three 36 37 38 39 STM-4#3: 8 9 10 11 twenty four 25 26 27 40 41 42 43 STM-4#4: 12 13 14 15 28 29 30 31 44 45 46 47

                表2、STM-16拆分为4路STM-4数据          Table 2, STM-16 is split into 4 channels of STM-4 data

以第一路为例，在处理第0，1，2，3字节的时候，其处理方法和以前的字节扰码是一样的；当处理完第3字节时，就突然跳到了第16字节，这中间跳过了12个字节。但是若是从第0字节开始算，就是跳过了16个字节，即128次比特扰码，而扰码器的序列长度是127，也就是说经过127次比特扰码之后，扰码器就会恢复到初始值。所以128个比特扰码就是127+1，相当于1次比特扰码。所以只要在处理第0字节时，记下当时的扰码值，在处理第16字节时，就可以将记下的扰码进行一次比特扰码变化后使用。这样，就是每隔四个字节扰码器要进行一次跳变，但是却大大降低了处理的复杂度。Taking the first path as an example, when processing the 0, 1, 2, and 3 bytes, the processing method is the same as the previous byte scrambling code; when the 3rd byte is processed, it suddenly jumps to the 1st byte 16 bytes, 12 bytes were skipped in the middle. But if counting from the 0th byte, 16 bytes are skipped, that is, 128 bits of scrambling, and the sequence length of the scrambler is 127, that is to say, after 127 bits of scrambling, the scrambler will return to the initial value. Therefore, the 128-bit scrambling code is 127+1, which is equivalent to one bit scrambling code. Therefore, as long as the scrambling code value at that time is recorded when processing the 0th byte, when the 16th byte is processed, the recorded scrambling code can be used after one bit scrambling code change. In this way, the scrambler needs to perform a jump every four bytes, but the processing complexity is greatly reduced.

图3是本发明所述的加/解扰码器的功能图。它包括比特扰码电路，字节扰码电路，选择器，寄存器组1，寄存器组2，译码器1，译码器2，译码器3。比特扰码电路就是图1所示的电路，它的输入来自寄存器组2的输出，结果输出到选择器的1端。字节扰码电路就是图2所示的电路，它的输入来自寄存器组1的输出，结果输出到选择器的0端。选择器是一个二选一选择器，0端的输入来自比特扰码电路的输出，1端的输入来自字节扰码电路的输出，控制选择位来自译码器1的输出，控制选择位为0时选择0端，为1时选择1端，其结果输出到寄存器组1。寄存器组1的输入来自选择器的输出，使能位来自译码器2的输出，使能时输入就是其输出结果，否则初始化寄存器组，输出初始值。寄存器组1的输出就是整个译码器电路的输出，同时也输出到寄存器组2和字节扰码电路。寄存器组2的输入来自寄存器组1的输出，使能位来自译码器3的输出，使能时输入就是其输出结果，否则输出保持不变，寄存器组2的输出就是比特扰码电路的输入。译码器1的输入是间插计数器cnt_sts[3:0]，(cnt_sts[1:0]＝3)时输出为1，否则为0，结果输出到选择器的选择控制位。译码器2的输入是行计数器cnt_row[3:0]和列计数器cnt_col[6:0]，！(cnt_row＝0&&cnt_col＜＝2)时输出为1，否则为0，结果输出到寄存器组1的使能位。译码器3的输入是间插计数器cnt_sts[3:0]，(cnt_sts[1:0]＝0)时输出为1，否则为0，结果输出到寄存器组2的使能位。Fig. 3 is a functional diagram of a scrambler/descrambler according to the present invention. It includes a bit scrambling circuit, a byte scrambling circuit, a selector, a register set 1, a register set 2, a decoder 1, a decoder 2, and a decoder 3. The bit scrambling circuit is the circuit shown in Figure 1. Its input comes from the output of register group 2, and the result is output to terminal 1 of the selector. The byte scrambling circuit is the circuit shown in Figure 2, its input comes from the output of register group 1, and the result is output to the 0 terminal of the selector. The selector is a two-to-one selector. The input of terminal 0 comes from the output of the bit scrambling circuit, the input of terminal 1 comes from the output of the byte scrambling circuit, and the control selection bit comes from the output of decoder 1. When the control selection bit is 0 Select terminal 0, select terminal 1 when it is 1, and output the result to register group 1. The input of register group 1 comes from the output of the selector, and the enable bit comes from the output of decoder 2. When enabled, the input is the output result, otherwise, the register group is initialized and the initial value is output. The output of register group 1 is the output of the entire decoder circuit, and is also output to register group 2 and the byte scrambling circuit. The input of register group 2 comes from the output of register group 1, and the enable bit comes from the output of decoder 3. When enabled, the input is the output result, otherwise the output remains unchanged, and the output of register group 2 is the input of the bit scrambling circuit . The input of decoder 1 is the interleave counter cnt_sts[3:0], when (cnt_sts[1:0]=3), the output is 1, otherwise it is 0, and the result is output to the selection control bit of the selector. The input of decoder 2 is row counter cnt_row[3:0] and column counter cnt_col[6:0], ! (cnt_row=0&&cnt_col<=2), the output is 1, otherwise it is 0, and the result is output to the enable bit of register group 1. The input of the decoder 3 is the interleave counter cnt_sts[3:0], when (cnt_sts[1:0]=0), the output is 1, otherwise it is 0, and the result is output to the enable bit of the register group 2.

图4是本发明所述的加/解扰码器应用功能图。它由四个本发明所述加/解扰码器和四个异或门组成。四个加/解扰码器的输入都是行、列和间插计数器，结果分别输出到四个异或门的一端。四个加/解扰码器的初始值是不同的。第一路的初始值是8′hfe，第二路的初始值是8′he4；第三路的初始值是8′h1c；第四路的初始值是8′h8d。异或门的另一端输入分别是四路STM-4数据，异或门的输出分别是四路STM-4加/解扰后的数据。Fig. 4 is an application function diagram of the scrambler/descrambler according to the present invention. It consists of four adding/de-scrambling devices and four XOR gates described in the present invention. The inputs of the four adding/de-scrambling devices are row, column and interleave counters, and the results are respectively output to one end of the four exclusive OR gates. The initial values of the four scramblers/descramblers are different. The initial value of the first path is 8'hfe, the initial value of the second path is 8'he4; the initial value of the third path is 8'h1c; the initial value of the fourth path is 8'h8d. The input of the other end of the XOR gate is four channels of STM-4 data, and the output of the XOR gate is the data after four channels of STM-4 scrambling/descrambling respectively.

在发送端，处理完毕之后，并行进行加扰，然后将四路STM-4(STS-12)合成一路STM-16(STS-48)，再进行串并转换。在接收端，将一路STM-16(STS-48)拆分成4路STM-4(STS-12)，再并行进行解扰以及后续处理；这样，处理的时钟速率降低了1/32。At the sending end, after the processing is completed, scrambling is performed in parallel, and then four channels of STM-4 (STS-12) are synthesized into one channel of STM-16 (STS-48), and then serial-to-parallel conversion is performed. At the receiving end, split one STM-16 (STS-48) into four STM-4 (STS-12), and then perform descrambling and subsequent processing in parallel; in this way, the processing clock rate is reduced by 1/32.

该扰码器已经应用到芯片设计之中，并通过了FPGA测试，证明了该扰码器不仅可以正确的解决STM-16的扰码问题，而且可以大大降低处理的时钟频率，简化逻辑，更易于工艺实现。The scrambler has been applied to the chip design and passed the FPGA test, which proves that the scrambler can not only correctly solve the STM-16 scrambling problem, but also can greatly reduce the processing clock frequency, simplify logic, and more Easy to process.

Claims (7)

Translated fromChinese

1、一种SDH STM-16加/解扰码器，其特征在于，包括：比特扰码电路，字节扰码电路，选择器，寄存器组1，寄存器组2，译码器1，译码器2，译码器3；1, a kind of SDH STM-16 adds/de-scrambler, is characterized in that, comprises: bit scrambler circuit, byte scrambler circuit, selector, register group 1, register group 2, decoder 1, decoding Device 2, decoder 3;比特扰码电路的输入来自寄存器组2的输出，结果输出到选择器的1端，字节扰码电路的输入来自寄存器组1的输出，结果输出到选择器的0端，选择器控制选择位来自译码器1的输出，译码器1的输入来自间插计数器，选择器的结果输出到寄存器组1，寄存器组1的使能位来自译码器2的输出，译码器2的两个输入分别来自行计数器和列计数器，寄存器组1的输出就是整个扰码器电路的输出，同时也输出到寄存器组2和字节扰码电路，寄存器组2的使能位来自译码器3的输出，译码器3的输入来自间插计数器。The input of the bit scrambler circuit comes from the output of register group 2, and the result is output to terminal 1 of the selector. The input of the byte scramble circuit comes from the output of register group 1, and the result is output to terminal 0 of the selector, and the selector controls the selection bit The output from decoder 1, the input of decoder 1 comes from the interleave counter, the result of the selector is output to register group 1, the enable bit of register group 1 comes from the output of decoder 2, the two bits of decoder 2 The two inputs come from the row counter and the column counter respectively. The output of the register group 1 is the output of the entire scrambler circuit, and it is also output to the register group 2 and the byte scrambler circuit. The enable bit of the register group 2 comes from the decoder 3 The output of Decoder 3 comes from the interleaved counter.2、根据权利要求1所述的加/解扰码器，其特征在于，采用4个所述的加/解扰码器和4个异或门组成的扰码器对STM-16数据进行加/解扰码；2. The adding/descrambling device according to claim 1, characterized in that, the STM-16 data is added to the STM-16 data by using 4 said adding/descrambling devices and a scrambler composed of 4 XOR gates. / unscrambling code;将STM-16数据分成4路STM-4数据，4个加/解扰码器的输入都是行、列计数器和间插计数器，所述4个加/解扰码器的输出分别连接到4个异或门的一端；The STM-16 data is divided into 4 paths of STM-4 data, the inputs of the 4 add/descramblers are row, column counters and interleave counters, and the outputs of the 4 add/descramblers are respectively connected to 4 One end of an XOR gate;4个加/解扰码器的四路初始值依次为：第一路的初始值是8′hfe，第二路的初始值是8′he4；第三路的初始值是8′h1c；第四路的初始值是8′h8d。The initial values of the four paths of the 4 add/descramblers are as follows: the initial value of the first path is 8′hfe, the initial value of the second path is 8′he4; the initial value of the third path is 8′h1c; The initial value of four-way is 8′h8d.3、根据权利要求1或2所述的加/解扰码器，其特征在于，所述选择器是二选一选择器。3. The scrambler/descrambler according to claim 1 or 2, characterized in that the selector is an alternative selector.4、根据权利要求1或2所述的加/解扰码器，其特征在于，所述间插计数器为cnt_sts[3:0]。4. The scrambler/descrambler according to claim 1 or 2, wherein the interleave counter is cnt_sts[3:0].5、根据权利要求4所述的加/解扰码器，其特征在于，输入译码器1的间插计数器当cnt_sts[1:0]＝＝3时，输出为1，否则为0。5. The scrambler/descrambler according to claim 4, wherein the interleave counter input to the decoder 1 outputs 1 when cnt_sts[1:0]==3, otherwise it outputs 0.6、根据权利要求4所述的加/解扰码器，其特征在于，输入译码器3的间插计数器当cnt_sts[1:0]＝＝0时，输出为1，否则为0。6. The scrambler/descrambler according to claim 4, wherein the interleave counter input to the decoder 3 outputs 1 when cnt_sts[1:0]==0, otherwise it is 0.7、根据权利要求1或2所述的加/解扰码器，其特征在于，所述译码器2的输入是行计数器cnt_row[3:0]和列计数器cnt_col[6:0]，！(cnt_row＝＝0&&cnt_col＜＝2)时输出为1，否则为0。7. The scrambler/descrambler according to claim 1 or 2, characterized in that the input of the decoder 2 is a row counter cnt_row[3:0] and a column counter cnt_col[6:0], ! (cnt_row==0&&cnt_col<=2), the output is 1, otherwise it is 0.

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