CN1870757B

Movatterモバイル変換

Info

Publication number: CN1870757B
Application number: CN 200510074637
Authority: CN
Inventors: 斯蒂芬·戈登
Original assignee: Zyray Wireless Inc
Current assignee: Zyray Wireless Inc
Priority date: 2004-05-21
Filing date: 2005-05-23
Publication date: 2010-11-10
Anticipated expiration: 2025-05-23
Also published as: CN1870757A

Abstract

Translated fromChinese

本发明揭示了一种处理编码视频流的方法和系统。该方法包括在芯片上接收编码视频流内的打包数据。在所述芯片上确定所接收打包数据内的标识符，该标识符定义与该编码视频流中的信息包关联的多个编码类型之一。在所述芯片上基于所确定的标识符从多个解码方法中选择一解码方法。在所述芯片上使用所选解码方法解码编码视频流中所接收打包数据的至少一部分。确定所接收打包数据内的报头，该报头分隔编码视频流内的信息包。将所接收打包数据内的多个字节与确定字节序列相匹配。

The present invention discloses a method and system for processing coded video streams. The method includes receiving, on a chip, packetized data within an encoded video stream. An identifier within the received packetized data is determined on said chip, the identifier defining one of a plurality of encoding types associated with packets in the encoded video stream. A decoding method is selected on the chip from a plurality of decoding methods based on the determined identifier. At least a portion of the received packetized data in the encoded video stream is decoded on the chip using a selected decoding method. A header within the received packetized data that separates packets within the encoded video stream is determined. Matches a number of bytes within the received packed data to a determined sequence of bytes.

Description

Translated fromChinese

多标准视频解码器Multi-standard video codec

技术领域technical field

本发明涉及处理编码视频流的方法和系统。The present invention relates to methods and systems for processing encoded video streams.

背景技术Background technique

在视频信号编码过程中，一种或多种编码技术，如H.261、H.263、H.263+(Annex J)、H.264、SMPTE VC-1、MPEG-1、MPEG-2和/或MPEG-4，可被用于基于宏块挨着宏块进行编码该视频信号。在视频信号编码过程中，例如，同解码过程需要其他旁信息一样，预测错误信息可与预测模式信息一起编码。为编码预测错误信息，在量化或熵编码之前，可应用离散余弦变换将预测错误信息变换为频域信息。在该过程中，例如，有关预测错误的信息可能被丢失。该遗漏信息导致的结果是解码视频信号的质量下降。更特殊的是，例如，变换块效应可能以方格网人为因素的形式出现在解码视频中。其他也可能由于遗漏视频信息出现在解码视频中。In the video signal encoding process, one or more encoding technologies, such as H.261, H.263, H.263+ (Annex J), H.264, SMPTE VC-1, MPEG-1, MPEG-2 and and/or MPEG-4, may be used to encode the video signal on a macroblock-by-macroblock basis. During encoding of a video signal, for example, prediction error information may be encoded together with prediction mode information, as other side information is required for decoding. To encode prediction error information, the discrete cosine transform can be applied to transform the prediction error information into frequency domain information before quantization or entropy coding. In the process, for example, information about prediction errors may be lost. The result of this missing information is a reduction in the quality of the decoded video signal. More specifically, for example, transform blocking artifacts may appear in the decoded video as grid artifacts. Others may also appear in the decoded video due to missing video information.

传统视频解码器适于解码根据单一编码标准如H.261、E VC-1、MPEG-1、MPEG-2和/或MPEG-4等编码标准编码的基本视频流。基本视频流可用单一编码技术编码。然而，应用空间可支持正使用多种标准中的任一标准编码的码流。例如，高清晰度DVD播放装置的蓝光只读存储器规范允许视频流使用MPEG-2、H.264或VC-1编码。Legacy video decoders are adapted to decode elementary video streams encoded according to a single encoding standard such as H.261, EVC-1, MPEG-1, MPEG-2 and/or MPEG-4. Elementary video streams can be encoded with a single encoding technique. However, an application space may support codestreams that are being encoded using any of a variety of standards. For example, the Blu-ray ROM specification for high-definition DVD players allows video streams to be encoded using MPEG-2, H.264, or VC-1.

然而，因两个或更多解码器需要用于已依照不同编码标准编码的基本视频流的处理或解码，传统视频处理系统的解码效率大大降低。However, since two or more decoders are required for processing or decoding elementary video streams that have been encoded according to different encoding standards, the decoding efficiency of conventional video processing systems is greatly reduced.

通过以下结合附图对本发明的描述，将常规和传统方法与本发明进行比较，本技术领域的普通技术人员会更明了常规和传统方法的更多局限性和缺点。By comparing the conventional and traditional methods with the present invention through the following description of the present invention in conjunction with the accompanying drawings, those skilled in the art will understand more limitations and disadvantages of the conventional and traditional methods.

发明内容Contents of the invention

本发明提供了一种处理编码视频流的方法和系统的几个实施例。该方法一方面包括在芯片上接收编码视频流内的打包数据。所接收打包数据内的标识符可在该芯片上确定，在该芯片上该标识符可定义与该编码视频流中的信息包相关联的多个编码类型之一。解码方法可基于所确定的标识符，在该芯片上从多个解码方法中选择。编码视频流中该所接收打包数据的一部分可使用所选解码方法在该芯片上解码。分隔符可在所接收打包数据内确定，分隔编码视频流内的信息包。将所接收打包数据内的多个字节与确定字节序列相匹配。如果该多个字节与该确定字节序列相匹配，则从该所接收打包数据移除该多个字节。The present invention provides several embodiments of a method and system for processing encoded video streams. An aspect of the method includes receiving, on a chip, packetized data within an encoded video stream. An identifier within the received packetized data may be determined on the chip where the identifier may define one of a plurality of encoding types associated with packets in the encoded video stream. The decoding method can be selected on the chip from a plurality of decoding methods based on the determined identifier. A portion of the received packetized data in an encoded video stream can be decoded on the chip using a selected decoding method. A delimiter may be determined within the received packetized data, separating packets within the encoded video stream. Matches a number of bytes within the received packed data to a defined sequence of bytes. If the bytes match the determined sequence of bytes, the bytes are removed from the received packetized data.

如果所确定的标识符符合H.264视频编码，则所接收打包数据可用固定长度编码(fixed length coding，简称FLC)方法、可变长度编码(varible length coding，简称VLC)方法和/或上下文自适应二进制算法编码(context adaptive binary arithmetic coding，简称CABAC)方法解码。如果所确定的标识符符合VC-1、H.261、H.263、H.263+、MPEG-1、MPEG-2和/或MPEG-4视频编码，则所接收打包数据可用FLC方法和/或VLC方法解码。该解码的打包数据包括解码方法控制信息和/或预测错误信息。解码视频流可使用该解码的打包数据生成。该生成的解码视频流可使用重叠变换方法和/或解块方法滤波。对于每一该多个解码方法，所接收打包数据的一部分可用逆变换、逆量化和/或运动补偿在该芯片上解码。If the determined identifier conforms to H.264 video coding, the received packetized data can be encoded with a fixed length coding (FLC) method, a variable length coding (VLC) method and/or a context self Adaptive binary algorithm coding (context adaptive binary arithmetic coding, CABAC for short) method decoding. If the determined identifier conforms to VC-1, H.261, H.263, H.263+, MPEG-1, MPEG-2 and/or MPEG-4 video coding, the received packetized data can be used with the FLC method and/or Or VLC method to decode. The decoded packetized data includes decoding method control information and/or prediction error information. A decoded video stream may be generated using the decoded packetized data. The resulting decoded video stream may be filtered using lapped transform methods and/or deblocking methods. For each of the plurality of decoding methods, a portion of the received packetized data may be decoded on-chip with inverse transform, inverse quantization, and/or motion compensation.

本发明的另一个实施例提供了一种机器可读存储器，其上存储有计算机程序，该计算机程序具有至少机器可执行的代码部分，以使该机器可执行上述处理编码视频流的步骤。Another embodiment of the present invention provides a machine-readable memory on which is stored a computer program, the computer program having at least a machine-executable code portion to enable the machine to perform the above-mentioned steps of processing an encoded video stream.

本发明的一方面还包括至少一个处理器，在芯片上接收芯片上的编码视频流内的打包数据。该处理器可在该芯片上确定所接收打包数据内的标识符，该标识符定义与该编码视频流中的信息包相关联的多个编码类型之一。解码方法可基于所确定的标识符，由该处理器从多个解码方法中选择。编码视频流中该所接收打包数据的一部分可由该处理器使用所选解码方法进行解码。所接收打包数据内的分隔符，该分隔符由该处理器确定，分隔编码视频流内的信息包。该处理器可将所接收打包数据内的多个字节与确定字节序列相匹配，如果该多个字节与该确定字节序列相匹配，则该处理器从该所接收打包数据中移除该多个字节。An aspect of the invention also includes at least one processor receiving on-chip packetized data within the on-chip encoded video stream. The processor can determine, on the chip, an identifier within the received packetized data that defines one of a plurality of encoding types associated with packets in the encoded video stream. The decoding method may be selected by the processor from a plurality of decoding methods based on the determined identifier. A portion of the received packetized data in an encoded video stream may be decoded by the processor using a selected decoding method. A delimiter within the received packetized data, determined by the processor, that separates packets within the encoded video stream. The processor may match a plurality of bytes within the received packed data to a determined sequence of bytes, and if the plurality of bytes match the determined sequence of bytes, the processor removes the bytes from the received packed data Divide that many bytes.

如果所确定的标识符符合H.264视频编码，则所接收打包数据可由该处理器用固定长度编码方法、可变长度编码方法和/或上下文自适应二进制算法编码方法解码。如果所确定的标识符符合VC-1、H.261、H.263、H.263+、MPEG-1、MPEG-2和/或MPEG-4视频编码，则所接收打包数据可由该处理器用FLC方法和/或VLC方法解码。该解码的打包数据包括解码方法控制信息和/或预测错误信息。解码视频流可由处理器使用该解码的打包数据生成。该处理器可使用重叠变换方法和/或解块方法将该生成的解码视频流滤波。If the determined identifier conforms to H.264 video coding, the received packetized data may be decoded by the processor using a fixed-length coding method, a variable-length coding method and/or a context-adaptive binary algorithm coding method. If the determined identifier conforms to VC-1, H.261, H.263, H.263+, MPEG-1, MPEG-2 and/or MPEG-4 video coding, the received packetized data can be used by the processor with FLC method and/or VLC method decoding. The decoded packetized data includes decoding method control information and/or prediction error information. A decoded video stream may be generated by a processor using the decoded packetized data. The processor may filter the generated decoded video stream using a lapped transform method and/or a deblocking method.

本发明的一个方面提供了一种处理编码视频流的方法，该方法包括：One aspect of the invention provides a method of processing an encoded video stream, the method comprising:

在芯片上接收编码视频流内的打包数据；Receiving packetized data within an encoded video stream on-chip;

在所述芯片上确定所接收打包数据内的标识符，该标识符定义与该编码视频流中的信息包相关联的多个编码类型之一；determining on said chip an identifier within the received packetized data, the identifier defining one of a plurality of encoding types associated with packets in the encoded video stream;

在所述芯片上，基于所确定的标识符，从多个解码方法中选择一个解码方法；及selecting, on said chip, a decoding method from a plurality of decoding methods based on the determined identifier; and

在所述芯片上使用所选解码方法解码编码视频流中所接收打包数据的至少一部分。At least a portion of the received packetized data in the encoded video stream is decoded on the chip using a selected decoding method.

优选地，所述方法进一步包括在所述芯片上确定所接收打包数据内的起始码，该起始码分隔编码视频流内的信息包。Advantageously, the method further comprises determining on said chip a start code within the received packetized data, the start code delimiting packets within the encoded video stream.

优选地，所述方法进一步包括将所接收打包数据内的多个字节与一个确定字节序列相匹配。Advantageously, the method further comprises matching bytes within the received packetized data to a determined sequence of bytes.

优选地，所述方法进一步包括如果该多个字节与该确定字节序列相匹配，则从该所接收打包数据中移除该多个字节。Advantageously, the method further comprises removing the plurality of bytes from the received packetized data if the plurality of bytes match the determined sequence of bytes.

优选地，所述方法进一步包括如果所确定的标识符符合H.264视频编码，则使用固定长度编码(FLC)方法、可变长度编码(VLC)方法和上下文自适应二进制算法编码(CABAC)方法的至少其一解码所接收打包数据的所述至少一部分。Advantageously, the method further comprises using a Fixed Length Coding (FLC) method, a Variable Length Coding (VLC) method and a Context Adaptive Binary Algorithm Coding (CABAC) method if the determined identifier conforms to H.264 video coding At least one of the decodes the at least a portion of the received packetized data.

优选地，所述方法进一步包括如果所确定的标识符符合VC-1视频编码，则使用固定长度编码(FLC)方法和可变长度编码(VLC)方法的至少其一解码所接收打包数据的所述至少一部分。Advantageously, the method further comprises decoding said received packetized data using at least one of a fixed length coding (FLC) method and a variable length coding (VLC) method if the determined identifier complies with VC-1 video coding. at least part of it.

优选地，所述方法进一步包括如果所确定的标识符符合H.261、H.263、H.263+、MPEG-1、MPEG-2和MPEG-4视频编码至少之一，则使用固定长度编码(FLC)方法和可变长度编码(VLC)方法的至少其一解码所接收打包数据的所述至少一部分。Advantageously, the method further comprises using fixed length encoding if the determined identifier conforms to at least one of H.261, H.263, H.263+, MPEG-1, MPEG-2 and MPEG-4 video encoding At least one of a (FLC) method and a variable length coding (VLC) method decodes the at least a portion of the received packetized data.

优选地，所述解码打包数据包括预测像素信息和预测错误信息的至少其一。Preferably, the decoded packet data includes at least one of predicted pixel information and predicted error information.

优选地，所述方法进一步包括使用所述解码打包数据的至少一部分生成解码视频流。Advantageously, the method further comprises generating a decoded video stream using at least a portion of said decoded packetized data.

优选地，所述方法进一步包括，对每一所述多个解码过程，在所述芯片上使用逆变换、逆量化和运动补偿的至少其一解码所接收打包数据的所述至少一部分。Advantageously, the method further comprises, for each of said plurality of decoding processes, decoding said at least a portion of received packed data on said chip using at least one of inverse transform, inverse quantization and motion compensation.

根据本发明的一个方面，提供了一种机读存储器，存储具有至少一代码部分的计算机程序，以处理编码视频流，该至少一个代码部分由机器执行，执行的步骤包括：According to one aspect of the present invention, there is provided a machine-readable memory storing a computer program having at least one code portion for processing an encoded video stream, the at least one code portion is executed by a machine, and the executed steps include:

优选地，所述存储器进一步包括在所述芯片上确定所接收打包数据内的起始码的代码，所述起始码分隔编码视频流内的信息包。Advantageously, said memory further comprises code on said chip to determine a start code within received packetized data, said start code delimiting packets within an encoded video stream.

优选地，所述存储器进一步包括将所接收打包数据内的多个字节与一个确定字节序列相匹配的代码。Advantageously, said memory further comprises code for matching a plurality of bytes within received packed data to a defined sequence of bytes.

优选地，所述存储器进一步包括如果该多个字节与该确定字节序列相匹配，则从该所接收打包数据中移除该多个字节的代码。Advantageously, said memory further comprises code for removing said plurality of bytes from said received packed data if said plurality of bytes match said determined sequence of bytes.

优选地，所述存储器进一步包括如果所确定的标识符符合H.264视频编码，则使用固定长度编码(FLC)方法、可变长度编码(VLC)方法和上下文自适应二进制算法编码(CABAC)方法的至少其一解码所接收打包数据的所述至少一部分的代码。Advantageously, said memory further comprises using a Fixed Length Coding (FLC) method, a Variable Length Coding (VLC) method and a Context Adaptive Binary Algorithm Coding (CABAC) method if the determined identifier conforms to H.264 video coding At least one of the codes that decodes the at least a portion of the received packetized data.

优选地，所述存储器进一步包括如果所确定的标识符符合VC-1视频编码，则使用固定长度编码(FLC)方法和可变长度编码(VLC)方法的至少其一解码所接收打包数据的所述至少一部分的代码。Advantageously, said memory further comprises means for decoding received packetized data using at least one of a fixed length coding (FLC) method and a variable length coding (VLC) method if the determined identifier complies with VC-1 video coding. At least a portion of the code described above.

优选地，所述存储器进一步包括如果所确定的标识符符合H.261、H.263、H.263+、MPEG-1、MPEG-2和MPEG-4视频编码至少之一，则使用固定长度编码(FLC)方法和可变长度编码(VLC)方法的至少其一解码所接收打包数据的所述至少一部分代码。Advantageously, said memory further comprises if the determined identifier complies with at least one of H.261, H.263, H.263+, MPEG-1, MPEG-2 and MPEG-4 video coding, using fixed length coding At least one of a (FLC) method and a variable length coding (VLC) method decodes the at least a portion of the code of the received packetized data.

优选地，所述解码打包数据包括预测像素信息和预测错误信息的至少之一。Preferably, the decoded packet data includes at least one of predicted pixel information and predicted error information.

优选地，所述存储器进一步包括使用所述解码打包数据的至少一部分生成解码视频流的代码。Advantageously, said memory further comprises code for generating a decoded video stream using at least a portion of said decoded packetized data.

优选地，所述存储器进一步包括使用重叠变换方法和/或解块方法的至少之一滤波所生成的解码视频流的代码。Advantageously, said memory further comprises code for filtering the generated decoded video stream using at least one of a lapped transform method and/or a deblocking method.

本发明的一方面提供了一种处理编码视频流的系统，该系统包括：An aspect of the present invention provides a system for processing encoded video streams, the system comprising:

至少一个处理器，其在芯片上接收编码视频流内的打包数据；at least one processor receiving on-chip packetized data within the encoded video stream;

所述至少一个处理器在所述芯片上确定所接收打包数据内的标识符，该标识符定义与该编码视频流中的信息包相关联的多个编码类型之一；said at least one processor determines on said chip an identifier within the received packetized data that defines one of a plurality of encoding types associated with packets in the encoded video stream;

所述至少一个处理器在所述芯片上基于该确定的标识符从多个解码方法中选择一个解码方法；及said at least one processor selects a decoding method from a plurality of decoding methods on said chip based on the determined identifier; and

所述至少一个处理器在所述芯片上使用所选解码方法解码编码视频流中所接收打包数据的至少一部分。The at least one processor decodes on the chip at least a portion of the received packetized data in the encoded video stream using the selected decoding method.

优选地，所述至少一个处理器在所述芯片上确定所接收打包数据内的起始码，该起始码分隔编码视频流内的信息包。Advantageously, said at least one processor determines on said chip a start code within received packetized data, the start code delimiting packets within the encoded video stream.

优选地，所述至少一个处理器将所接收打包数据内的多个字节与一确定字节序列相匹配。Advantageously, said at least one processor matches a plurality of bytes within received packed data to a determined sequence of bytes.

优选地，如果该多个字节与该确定字节序列相匹配，所述至少一个处理器则从该所接收打包数据中移除该多个字节。Advantageously, said at least one processor removes said plurality of bytes from said received packetized data if said plurality of bytes match said determined sequence of bytes.

优选地，如果所确定的标识符符合H.264视频编码，所述至少一处理器则使用固定长度编码(FLC)方法、可变长度编码(VLC)方法和上下文自适应二进制算法编码(CABAC)方法至少之一解码所接收打包数据的所述至少一部分。Advantageously, said at least one processor uses a Fixed Length Coding (FLC) method, a Variable Length Coding (VLC) method and Context Adaptive Binary Algorithm Coding (CABAC) if the determined identifier is compliant with H.264 video coding At least one of the methods decodes the at least a portion of the received packetized data.

优选地，如果所确定的标识符符合VC-1视频编码，所述至少一个处理器则使用固定长度编码(FLC)方法和可变长度编码(VLC)方法的至少之一解码所接收打包数据的所述至少一部分。Advantageously, said at least one processor decodes the received packetized data using at least one of a fixed length coding (FLC) method and a variable length coding (VLC) method if the determined identifier is compliant with VC-1 video coding. said at least a portion.

优选地，如果所确定的标识符符合H.261、H.263、H.263+、MPEG-1、MPEG-2和MPEG-4视频编码至少之一，所述的至少一个处理器则使用固定长度编码(FLC)方法和可变长度编码(VLC)方法至少之一解码所接收打包数据的所述至少一部分。Preferably, said at least one processor uses fixed At least one of a length coding (FLC) method and a variable length coding (VLC) method decodes the at least a portion of the received packetized data.

优选地，所述解码打包数据包括预测像素信息和预测错误信息至少之一。Preferably, the decoded packet data includes at least one of predicted pixel information and predicted error information.

优选地，所述至少一处理器使用所述解码打包数据的至少一部分生成解码视频流。Advantageously, said at least one processor generates a decoded video stream using at least a portion of said decoded packetized data.

优选地，所述至少一处理器使用重叠变换方法和解块方法至少之一滤波所生成的解码视频流。Advantageously, said at least one processor filters the generated decoded video stream using at least one of a lapped transform method and a deblocking method.

根据本发明的一方面，其提供了一种处理编码视频流的方法，该方法包括：According to an aspect of the present invention, it provides a method of processing a coded video stream, the method comprising:

使用第一CPU解码来自编码视频流的报头信息；及decoding header information from the encoded video stream using the first CPU; and

当所述第一CPU解码所述报头信息时，使用第二CPU解码来自编码视频流的宏块信息。When the first CPU decodes the header information, a second CPU is used to decode macroblock information from the encoded video stream.

本发明的这些或其他特征和优点，将从以下结合附图对本发明的详细描述获得更全面地理解。These and other features and advantages of the present invention will be more fully understood from the following detailed description of the invention in conjunction with the accompanying drawings.

附图说明Description of drawings

图1是根据本发明的实施例的具有分隔符的封装视频有效载荷的结构图。FIG. 1 is a structural diagram of an encapsulated video payload with delimiters according to an embodiment of the present invention.

图2是根据本发明的实施例的示例性的基本视频流数据内的字节解除的结构图。FIG. 2 is a structural diagram of byte unpacking in exemplary elementary video stream data according to an embodiment of the present invention.

图3A是根据本发明的实施例的示例性的多标准视频解码器的高水平结构图。FIG. 3A is a high-level block diagram of an exemplary multi-standard video decoder according to an embodiment of the present invention.

图3B是根据本发明的实施例的示例性的使用单一CPU的多标准视频解码器的高水平结构图。3B is a high-level block diagram of an exemplary multi-standard video decoder using a single CPU according to an embodiment of the present invention.

图3C是根据本发明的实施例的示例性的使用CPU对的多标准视频解码器的高水平结构图。3C is a high-level block diagram of an exemplary multi-standard video decoder using a CPU pair according to an embodiment of the present invention.

图4A是根据本发明的实施例的示例性的具有硬件辅助块和单一CPU的多标准视频解码器的结构图。FIG. 4A is a block diagram of an exemplary multi-standard video decoder with hardware assistance blocks and a single CPU, according to an embodiment of the present invention.

图4B是根据本发明的实施例的示例性的具有硬件辅助块和CPU对的多标准视频解码器的结构示意图。FIG. 4B is a block diagram of an exemplary multi-standard video decoder with a hardware-assisted block and a CPU pair according to an embodiment of the present invention.

图5是根据本发明的实施例的示例性的当解码H.264视频数据时，图4所示多标准视频解码器的运行的结构图。FIG. 5 is a block diagram illustrating an exemplary operation of the multi-standard video decoder shown in FIG. 4 when decoding H.264 video data according to an embodiment of the present invention.

图6是根据本发明的实施例的示例性的当解码VC-1视频数据时，图4所示多标准视频解码器的运行的结构图。FIG. 6 is a block diagram illustrating an exemplary operation of the multi-standard video decoder shown in FIG. 4 when decoding VC-1 video data according to an embodiment of the present invention.

图7是根据本发明的实施例的示例性的当解码MPEG-1或PMEG-2视频数据时，图4所示多标准视频解码器的运行的结构图。FIG. 7 is a block diagram illustrating an exemplary operation of the multi-standard video decoder shown in FIG. 4 when decoding MPEG-1 or PMEG-2 video data according to an embodiment of the present invention.

图8是根据本发明的实施例的示例性的当解码MPEG-4视频数据时，图4所示多标准视频解码器的运行的结构图。FIG. 8 is a block diagram illustrating the operation of the multi-standard video decoder shown in FIG. 4 when decoding MPEG-4 video data according to an embodiment of the present invention.

图9是根据本发明的实施例的处理视频数据流的示范性方法的流程图。9 is a flowchart of an exemplary method of processing a video data stream according to an embodiment of the present invention.

具体实施方式Detailed ways

本发明提供了一种处理编码视频流的方法和系统的几个实施例。在视频流编码过程中，不同编码标准可被用于基本视频流内进行编码数据。在本发明的一个方面中，多标准视频解码器可适于获得根据编码标准如H.261、H.263、H.263+(Annex J)、H.264、VC-1、MPEG-1、MPEG-2和/或MPEG-4编码的基本视频流。该多标准解码器可在该基本视频流内设置一个或多个分隔符，在该基本视频流内该分隔符可分隔封装视频有效载荷内的信息包。每一分隔符包括表明视频有效载荷的开始的起始码信息和编码类型信息。The present invention provides several embodiments of a method and system for processing encoded video streams. During encoding of the video stream, different encoding standards may be used to encode data within the elementary video stream. In one aspect of the present invention, the multi-standard video decoder can be adapted to obtain data according to encoding standards such as H.261, H.263, H.263+(Annex J), H.264, VC-1, MPEG-1, MPEG-2 and/or MPEG-4 encoded elementary video stream. The multi-standard decoder can set one or more delimiters within the elementary video stream, where the delimiters can separate packets within an encapsulated video payload. Each delimiter includes start code information indicating the start of video payload and encoding type information.

该编码类型信息可与被编码器用于编码相应视频有效载荷的编码方法相关联。该多标准解码器也可从封装视频有效载荷中解除或移除一个或多个字节，在封装视频有效载荷中这样的字节被编码器插入以避免错误的起始码出现在视频有效载荷中。根据该编码类型信息，封装视频有效载荷可在芯片上使用相应解码模块解码。例如，时间或空间预测像素可在封装视频有效载荷中从解码方法控制信息生成。此外，预测错误可在封装视频有效载荷内从量化频率系数生成。然后，可使用时间和/或空间预测像素和预测错误信息重建解码视频流。根据本发明的一个方面，该多标准解码器可使用单中央处理器(central processing unit，简称CPU)处理编码比特流中的信息包内的报头信息和宏块信息。在本发明的另一个方面中，可使用CPU对，其中第一CPU可处理未来报头信息，而第二CPU可处理当前宏块信息。The encoding type information may be associated with the encoding method used by the encoder to encode the corresponding video payload. The multi-standard decoder may also strip or remove one or more bytes from the encapsulated video payload where such bytes are inserted by the encoder to avoid false start codes in the video payload middle. Based on this encoding type information, the encapsulated video payload can be decoded on-chip using the corresponding decoding module. For example, temporally or spatially predicted pixels can be generated from decoding method control information in the encapsulated video payload. Furthermore, prediction errors can be generated from quantized frequency coefficients within the encapsulated video payload. The decoded video stream can then be reconstructed using temporally and/or spatially predicted pixels and prediction error information. According to an aspect of the present invention, the multi-standard decoder may use a single central processing unit (CPU for short) to process header information and macroblock information in packets in the coded bitstream. In another aspect of the invention, a pair of CPUs can be used, where a first CPU can process future header information and a second CPU can process current macroblock information.

图1是根据本发明的实施例的具有分隔符的封装视频有效载荷100的结构图。如图1所示，该封装视频有效载荷100包括分隔符104和基本视频流数据105。该分隔符104包括起始码101和起始码后缀103，且可被解码器用于如为封装视频有效载荷100设起始位及为基本视频流数据105设起始位。此外，分隔符104包括与用于编码基本视频流数据105的编码方法相关的信息。该基本视频流数据包括多个字节，每一字节包括两个半位元组。FIG. 1 is a structural diagram of an encapsulatedvideo payload 100 with delimiters according to an embodiment of the present invention. As shown in FIG. 1 , the encapsulatedvideo payload 100 includes adelimiter 104 and elementaryvideo stream data 105 . Thedelimiter 104 includes astart code 101 and astart code suffix 103 and can be used by a decoder, eg, to set the start bit for the encapsulatedvideo payload 100 and to set the start bit for the elementaryvideo stream data 105 . Furthermore, thedelimiter 104 includes information related to the encoding method used to encode the elementaryvideo stream data 105 . The elementary video stream data includes a plurality of bytes, and each byte includes two nibbles.

起始码101包括多个字节，可被安排以唯一组合表示编码视频流内封装视频有效载荷100的开始。例如，起始码101包括示范性字节序列“00 00 01”。起始码后缀103包括一个或多个字节，设于封装视频有效载荷100内的起始码101后。在本发明的一个方面中，该起始码后缀103与用于封装视频有效载荷100内的编码基本视频流数据105的编码方法相对应。例如，当这些编码方法被用于编码基本视频流数据105时，该起始码后缀103可相应于H.264、VC-1、MPEG-1、MPEG-2和/或MPE-4。在将该编码视频流数据传送至视频解码器前，起始码101和起始码后缀103可由编码器生成。Thestart code 101 comprises a plurality of bytes that can be arranged in a unique combination to represent the start of the encapsulatedvideo payload 100 within the encoded video stream. For example, startcode 101 includes the exemplary byte sequence "00 00 01". Thestart code suffix 103 includes one or more bytes and is set after thestart code 101 in the encapsulatedvideo payload 100 . In one aspect of the invention, thestart code suffix 103 corresponds to the encoding method used to encapsulate the encoded elementaryvideo stream data 105 within thevideo payload 100 . For example, when these encoding methods are used to encode the elementaryvideo stream data 105, thestart code suffix 103 may correspond to H.264, VC-1, MPEG-1, MPEG-2 and/or MPE-4. Thestart code 101 and thestart code suffix 103 may be generated by the encoder before transmitting the encoded video stream data to the video decoder.

图2是根据本发明的实施例的示例性的基本视频流数据内的字节解除的结构图。如图2所示，基本视频流数据200包括基本视频数据序列201和203。该基本视频流数据200可被分隔符加上前言，包括起始码序列和起始码后缀，如图1所示。在视频信号编码过程中以及编码器为该基本视频流数据200生成分隔符后，该编码器可在基本视频流数据200中插入一个或多个字节，以使编码期间相应起始码序列在基本视频流数据200内可能不被编码器识别。FIG. 2 is a structural diagram of byte unpacking in exemplary elementary video stream data according to an embodiment of the present invention. As shown in FIG. 2 , elementaryvideo stream data 200 includes elementaryvideo data sequences 201 and 203 . The elementaryvideo stream data 200 may be preambled by a delimiter, including a start code sequence and a start code suffix, as shown in FIG. 1 . During video signal encoding and after the encoder generates a delimiter for the elementaryvideo stream data 200, the encoder may insert one or more bytes in the elementaryvideo stream data 200, so that the corresponding start code sequence is Elementaryvideo stream data 200 may not be recognized by the encoder.

例如，在基本视频流数据200编码期间，编码器可使用包括字节序列“00 00 01”的起始码。在基本视频流数据200解码期间，解码器可能错误识别基本视频流数据200内的起始码序列“00 00 01”。为避免起始码序列的任何这种误识别，编码器可插入一个或多个额外字符或符号，或填充字节，以使得解码期间起始码序列在基本视频流数据200内不被误识别。例如，额外字符串或填充字节“03”可被插入基本视频数据序列201内的字节序列205内。同样的，填充字节“03”也可被插入基本视频数据序列203内的字节序列207内。以这种方式，可阻止解码器在基本视频流200解码期间识别起始码“00 00 01”For example, during encoding of the elementaryvideo stream data 200, the encoder may use a start code comprising the byte sequence "00 00 01". During decoding of the elementaryvideo stream data 200, the decoder may misidentify the start code sequence "00 00 01" within the elementaryvideo stream data 200. To avoid any such misidentification of the start code sequence, the encoder may insert one or more extra characters or symbols, or stuffing bytes, so that the start code sequence is not misidentified within the elementaryvideo stream data 200 during decoding . For example, an extra character string or stuffing bytes "03" may be inserted into thebyte sequence 205 within the basevideo data sequence 201 . Likewise, stuffing bytes “03” can also be inserted into thebyte sequence 207 in the elementaryvideo data sequence 203 . In this way, the decoder is prevented from recognizing the start code "00 00 01" during decoding of theelementary video stream 200

在基本视频流200解码过程中，视频解码器可解除或移除编码过程中被插入基本视频流200中的任何额外字符。因此，额外字符串“03”可被从基本视频数据序列201内的字节序列205移除，额外字符“2”可被从基本视频数据序列203内的字节序列207移除。以这种方式，基本视频流200内移除任何额外字符后，生成未处理的视频有效载荷。而后，该得到的未处理的视频有效载荷可由例如符号翻译器解码。During the decoding of theelementary video stream 200 , the video decoder may undo or remove any extra characters inserted into theelementary video stream 200 during the encoding. Therefore, the extra character string “03” can be removed from thebyte sequence 205 within the basevideo data sequence 201 , and the extra character “2” can be removed from thebyte sequence 207 within the basevideo data sequence 203 . In this way, the raw video payload is generated after removing any extra characters within theelementary video stream 200 . This resulting raw video payload can then be decoded by, for example, a symbol translator.

图3A是根据本发明的实施例的示例性多标准视频解码器的高水平结构图。如图3所示，该多标准视频解码器200可包括存储块301、端口编码器(code-in-port，CIP)305、码流解析器307和处理模块303。该端口编码器305包括适合的电路、逻辑和/或代码，适于获得基本视频流309。端口编码器305还可适于在基本视频流309内设起始码和起始码后缀，及从基本视频流309解除额外字节，由此生成未处理的基本视频流。Figure 3A is a high-level block diagram of an exemplary multi-standard video decoder according to an embodiment of the present invention. As shown in FIG. 3 , themulti-standard video decoder 200 may include astorage block 301 , a port coder (code-in-port, CIP) 305 , acode stream parser 307 and aprocessing module 303 . Theport encoder 305 includes suitable circuitry, logic and/or code adapted to obtain anelementary video stream 309 . Theport encoder 305 may also be adapted to place a start code and a start code suffix within theelementary video stream 309, and strip extra bytes from theelementary video stream 309, thereby generating a raw elementary video stream.

该多标准视频解码器300可使用码流解析器307处理起始码信息和可从端口编码器305获得的新码流信息。例如，码流解析器307可适于处理来自端口编码器305生成的未处理的基本比特流的报头信息和/或宏块信息。来自未处理的基本视频流的报头信息包括如片段信息、画面信息、GOP/切入点信息和/或序列信息。端口编码器305生成的该未处理的基本视频流内的片段信息包包括相应于特定片段的片段报头信息和宏块信息。此外，码流解析器307可适于处理从端口编码器305获得的未处理的基本码流中的报头和/或宏块信息，并生成例如该未处理的基本视频流中的宏块信息解码所需的量化的频率系数信息和/或附加旁信息。Themulti-standard video decoder 300 can use thecode stream parser 307 to process the start code information and the new code stream information obtained from theport encoder 305 . For example, thecodestream parser 307 may be adapted to process header information and/or macroblock information from the raw elementary bitstream generated by theport encoder 305 . The header information from the raw elementary video stream includes, for example, segment information, picture information, GOP/point cut information and/or sequence information. The slice information packets within the raw elementary video stream generated by theport encoder 305 include slice header information and macroblock information corresponding to a specific slice. Furthermore, thecodestream parser 307 may be adapted to process header and/or macroblock information in the unprocessed elementary stream obtained from theport encoder 305, and generate, for example, macroblock information decoded in the unprocessed elementary video stream The desired quantized frequency coefficient information and/or additional side information.

码流解析器307包括针对每种编码模式的一个或多个解码辅助块，可用于解码该未处理的基本视频流。来自码流解析器307的输出信号可通过总线311被传送到处理模块303。该总线311可在该多标准视频解码器内实现，作为一路总线将信息传送至处理模块303，以增加处理效率和简化执行过程。该未处理的基本视频流解码过程生成的时间信息可被存储模块301中的码流解析器307和/或端口编码器305存储。该存储模块301包括DRAM。Thecodestream parser 307 includes one or more decoding auxiliary blocks for each coding mode, which can be used to decode the raw elementary video stream. The output signal from thecodestream parser 307 can be transmitted to theprocessing module 303 through thebus 311 . Thebus 311 can be implemented in the multi-standard video decoder as a bus to transmit information to theprocessing module 303 to increase processing efficiency and simplify the execution process. The time information generated by the unprocessed elementary video stream decoding process can be stored by thecode stream parser 307 and/or theport encoder 305 in thestorage module 301 . Thestorage module 301 includes DRAM.

在本发明示范性的一个方面中，该码流解析器307可使用单一CPU和单一相应符号翻译器(SI)实现。该单一CPU或SI配置可用于处理包括起始码/后缀、报头信息和/或宏块信息的完整基本视频流。在本发明的另一个方面中，码流解析器307可使用两个单独的CPU和符号翻译器(SI)实现，以提高处理效率。例如，在示范性双CPU/SI结构中，第一CPU和第一SI可用于处理基本视频流中的报头信息，具有相应第二SI的第二CPU可用于处理来自基本比特流的宏块信息。在这一点上，后续报头信息可被第一CPU和第一SI处理，而第二CPU和第二SI可同时处理当前宏块信息。In an exemplary aspect of the present invention, thecodestream parser 307 can be implemented using a single CPU and a single corresponding symbol translator (SI). This single CPU or SI configuration can be used to process a complete elementary video stream including start code/suffix, header information and/or macroblock information. In another aspect of the present invention, thecode stream parser 307 can be implemented using two separate CPUs and a symbol translator (SI) to improve processing efficiency. For example, in an exemplary dual CPU/SI architecture, a first CPU and a first SI can be used to process header information in an elementary video stream, and a second CPU with a corresponding second SI can be used to process macroblock information from an elementary bitstream . At this point, the subsequent header information can be processed by the first CPU and the first SI, while the second CPU and the second SI can simultaneously process the current macroblock information.

处理模块303可使用由码流解析器307生成的处理信息生成解码视频流313。该处理模块303包括适合的电路、逻辑和/或代码，并可适于执行一个或多个以下处理任务：空间预测、运动补偿、逆量化和变换、宏块重建、回路内宏块滤波和/或宏块后处理。处理模块303中的每一处理任务可使用一个或多个辅助块，该辅助块符合被用于编码基本视频流33 1的特定编码方法。在这一点上，处理模块303可适于解码使用多个编码方法如H.261、H.263、H.263+(Annex J)、H.264、VC-1、MPEG-1、MPEG-2和/或MPEG-4之一编码的基本视频流。Theprocessing module 303 may use the processing information generated by thecodestream parser 307 to generate a decodedvideo stream 313 . Theprocessing module 303 includes suitable circuitry, logic, and/or code, and may be adapted to perform one or more of the following processing tasks: spatial prediction, motion compensation, inverse quantization and transformation, macroblock reconstruction, in-loop macroblock filtering, and/or or macroblock postprocessing. Each processing task in theprocessing module 303 may use one or more auxiliary blocks conforming to the particular encoding method used to encode theelementary video stream 331. In this regard, theprocessing module 303 may be adapted to decode codes using multiple encoding methods such as H.261, H.263, H.263+ (Annex J), H.264, VC-1, MPEG-1, MPEG-2 and/or one of the MPEG-4 encoded elementary video streams.

图3B是根据本发明的实施例的示例性的使用单一CPU的多标准视频解码器320的高水平结构图。如图3B所示，该多标准视频解码器320包括存储模块321、端口编码器329、内部回路中央处理器(ILCPU)325、内部回路符号翻译器(ILSI)327和处理模块323。该端口编码器329包括适合的电路、逻辑和/或代码，并适于获得基本视频流331。该端口编码器329也可适于在该基本视频流331内设起始码和/或起始码后缀，并从该基本视频流331解除额外字节，从而生成未处理的基本视频流。FIG. 3B is a high-level block diagram of an exemplarymulti-standard video decoder 320 using a single CPU, according to an embodiment of the present invention. As shown in FIG. 3B , themulti-standard video decoder 320 includes astorage module 321 , aport encoder 329 , an inner loop central processing unit (ILCPU) 325 , an inner loop symbol translator (ILSI) 327 and aprocessing module 323 . Theport encoder 329 includes suitable circuitry, logic and/or code and is adapted to obtain anelementary video stream 331 . Theport encoder 329 may also be adapted to place a start code and/or start code suffix within theelementary video stream 331 and strip extra bytes from theelementary video stream 331, thereby generating a raw elementary video stream.

在本发明的一个示范性实施例中，该多标准视频解码器320可使用内部回路中央处理器325和内部回路符号翻译器327处理来自端口编码器329生成的未处理的基本比特流的报头信息和/或宏块信息。来自未处理的基本比特流的报头信息包括如片段信息、画面信息、GOP/切入点信息和/或序列信息。端口编码器329生成的未处理的基本视频流内的片段信息包包括相应于特定片段的片段报头信息和宏块信息。In an exemplary embodiment of the present invention, themulti-standard video decoder 320 may use an inner-loop CPU 325 and an inner-loop symbol translator 327 to process the header information from the raw elementary bitstream generated by theport encoder 329 and/or macroblock information. The header information from the unprocessed elementary bitstream includes, for example, segment information, picture information, GOP/pointcut information and/or sequence information. The slice information packets within the raw elementary video stream generated by theport encoder 329 include slice header information and macroblock information corresponding to a specific slice.

内部回路符号翻译器327包括适合的电路、逻辑和/或代码，并可适于处理从端口编码器329获得的未处理的基本视频流中的报头和/或宏块信息，并生成如该未处理的基本视频流中的宏块信息解码所需的量化的频率系数信息和/或附加旁信息。该内部回路符号翻译器327包括一个或多个特定于使用的每一编码模式的解码辅助模块，以解码该未处理的基本视频流。Intra-loop symbol translator 327 includes suitable circuitry, logic, and/or code, and may be adapted to process header and/or macroblock information in the raw elementary video stream obtained fromport encoder 329, and generate Quantized frequency coefficient information and/or additional side information required for decoding macroblock information in the processed elementary video stream. The in-loop symbol translator 327 includes one or more decoding helper modules specific to each encoding mode used to decode the raw elementary video stream.

内部回路中央处理器325可适于通过如通过总线333提供向内部回路符号翻译器327提供解码指令将内部回路符号翻译器327程序化。该总线333可在该多标准视频解码器内实现，作为一路总线将信息传送至处理模块303，以增加处理效率和简化执行过程。该未处理的基本视频流解码过程生成的时间信息可被存储模块321中的内部回路中央处理器325、端口编码器329和/或内部回路符号翻译器327存储。该存储模块301包括DRAM。Inner-loop CPU 325 may be adapted to program inner-loop symbol translator 327 by providing decode instructions to inner-loop symbol translator 327 , eg, viabus 333 . Thebus 333 can be implemented in the multi-standard video decoder as a bus to transmit information to theprocessing module 303 to increase processing efficiency and simplify the execution process. The time information generated by the raw elementary video stream decoding process may be stored by theinner loop CPU 325 , theport encoder 329 and/or the innerloop symbol translator 327 in thestorage module 321 . Thestorage module 301 includes DRAM.

在操作过程中，输入的基本视频流331包括根据多个编码标准如H.261、H.263、H.263+(Annex J)、H.264、VC-1、MPEG-1、MPEG-2和/或MPEG-4之一编码的视频数据。端口编码器329可适于检测一个或多个符合该基本视频流331编码模式的起始码和起始码后缀。该端口编码器329还适于生成包括报头和/或宏块信息的未处理的基本视频流。该起始码和未处理的基本视频流可通过存储器321传送至内部回路中央处理器325和内部回路符号翻译器327，以进行进一步处理。该内部回路符号翻译器327，使用来自内部回路中央处理器325的指令，可适于处理端口编码器329传送的报头和/或宏块信息。然后，该内部回路符号翻译器327可生成输出信号，该输出信号包括如获得的宏块类型信息、片段类型信息、预测模式信息、运动矢量信息和/或量化频率系数。该输出信号可通过总线333传送至处理模块323，在宏块解码期间使用。During operation, the inputelementary video stream 331 includes codes according to multiple encoding standards such as H.261, H.263, H.263+ (Annex J), H.264, VC-1, MPEG-1, MPEG-2 and/or one of the MPEG-4 encoded video data. Theport encoder 329 may be adapted to detect one or more start codes and start code suffixes conforming to the encoding mode of theelementary video stream 331 . Theport encoder 329 is also adapted to generate a raw elementary video stream including header and/or macroblock information. The start code and unprocessed elementary video stream can be sent to theinner loop CPU 325 and the innerloop symbol translator 327 through thememory 321 for further processing. The in-loop symbol translator 327, using instructions from the in-loop CPU 325, may be adapted to process header and/or macroblock information transmitted by theport encoder 329. Theintra-loop sign translator 327 may then generate an output signal comprising macroblock type information, slice type information, prediction mode information, motion vector information and/or quantized frequency coefficients as obtained. The output signal may be transmitted to theprocessing module 323 via thebus 333 for use during macroblock decoding.

处理模块323可使用内部回路符号翻译器327生成的处理信息生成解码视频流335。该处理模块323包括适合的电路、逻辑和/或代码，适于执行一个或多个以下处理任务：空间预测、运动补偿、逆量化和变换、宏块重建、回路内宏块滤波和/或宏块后处理。处理模块323内的每一处理任务可使用一个或多个辅助块，该辅助块符合被用于编码基本视频流331的特定编码方法。在这一点上，处理模块323可适于解码使用多个编码方法如H.261、H.263、H.263+(Annex J)、H.264、VC-1、MPEG-1、MPEG-2和/或MPEG-4之一编码的基本视频流。Processing module 323 may generate decodedvideo stream 335 using the processing information generated by in-loop symbol translator 327 . Theprocessing module 323 includes suitable circuitry, logic, and/or code adapted to perform one or more of the following processing tasks: spatial prediction, motion compensation, inverse quantization and transformation, macroblock reconstruction, in-loop macroblock filtering, and/or macroblock Block postprocessing. Each processing task within theprocessing module 323 may use one or more auxiliary blocks that conform to the particular encoding method used to encode theelementary video stream 331 . In this regard, theprocessing module 323 may be adapted to decode codes using multiple encoding methods such as H.261, H.263, H.263+ (Annex J), H.264, VC-1, MPEG-1, MPEG-2 and/or one of the MPEG-4 encoded elementary video streams.

图3C是根据本发明的实施例的示例性的使用CPU对的多标准视频解码器340的高水平结构图。如图3C所示，该多标准视频解码器340可包括存储模块341、外部回路中央处理器(OLCPU)349、端口编码器(CPI)351、外部回路符号翻译器(OLSI)353、内部回路中央处理器(ILCPU)345、内部回路符号翻译器(OLSI)347和处理模块343。该端口编码器351包括适合的电路、逻辑和/或代码，并适于获得基本视频流355。该端口编码器329也可适于在该基本视频流355内设起始码和/或起始码后缀，并从该基本视频流355解除额外字节，从而生成未处理的基本视频流。FIG. 3C is a high-level block diagram of an exemplarymulti-standard video decoder 340 using CPU pairs according to an embodiment of the present invention. As shown in Figure 3C, themulti-standard video decoder 340 may include astorage module 341, an outer loop central processing unit (OLCPU) 349, a port encoder (CPI) 351, an outer loop symbol translator (OLSI) 353, an inner loop central Processor (ILCPU) 345 , Internal Loop Symbol Interpreter (OLSI) 347 andProcessing Module 343 . Theport encoder 351 includes suitable circuitry, logic and/or code and is adapted to obtain anelementary video stream 355 . Theport encoder 329 may also be adapted to place a start code and/or start code suffix within theelementary video stream 355 and strip extra bytes from theelementary video stream 355, thereby generating a raw elementary video stream.

在本发明的一个示范性实施例中，该多标准视频解码器320可使用CPU对，如内部回路中央处理器345和外部回路中央处理器349，具有相应的内部回路符号翻译器347、外部回路符号翻译器353，以分别处理来自端口编码器351生成的未处理的基本比特流的报头信息和/或宏块信息。来自未处理的基本比特流的报头信息可包括如片段信息、画面信息、GOP/切入点信息和/或序列信息。端口编码器351生成的新基本视频流内的片段信息包包括相应于特定片段的片段报头信息和宏块信息。例如，外部回路中央处理器349和外部回路符号翻译器353可适于处理来自端口编码器351生成的新基本比特流的报头信息。此外，内部回路中央处理器345和内部回路符号翻译器347可适于处理来自端口编码器351生成的未处理的基本比特流的宏块信息。以这种方式，可在多标准视频解码器340中实现平行处理，当外部回路中央处理器349和外部回路符号翻译器353处理未来报头信息时，内部回路中央处理器345和内部回路符号翻译器347可处理当前宏块信息。In an exemplary embodiment of the present invention, themulti-standard video decoder 320 may use a pair of CPUs, such as an inner-loopcentral processing unit 345 and an outer-loopcentral processing unit 349, with corresponding inner-loop symbol translators 347, outer-loop A symbol translator 353 to process header information and/or macroblock information from the unprocessed elementary bitstream generated by theport encoder 351, respectively. Header information from an unprocessed elementary bitstream may include, for example, segment information, picture information, GOP/pointcut information and/or sequence information. The slice information packet within the new elementary video stream generated by theport encoder 351 includes slice header information and macroblock information corresponding to a specific slice. For example,outer loop CPU 349 and outer loop symbol translator 353 may be adapted to process header information from the new elementary bitstream generated byport encoder 351 . Additionally, theintra-loop CPU 345 and theintra-loop symbol translator 347 may be adapted to process macroblock information from the raw elementary bitstream generated by theport encoder 351 . In this way, parallel processing can be achieved in themulti-standard video decoder 340, while theouter loop CPU 349 and the outer loop symbol translator 353 process future header information, theinner loop CPU 345 and the innerloop symbol translator 347 can process current macroblock information.

内部回路符号翻译器347包括适合的电路、逻辑和/或代码，并可适于处理从端口编码器351获得的未处理的基本视频流中的宏块信息，并生成如该未处理的基本视频流中的宏块信息解码所需的量化的频率系数信息和/或附加旁信息。该内部回路符号翻译器347包括一个或多个特定于使用的每一编码模式的解码辅助模块，以解码该未处理的基本视频流。外部回路符号翻译器353包括适合的电路、逻辑和/或代码，并可适于处理从端口编码器351获得的未处理的基本视频流中的报头信息。Intra-loop symbol translator 347 includes suitable circuitry, logic, and/or code, and may be adapted to process macroblock information in the raw elementary video stream obtained fromport encoder 351, and generate the raw elementary video stream as Quantized frequency coefficient information and/or additional side information required for decoding macroblock information in the stream. The in-loop symbol translator 347 includes one or more decoding helper modules specific to each encoding mode used to decode the raw elementary video stream. The outer loop symbol translator 353 includes suitable circuitry, logic and/or code, and may be adapted to process header information in the raw elementary video stream obtained from theport encoder 351 .

内部回路中央处理器345可适于通过如通过总线357向内部回路符号翻译器347提供解码指令将内部回路符号翻译器347程序化。该总线357可在该多标准视频解码器内实现，作为一路总线将信息传送至处理模块343，以增加处理效率和简化执行过程。该未处理的基本视频流解码过程生成的时间信息可被存储模块341中的内部回路中央处理器345、外部回路中央处理器349、外部回路符号翻译器353、端口编码器351和/或内部回路符号翻译器347存储。该存储模块301包括如DRAM。The inner loopcentral processing unit 345 may be adapted to program the innerloop symbol translator 347 by providing decoding instructions to the innerloop symbol translator 347, eg, via thebus 357 . Thebus 357 can be implemented in the multi-standard video decoder as a bus to transmit information to theprocessing module 343 to increase processing efficiency and simplify the execution process. The time information generated by the unprocessed elementary video stream decoding process can be stored by theinner loop CPU 345 in thestorage module 341, theouter loop CPU 349, the outer loop symbol translator 353, theport encoder 351 and/or the innerloop Symbol translator 347 stores. Thestorage module 301 includes, for example, DRAM.

操作过程中，输入的基本视频流355包括根据多个编码标准如H.261、H.263、H.263+(Annex J)、H.264、VC-1、MPEG-1、MPEG-2和/或MPEG-4之一编码的视频数据。端口编码器351可适于检测一个或多个符合该基本视频流355编码模式的起始码和起始码后缀。该端口编码器351还适于生成包括报头和/或宏块信息的未处理的基本视频流。该端口编码器351生成的未处理的基本视频流内的报头信息可传送至外部回路中央处理器349和外部回路符号翻译器353以进一步处理。未处理的基本视频流内的起始码和宏块信息可通过存储器341传送至内部回路中央处理器345和内部回路符号翻译器347，以进行进一步处理。在本发明示范性的一个方面中，该外部回路中央处理器349和外部回路符号翻译器353可适于处理随后的或未来的报头信息，而内部回路中央处理器345和内部回路符号翻译器347可处理当前宏块信息。During operation, the inputelementary video stream 355 includes encoding standards such as H.261, H.263, H.263+ (Annex J), H.264, VC-1, MPEG-1, MPEG-2 and / or video data encoded by one of MPEG-4. Theport encoder 351 may be adapted to detect one or more start codes and start code suffixes conforming to the encoding mode of theelementary video stream 355 . Theport encoder 351 is also adapted to generate a raw elementary video stream including header and/or macroblock information. The header information within the unprocessed elementary video stream generated by theport encoder 351 may be transmitted to theouter loop CPU 349 and the outer loop symbol translator 353 for further processing. The start code and macroblock information in the unprocessed elementary video stream can be sent to theinner loop CPU 345 and the innerloop symbol translator 347 through thememory 341 for further processing. In an exemplary aspect of the invention, theouter loop CPU 349 and outer loop symbol translator 353 may be adapted to process subsequent or future header information, while theinner loop CPU 345 and innerloop symbol translator 347 Can process current macroblock information.

该内部回路符号翻译器347可适于处理端口编码器329传送未处理的基本视频流中的宏块信息。然后，该内部回路符号翻译器347可生成输出信号，该输出信号包括如获得的宏块类型信息、片段类型信息、预测模式信息、运动矢量信息和/或量化频率系数。该输出信号可通过总线3 57传送至处理模块343，在宏块解码期间使用。Theintra-loop symbol translator 347 may be adapted to process macroblock information in the raw elementary video stream delivered by theport encoder 329 . Theintra-loop sign translator 347 may then generate an output signal comprising macroblock type information, slice type information, prediction mode information, motion vector information and/or quantized frequency coefficients as obtained. This output signal can be sent to theprocessing module 343 via thebus 357 for use during macroblock decoding.

处理模块343可使用内部回路符号翻译器347生成的处理信息生成解码视频流361。该处理模块343包括适合的电路、逻辑和/或代码，适于执行一个或多个以下处理任务：空间预测、运动补偿、逆量化和变换、宏块重建、回路内宏块滤波和/或宏块后处理。处理模块343内的每一处理任务可使用一个或多个辅助块，该辅助块符合被用于编码基本视频流331的特定编码方法。在这一点上，处理模块323可适于解码使用多个编码方法如H.261、H.263、H.263+(Annex J)、H.264、VC-1、MPEG-1、MPEG-2和/或MPEG-4之一编码的基本视频流。Processing module 343 may generate decodedvideo stream 361 using the processing information generated by in-loop symbol translator 347 . Theprocessing module 343 includes suitable circuitry, logic, and/or code adapted to perform one or more of the following processing tasks: spatial prediction, motion compensation, inverse quantization and transformation, macroblock reconstruction, in-loop macroblock filtering, and/or macroblock Block postprocessing. Each processing task within theprocessing module 343 may use one or more auxiliary blocks that conform to the particular encoding method used to encode theelementary video stream 331 . In this regard, theprocessing module 323 may be adapted to decode codes using multiple encoding methods such as H.261, H.263, H.263+ (Annex J), H.264, VC-1, MPEG-1, MPEG-2 and/or one of the MPEG-4 encoded elementary video streams.

图4A是根据本发明的实施例的示例性的具有硬件辅助块和单一CPU的多标准视频解码器的结构图。如图4A所示，该多标准视频解码器400包括端口编码器(CIP)403、符号翻译器405、中央处理器(CPU)407、空间预测模块409、逆量化和变换(IQT)模块411、运动补偿模块413、重建器415、内部回路滤波器417、帧缓冲器419和后处理模块421。FIG. 4A is a block diagram of an exemplary multi-standard video decoder with hardware assistance blocks and a single CPU, according to an embodiment of the present invention. As shown in Figure 4A, themulti-standard video decoder 400 includes a port encoder (CIP) 403, asymbol translator 405, a central processing unit (CPU) 407, aspatial prediction module 409, an inverse quantization and transform (IQT)module 411,Motion compensation module 413 , reconstructor 415 , in-loop filter 417 ,frame buffer 419 andpost-processing module 421 .

该端口编码器403包括适合的电路、逻辑和/或代码，可适于接收视频基本码流401并生成起始码、起始码后缀和未处理的基本流。端口编码器403包括起始码寻找模块423和字节解除模块425。该起始码寻找模块423可适于确定起始码和起始码后缀，如图1所示。字节解除模块425可适于从视频基本码流401解除额外字节，并生成未处理的基本流数据，如图2所示。起始码、起始码后缀和未处理的基本流在端口编码器403内生成后，该起始码后缀426可被传送至中央处理器407，未处理的基本流可被传送至符号翻译器405，以进一步处理。Theport encoder 403 includes suitable circuitry, logic and/or code that may be adapted to receive the videoelementary stream 401 and generate a start code, a start code suffix, and a raw elementary stream. Theport encoder 403 includes a start code finding module 423 and abyte unblocking module 425 . The start code finding module 423 can be adapted to determine the start code and the start code suffix, as shown in FIG. 1 . Thebyte stripping module 425 may be adapted to strip extra bytes from the videoelementary stream 401 and generate unprocessed elementary stream data, as shown in FIG. 2 . After the start code, the start code suffix and the unprocessed elementary stream are generated in theport encoder 403, thestart code suffix 426 can be sent to theCPU 407, and the unprocessed elementary stream can be sent to thesymbol translator 405 for further processing.

在在本发明的一个示范性实施例中，该多标准视频解码器400可使用中央处理器407和符号翻译器405处理来自端口编码器403生成的未处理的基本比特流的报头信息和/或宏块信息。来自未处理的基本比特流的报头信息可包括片段信息、画面信息、GOP/切入点信息和/或序列信息。端口编码器403生成的未处理的基本视频流内片段信息包包括相应于特定片段的片段报头信息和宏块信息。In an exemplary embodiment of the present invention, themulti-standard video decoder 400 may use theCPU 407 and thesymbol translator 405 to process the header information and/or Macroblock information. Header information from an unprocessed elementary bitstream may include segment information, picture information, GOP/pointcut information, and/or sequence information. The slice information packet in the raw elementary video stream generated by theport encoder 403 includes slice header information and macroblock information corresponding to a specific slice.

符号翻译器405包括适合的电路、逻辑和/或代码，可适于翻译从端口编码器403获得的未处理的基本流424，获得未处理的基本视频流424解码所需的量化的频率系数信息和/或附加旁信息。该符号翻译器405也可将随后的宏块和/或未处理的基本视频流内的帧上的视频信息通过连接406传送至中央处理器407。该中央处理器407从端口编码器403获得起始码后缀426后，可根据与获得的起始码后缀426相关的编码方法，生成符号翻译器的一个或多个解码指令。该中央处理器407可适于通过连接408将这些解码指令提供给符号翻译器405来将该符号翻译器405程序化。该中央处理器407也可根据在后续宏块或帧上的接收视频信息，通过连接406传送解码指令给符号翻译器45。Thesymbol translator 405 includes suitable circuitry, logic and/or code adapted to translate the rawelementary stream 424 obtained from theport encoder 403 to obtain the quantized frequency coefficient information required for decoding the rawelementary video stream 424 and/or additional side information. Thesymbol translator 405 may also transfer video information on subsequent macroblocks and/or frames within the unprocessed elementary video stream to thecentral processing unit 407 viaconnection 406 . After thecentral processing unit 407 obtains thestart code suffix 426 from theport encoder 403, it can generate one or more decoding instructions of the symbol translator according to the encoding method related to the obtainedstart code suffix 426. Thecentral processing unit 407 may be adapted to program thesymbol translator 405 by providing the decoding instructions to thesymbol translator 405 via theconnection 408 . TheCPU 407 can also send decoding instructions to the symbol translator 45 via theconnection 406 according to the received video information on subsequent macroblocks or frames.

根据本发明的一个方面，输入的基本视频流401包括根据多个编码标准如H.261、H.263、H.263+(Annex J)、H.264、VC-1、MPEG-1、MPEG-2和/或MPEG-4之一编码的视频数据。符号翻译器405，使用来自中央处理器407的指令，可适于解码一个或多个符号和/或附加处理信息，如报头和/或宏块信息，用于完成从端口编码器403接收的未处理的基本流424的解码。该符号翻译器可包括特定于每一被使用的编码模式的多个解码辅助模块，以解码未处理的基本流424。According to one aspect of the present invention, the inputelementary video stream 401 includes encoding standards such as H.261, H.263, H.263+(Annex J), H.264, VC-1, MPEG-1, MPEG -2 and/or MPEG-4 encoded video data. Thesymbol translator 405, using instructions from thecentral processing unit 407, may be adapted to decode one or more symbols and/or additional processing information, such as header and/or macroblock information, for completing the pending Decoding ofelementary stream 424 is processed. The symbol translator may include a number of decoding helper modules specific to each encoding mode used to decode the rawelementary stream 424 .

在本发明的一个示例性的实施例中，该符号翻译器405包括固定长度编码(fixed length coding，简称FLC)模块427、可变长度编码(variblelength coding，简称VLC)模块429和/或上下文自适应二进制算法编码(context adaptive binary arithmetic coding，简称CABAC)模块433、系数构造模块435和矢量构造模块437。符号翻译器405内的解码辅助模块可用于根据从端口编码器403生成的起始码后缀426获得并传送至中央处理器407的解码方法信息解码过程中。FLC模块427、VLC模块429和CABAC模块433可被符号翻译器405用于解码/翻译单一语法元，该单一语法元来自分别使用固定长度编码、可变长度编码或CABAC编码技术编码的未处理的基本流424。In an exemplary embodiment of the present invention, thesymbol translator 405 includes a fixed length coding (fixed length coding, FLC for short)module 427, a variable length coding (variable length coding, VLC for short)module 429 and/or a context self- A context adaptive binary arithmetic coding (CABAC for short)module 433 , acoefficient construction module 435 and a vector construction module 437 . The decoding auxiliary module in thesymbol translator 405 can be used in the decoding process according to the decoding method information obtained from thestart code suffix 426 generated by theport encoder 403 and transmitted to thecentral processing unit 407 . TheFLC module 427, theVLC module 429 and theCABAC module 433 can be used by thesymbol translator 405 to decode/translate a single syntax element from the raw code encoded using fixed-length coding, variable-length coding or CABAC coding techniques, respectively.Elementary Stream 424.

系数构造模块435可适于从未处理的基本流424生成一个或多个量化频率系数。该系数构造模块435生成的量化的频率系数随后用于多标准视频解码器400内，以生成一个或多个宏块重建过程中使用的预测错误信息。该生成的量化频率系数可被符号翻译器405传送至IQT模块411，以进一步处理。Thecoefficient construction module 435 may be adapted to generate one or more quantized frequency coefficients from the unprocessedelementary stream 424 . The quantized frequency coefficients generated by thecoefficient construction module 435 are then used within themulti-standard video decoder 400 to generate prediction error information used in the reconstruction process of one or more macroblocks. The generated quantized frequency coefficients may be sent by thesymbol translator 405 to theIQT module 411 for further processing.

相似地，矢量构造模块437可适于从未处理的基本流424生成一个或多个运动矢量。该矢量构造模块437生成的运动矢量可用于多标准视频解码器400内，以生成一个或多个宏块重建过程中使用的预测像素。该生成的运动矢量信息可被符号翻译器传送至运动补偿模块413，以进一步处理。Similarly, the vector construction module 437 may be adapted to generate one or more motion vectors from the unprocessedelementary stream 424 . The motion vectors generated by the vector construction module 437 may be used within themulti-standard video decoder 400 to generate predictive pixels for use in the reconstruction of one or more macroblocks. The generated motion vector information can be sent by the symbol translator to themotion compensation module 413 for further processing.

空间预测模块409包括适合的电路、逻辑和/或代码，可适于生成被重建器415用来生成解码宏块的预测像素。该空间预测模块409可适于如从符号翻译器获得宏块类型信息、片段类型信息和/或预测模式信息。而后，该空间预测模块409可使用所获的的宏块类型信息、片段类型信息和/或预测模式信息为空间上被预测的宏块生成预测像素。Spatial prediction module 409 includes suitable circuitry, logic, and/or code that may be adapted to generate predicted pixels that are used by reconstructor 415 to generate decoded macroblocks. Thespatial prediction module 409 may be adapted to obtain macroblock type information, slice type information and/or prediction mode information, eg from a symbol translator. Then, thespatial prediction module 409 can use the obtained macroblock type information, slice type information and/or prediction mode information to generate prediction pixels for the spatially predicted macroblocks.

运动补偿模块413包括适合的电路、逻辑和/或代码，可适于使用从符号翻译器405接收的运动矢量信息，生成预测像素。例如，该运动补偿模块413可为时间上被预测的宏块生成预测像素，可与当前帧/域相邻的帧/域中的运动补偿矢量相关联。该运动补偿模块413可从帧缓冲器419获得在先和/或随后的帧/域，并使用获得的先和/或随后的帧/域预测当前宏块内的时间上的编码像素。Motion compensation module 413 includes suitable circuitry, logic, and/or code that may be adapted to generate predicted pixels using motion vector information received fromsign translator 405 . For example, themotion compensation module 413 may generate prediction pixels for temporally predicted macroblocks, which may be associated with motion compensation vectors in frames/fields adjacent to the current frame/field. Themotion compensation module 413 may obtain previous and/or subsequent frames/fields from theframe buffer 419 and use the obtained previous and/or subsequent frames/fields to predict temporally encoded pixels within the current macroblock.

该运动补偿模块413包括多个运动补偿辅助模块，可用于根据用于编码未处理的基本流数据424的方法生成预测像素。例如，该运动补偿模块413包括范围重设模块447、强度补偿模块449、插入模块451、可变块尺寸模块453和双向预测模块455。该插入模块451可适于使用从符号翻译器45接收的运动矢量信息插入当前帧内一个或多个预测像素以及插入一个或多个时间上与当前帧相邻的参考帧。Themotion compensation module 413 includes a plurality of motion compensation auxiliary modules that can be used to generate prediction pixels according to the method used to encode the rawelementary stream data 424 . For example, themotion compensation module 413 includes a range resetting module 447 , an intensity compensation module 449 , an interpolation module 451 , a variable block size module 453 and abidirectional prediction module 455 . The insertion module 451 may be adapted to use the motion vector information received from the sign translator 45 to insert one or more predicted pixels within the current frame and to insert one or more reference frames temporally adjacent to the current frame.

如果仅使用一个参考帧插入预测像素，该插入模块451可用于生成预测象素。然而，如果多于一个预测参考帧被用于当前像素的时间预测过程中，运动补偿模块413可使用双向预测模块455生成预测像素。例如，如果几个参考帧被用于当前像素的预测，双向预测模块455可确定当前预测像素作为参考帧中的预测像素的平均值。If only one reference frame is used to interpolate predicted pixels, the interpolation module 451 can be used to generate predicted pixels. However, if more than one prediction reference frame is used in the temporal prediction process of the current pixel, themotion compensation module 413 may use thebidirectional prediction module 455 to generate the predicted pixel. For example, if several reference frames are used for prediction of the current pixel, thebidirectional prediction module 455 may determine the current prediction pixel as the average of the prediction pixels in the reference frames.

范围重设模块447可被运动补偿模块413用于VC-1标准编码的未处理的基本流的编码过程中。更特殊的是，该范围重设模块447可用于在插入模块451插入之前，重设参考帧的动态范围。强度补偿模块449可被运动补偿模块413用于在插入模块451插入之前，将参考帧的强度水平调整至当前帧的强度水平。The rerange module 447 can be used by themotion compensation module 413 in the encoding process of the unprocessed elementary stream encoded by the VC-1 standard. More specifically, the range reset module 447 can be used to reset the dynamic range of the reference frame before the insertion module 451 inserts. The intensity compensation module 449 can be used by themotion compensation module 413 to adjust the intensity level of the reference frame to the intensity level of the current frame before insertion by the insertion module 451 .

可变块尺寸模块453可被运动补偿模块413用于控制从帧缓冲器419获得的参考帧的应用。例如，该可变块尺寸模块453可从帧缓冲器419取一个16×16、16×8和/或4×4像素尺寸宏块以用于当前宏块内像素的时间预测期间。当运动补偿模块413内运动补偿预测期间需要时，其他宏块和/或帧尺寸也可被帧缓冲器419支持。The variable block size module 453 may be used by themotion compensation module 413 to control the application of reference frames obtained from theframe buffer 419 . For example, the variable block size module 453 may fetch a 16x16, 16x8 and/or 4x4 pixel sized macroblock from theframe buffer 419 for use during temporal prediction of pixels within the current macroblock. Other macroblock and/or frame sizes may also be supported by theframe buffer 419 as required during motion compensated prediction within themotion compensation module 413 .

IQT模块411包括适合的电路、逻辑和/或代码，可适于将从符号翻译器接收的量化频率系数转换为一个或多个预测错误。更特殊地是，该IQT模块411可适于使用逆量化模块443和逆变换模块445将量化频率系数变换回空间域，由此生成预测错误信息。而后，该IQT模块411生成的预测错误信息被传送至重建器415，以在宏块重建期间进一步处理。TheIQT module 411 includes suitable circuitry, logic and/or code that may be adapted to convert the quantized frequency coefficients received from the symbol translator into one or more prediction errors. More specifically, theIQT module 411 may be adapted to transform the quantized frequency coefficients back to the spatial domain using an inverse quantization module 443 and an inverse transform module 445, thereby generating prediction error information. The prediction error information generated by theIQT module 411 is then sent to the reconstructor 415 for further processing during macroblock reconstruction.

逆锯齿模块439可被IQT模块411用于在被逆变换模块445逆变换之前，重新排列从符号翻译器405接收的量化频率系数。符号翻译器405生成的量化频率系数可被安排锯齿(Z形)扫描顺序，以便于编码。因此逆锯齿模块439可使用一个或多个查找表将量化频率系数以如连续的顺序进行安排。The inverse aliasing module 439 may be used by theIQT module 411 to rearrange the quantized frequency coefficients received from thesign translator 405 before being inverse transformed by the inverse transform module 445 . The quantized frequency coefficients generated by thesign translator 405 may be arranged in a zigzag (Zigzag) scan order for ease of encoding. The anti-aliasing module 439 may therefore use one or more look-up tables to arrange the quantized frequency coefficients in eg consecutive order.

根据未处理的基本流424地编码方法，IQT模块41在预测错误信息解码期间可使用AC/DC预测模块441。例如，量化频率系数可使用来自相邻像素的预测剩余和预测错误，在未处理的基本流424内被编码。更进一步，AC/DC预测模块441内的DC预测可相应于生成预测错误信息所使用的零频率系数。AC/DC预测模块441内的AC预测可相应于生成预测错误信息所使用的低频率系数。符号翻译器、运动补偿模块、空间预测模块和逆量化和变换模块操作上的其他信息更充分地揭露于序列号为10/963,677(机构代码案件编号为15748US02)、申请日为2004年10月13日的美国专利申请中，该申请在此作为全面参考。Depending on the encoding method of the rawelementary stream 424, the IQT module 41 may use the AC/DC prediction module 441 during decoding of prediction error information. For example, quantized frequency coefficients may be encoded within the rawelementary stream 424 using prediction residuals and prediction errors from neighboring pixels. Furthermore, the DC prediction within the AC/DC prediction module 441 may correspond to zero frequency coefficients used to generate the prediction error information. The AC prediction within the AC/DC prediction module 441 may correspond to the low frequency coefficients used to generate the prediction error information. Additional Information on the Operation of the Symbol Translator, Motion Compensation Module, Spatial Prediction Module, and Inverse Quantization and Transformation Module is more fully disclosed in Serial No. 10/963,677 (Agency Code Case No. 15748US02), filed October 13, 2004 in the U.S. Patent Application dated 1999, which is hereby incorporated by reference in its entirety.

重建器415可适于分别从空间预测模块409或运动补偿模块获得空间预测像素或时间预测像素。此外，该重建器415可适于获得IQT模块411生成的预测错误信息。而后，该重建器可使用预测像素和预测错误信息重建当前宏块。该重建宏块可传送至内部回路滤波器417以作进一步处理。The reconstructor 415 may be adapted to obtain spatially predicted pixels or temporally predicted pixels from thespatial prediction module 409 or the motion compensation module, respectively. Furthermore, the reconstructor 415 may be adapted to obtain prediction error information generated by theIQT module 411 . The reconstructor can then use the predicted pixels and prediction error information to reconstruct the current macroblock. The reconstructed macroblock may be sent to theinner loop filter 417 for further processing.

该内部回路滤波器417包括适合的电路、逻辑和/或代码，可适于进一步滤波从重建器415获得的解码/重建宏块。根据未处理的基本流424地编码方法，该内部回路滤波器417可包括重叠变换模块457和解块模块459。该重叠变换模块457可用于从以VC-1标准编码的未处理的基本流424生成的宏块的滤波的过程中。更特殊地是，重叠变换模块457可将重叠变换应用于重建的宏块以减小沿该重建的宏块一个或多个边缘的边缘人为因素。同样地，解块模块459也可被内部回路滤波器417用于减小沿该重建的宏块一个或多个边缘地边缘人为因素并变换块效应。解码器中解块和解块存储应用上有关的其他信息更充分地揭露于序列号为10/965,172(机构代码案件编号为15756US02)、申请日为2004年10月13日和序列号为10/972,931(机构代码案件编号为15757US02)、申请日为2004年10月25日的美国专利申请中，该两申请在此作为全面参考。The in-loop filter 417 includes suitable circuitry, logic and/or code that may be adapted to further filter the decoded/reconstructed macroblocks obtained from the reconstructor 415 . Depending on the encoding method of the rawelementary stream 424 , theinner loop filter 417 may include alapped transform module 457 and adeblocking module 459 . The lappedtransform module 457 may be used in the process of filtering macroblocks generated from the rawelementary stream 424 coded in the VC-1 standard. More particularly, lappedtransform module 457 may apply lapped transforms to the reconstructed macroblock to reduce edge artifacts along one or more edges of the reconstructed macroblock. Likewise,deblocking module 459 may also be used byinner loop filter 417 to reduce edge artifacts and transform blockiness along one or more edges of the reconstructed macroblock. Additional Information Relating to Application of Deblocking and Deblocking Storage in Decoders is more fully disclosed in Serial No. 10/965,172 (Agency Code Case No. 15756US02), filed October 13, 2004 and Serial No. 10/972,931 (Institution Code Case No. 15757US02), filed on October 25, 2004, both of which are hereby incorporated by reference in their entirety.

重建宏块被内部回路滤波器417滤波后，附加后处理可由后处理模块421执行。根据新基本流424的编码方法，后处理模块可使用一个或多个以下后处理辅助模块：范围重设模块461、尺寸调整模块463、解块模块465和/或解环模块467。如果以VC-1标准编码的过程中，一个宏块或一组宏块的动态范围被改变，则该范围重设模块46可被后处理模块421使用。以这种方式，所有传送至显示后处理器的解码宏块469被同一个动态范围描述。After the reconstructed macroblocks are filtered by the in-loop filter 417 , additional post-processing may be performed by thepost-processing module 421 . Depending on the encoding method of the newelementary stream 424 , the post-processing module may use one or more of the following post-processing auxiliary modules: rerange module 461 , resizemodule 463 , deblock module 465 and/or dering module 467 . The rerange module 46 may be used by thepost-processing module 421 if the dynamic range of a macroblock or a group of macroblocks is changed during encoding in the VC-1 standard. In this way, all decodedmacroblocks 469 passed to the display post-processor are described by the same dynamic range.

尺寸调整模块463可被后处理模块421用来缩放/调整尺寸一个编码期间被尺寸升级或降级的宏块。通过使用尺寸调整模块463，后处理模块421可生成具有相同清晰度的解码的宏块469。解环模块467可用于消弱过度量化的AC系数生成的重构宏块内的“飞蚊噪声”。解块模块465类似于内部回路滤波器417内的解块模块459，可用于进一步减小边缘人为因素，并优先于将宏块传送至如显示后处理器，变换沿该重建的宏块一个或多个边缘的块效应。Theresizing module 463 may be used by thepost-processing module 421 to scale/resize a macroblock that is upscaled or downgraded during encoding. By using theresizing module 463, thepost-processing module 421 may generate a decodedmacroblock 469 with the same resolution. The deringing module 467 may be used to attenuate "mosquito noise" within reconstructed macroblocks generated by over-quantized AC coefficients. Deblocking module 465, similar todeblocking module 459 withininner loop filter 417, can be used to further reduce edge artifacts and transform the reconstructed macroblock along one or Blocking effect with multiple edges.

图4B是根据本发明的实施例的示例性的具有硬件辅助块和CPU对的多标准视频解码器的结构示意图。如图4B所示，该多标准视频解码器470包括端口编码器(CIP)471、外部回路中央处理器(OLCPU)473、外部回路符号翻译器(OLSI)475、内部回路中央处理器(ILCPU)477和内部回路符号翻译器(ILSI)479。该多标准视频解码器470还可包括空间预测模块、逆量化和变换模块、运动补偿模块、重建模块、内部回路滤波模块、帧缓冲器模块和后处理模块(图4B中未示)，如图4A中多标准视频编码器的细节说明和描述。FIG. 4B is a block diagram of an exemplary multi-standard video decoder with a hardware-assisted block and a CPU pair according to an embodiment of the present invention. As shown in Figure 4B, thismulti-standard video decoder 470 includes a port encoder (CIP) 471, an outer loop central processing unit (OLCPU) 473, an outer loop symbol translator (OLSI) 475, an inner loop central processing unit (ILCPU) 477 and the Interloop Symbol Interpreter (ILSI) 479. Themulti-standard video decoder 470 may also include a spatial prediction module, an inverse quantization and transformation module, a motion compensation module, a reconstruction module, an in-loop filtering module, a frame buffer module and a post-processing module (not shown in FIG. 4B ), as shown in FIG. Detailed illustration and description of multistandard video encoders in 4A.

在本发明的一个示范性实施例中，多标准解码器470可使用外部回路中央处理器473和外部回路符号翻译器475处理来自视频基本比特流480的报头信息。内部回路中央处理器477和内部回路符号翻译器479可用于处理来自视频基本比特流480的宏块信息。以这种方式，可在多标准视频解码器470中实现平行处理，当外部回路中央处理器473和外部回路符号翻译器475可处理未来报头信息时，内部回路中央处理器477和内部回路符号翻译器479可处理当前宏块信息。来自基本比特流480的报头信息可包括如片段信息、画面信息、GOP/切入点信息和/或序列信息。In an exemplary embodiment of the present invention,multi-standard decoder 470 may process header information from videoelementary bitstream 480 usingouter loop CPU 473 and outer loop symbol translator 475 .Intra-loop CPU 477 andintra-loop symbol translator 479 may be used to process macroblock information from videoelementary bitstream 480 . In this way, parallel processing can be achieved in themulti-standard video decoder 470, while theouter loop CPU 473 and the outer loop symbol translator 475 can process future header information, theinner loop CPU 477 and the inner loop symbol translator Theprocessor 479 can process current macroblock information. Header information fromelementary bitstream 480 may include, for example, segment information, picture information, GOP/point cut information, and/or sequence information.

在操作过程中，端口编码器471可接收视频基本码流480并生成起始码和起始码后缀481以及未处理的基本流482。该起始码和起始码后缀481被传送至外部回路中央处理器473处理，未处理的基本流482被传送至外部回路符号翻译器475处理。外部回路中央处理器473和外部回路符号翻译器475可适于仅处理来自起始码和起始码后缀481以及未处理的基本流482的报头信息。外部回路中央处理器473通过如系统传送端口483与离线视频处理系统相连接。During operation,port encoder 471 may receive videoelementary stream 480 and generate start code and startcode suffix 481 and rawelementary stream 482 . The start code and startcode suffix 481 are sent to theouter loop CPU 473 for processing, and the unprocessedelementary stream 482 is sent to the outer loop symbol translator 475 for processing. Theouter loop CPU 473 and the outer loop symbol translator 475 may be adapted to only process header information from the start code and startcode suffix 481 and the unprocessedelementary stream 482 . Theexternal loop CPU 473 is connected with the off-line video processing system through, for example, thesystem transmission port 483 .

外部回路符号翻译器475包括可变长度编码(varible length coding，简称VLC)模块484和固定长度编码(fixed length coding，简称FLC)模块472。该VLC模块484和FLC模块472可用于解码来自端口解码器471接收的未处理的基本流482的报头信息。例如，报头信息485可从未处理的基本流482取出，由此生成输出比特流486。该输出比特流486包括宏块相关信息，并可传送至内部回路符号翻译器479进一步处理。外部回路中央处理器473处理来自起始码和起始码后缀481的报头信息后，结果处理控制信息476可被传送至内部回路中央处理器477进一步处理。该过程控制信息476包括控制信息，该控制信息相应于包含宏块信息的信息包，如输出比特流486中的信息包。The external loop symbol translator 475 includes a variable length coding (variable length coding, VLC for short)module 484 and a fixed length coding (fixed length coding, FLC for short)module 472 . TheVLC module 484 andFLC module 472 may be used to decode header information from the rawelementary stream 482 received by theport decoder 471 . For example, header information 485 may be taken from unprocessedelementary stream 482, thereby generatingoutput bitstream 486. Theoutput bitstream 486 includes macroblock related information and may be sent to the innerloop symbol translator 479 for further processing. After theouter loop CPU 473 processes the header information from the start code and startcode suffix 481 , the resultingprocessing control information 476 can be sent to theinner loop CPU 477 for further processing. Theprocess control information 476 includes control information corresponding to packets containing macroblock information, such as packets in theoutput bitstream 486 .

当外部回路中央处理器473和外部回路符号翻译器475可处理后续报头信息时，内部回路中央处理器477和内部回路符号翻译器479可适于同时为当前宏块处理与宏块相关的信息。内部回路符号翻译器479，与图4A的符号翻译器405相似，可适于生成输出信号487。该输出信号包括如获得的宏块类型信息、片段类型信息、预测模式信息、运动矢量信息和/或量化频率系数。该获得的宏块类型信息、片段类型信息和/或预测模式信息可传送至空间预测模块(图未示)，如图4A所示空间预测模块409，以进一步处理及为空间上预测的宏块生成预测像素。While theouter loop CPU 473 and the outer loop symbol translator 475 can process subsequent header information, theinner loop CPU 477 and the innerloop symbol translator 479 can be adapted to simultaneously process macroblock related information for the current macroblock. Innerloop sign translator 479 , similar to signtranslator 405 of FIG. 4A , may be adapted to generateoutput signal 487 . The output signal comprises, as obtained, macroblock type information, slice type information, prediction mode information, motion vector information and/or quantized frequency coefficients. The obtained macroblock type information, slice type information and/or prediction mode information can be sent to a spatial prediction module (not shown in the figure), such as thespatial prediction module 409 shown in FIG. Generate predicted pixels.

运动矢量信息490可传送至运动补偿模块(图未示)，如图4A所示的运动补偿模块413，以进一步处理及为时间上预测的宏块生成预测像素。量化频率系数489可传送至逆量化和变换模块(图未示)，如图4A所示的逆量化和变换模块411，以进一步处理及生成宏块解码期间使用的预测错误。Themotion vector information 490 can be sent to a motion compensation module (not shown), such as themotion compensation module 413 shown in FIG. 4A , for further processing and generating prediction pixels for temporally predicted macroblocks. Thequantized frequency coefficients 489 may be sent to an inverse quantization and transformation module (not shown), such as the inverse quantization andtransformation module 411 shown in FIG. 4A, for further processing and generation of prediction errors used during macroblock decoding.

图5是根据本发明的实施例的示例性的当解码H.264视频数据时，图4所示多标准视频解码器500的运行的结构图。如图5所示，该多标准视频解码器500可适于处理使用H.264编码技术编码的视频基本码流401。端口编码器403可使用起始码寻找模块423确定起始码和起始码后缀，使用字节解除模块425从H.264编码视频基本码流401移除额外字节。FIG. 5 is a block diagram illustrating an exemplary operation of themulti-standard video decoder 500 shown in FIG. 4 when decoding H.264 video data according to an embodiment of the present invention. As shown in FIG. 5 , themulti-standard video decoder 500 may be adapted to process a videoelementary stream 401 encoded using H.264 encoding technology. Theport encoder 403 may use a start code lookup module 423 to determine a start code and a start code suffix, and abyte stripping module 425 to remove extra bytes from the H.264 encoded videoelementary stream 401 .

符号翻译器405可适于翻译从端口编码器403获得的H.264未处理的基本流424，以获得量化频率系数信息和/或附加旁信息，如H.264未处理的基本视频流424解码需要的宏块类型信息、片段类型信息、预测模式信息和/或运动矢量信息。量化频率系数信息和/或附加旁信息生成过程中，符号翻译器405可接收中央处理器407的指令，并向中央处理器407提供后续符号信息。此外，符号翻译器可使用下列辅助模块的一个或多个：FLC模块427、VLC模块429、CABAC模块433、系数构造模块435和/或矢量构造模块437。Thesymbol translator 405 may be adapted to translate the H.264 rawelementary stream 424 obtained from theport encoder 403 to obtain quantized frequency coefficient information and/or additional side information, such as the H.264 rawelementary video stream 424 decoded Required macroblock type information, slice type information, prediction mode information and/or motion vector information. During the generation of quantized frequency coefficient information and/or additional side information, thesymbol translator 405 may receive instructions from theCPU 407 and provide subsequent symbol information to theCPU 407 . Additionally, the symbol translator may use one or more of the following auxiliary modules:FLC module 427 ,VLC module 429 ,CABAC module 433 ,coefficient construction module 435 and/or vector construction module 437 .

逆量化频率系数可从符号翻译器405传送至IQT模块411，可生成预测错误信息。IQT模块411可使用逆锯齿模块439、逆量化模块443和/或逆变换模块445生成预测错误信息。来自符号翻译器405的旁信息可被传送至空间预测模块409或运动补偿模块413，生成预测像素。运动补偿模块413可使用帧缓冲器419以及强度补偿模块449、插入模块451、可变块尺寸模块453和/或双向预测模块455生成时间上的预测像素。The inverse quantized frequency coefficients may be passed from thesign translator 405 to theIQT module 411, which may generate prediction error information. TheIQT module 411 may use the inverse aliasing module 439 , the inverse quantization module 443 and/or the inverse transform module 445 to generate prediction error information. The side information from thesign translator 405 may be passed to thespatial prediction module 409 or themotion compensation module 413 to generate predicted pixels.Motion compensation module 413 may generate temporally predicted pixels usingframe buffer 419 as well as intensity compensation module 449 , interpolation module 451 , variable block size module 453 , and/orbidirectional prediction module 455 .

而后，重建器415可被多标准解码器500用于使用分别从空间预测模块409或运动补偿模块413获得的预测像素信息，以及从IQT模块411获得的预测错误信息，重建当前宏块。重建的宏块可被内部回路滤波器417使用解块模块459滤波。滤波后的宏块可进一步被后处理模块421处理。后处理模块421可使用解环模块467生成解码的宏块469。而后，该解码的宏块469可被传送至如显示后处理器。The reconstructor 415 can then be used by themulti-standard decoder 500 to reconstruct the current macroblock using the predicted pixel information obtained from thespatial prediction module 409 or themotion compensation module 413, respectively, and the prediction error information obtained from theIQT module 411. The reconstructed macroblocks may be filtered by in-loop filter 417 usingdeblocking module 459 . The filtered macroblocks may be further processed by apost-processing module 421 .Post-processing module 421 may use deringing module 467 to generate decodedmacroblock 469 . The decodedmacroblock 469 may then be passed, eg, to a display post-processor.

图6是根据本发明和实施例的示例性的当解码VC-1视频数据时，图4所示多标准视频解码器600的运行的结构图。如图6所示，该多标准视频解码器600可适于处理使用VC-1编码技术编码的视频基本码流401。端口编码器403可使用起始码寻找模块423确定起始码和起始码后缀，使用字节解除模块425从VC-1编码视频基本码流401移除额外字节。FIG. 6 is an exemplary block diagram of the operation of themulti-standard video decoder 600 shown in FIG. 4 when decoding VC-1 video data according to the present invention and embodiments. As shown in FIG. 6, themulti-standard video decoder 600 may be adapted to process a videoelementary stream 401 encoded using the VC-1 encoding technique. Theport encoder 403 may use a start code lookup module 423 to determine the start code and start code suffix, and abyte stripping module 425 to remove extra bytes from the VC-1 encoded videoelementary stream 401 .

符号翻译器405可适于翻译从端口编码器403获得的VC-1未处理的基本流424，以获得量化频率系数信息和/或附加旁信息，如VC-1未处理的基本视频流424解码需要的宏块类型信息、片段类型信息、预测模式信息和/或运动矢量信息。量化频率系数信息和/或附加旁信息生成过程中，符号翻译器405可接收中央处理器407的指令，并向中央处理器407提供后续符号信息。此外，符号翻译器可使用下列辅助模块的一个或多个：FLC模块427、VLC模块429、系数构造模块43 5和/或矢量构造模块437。Thesymbol translator 405 may be adapted to translate the VC-1 rawelementary stream 424 obtained from theport encoder 403 to obtain quantized frequency coefficient information and/or additional side information, such as the VC-1 rawelementary video stream 424 decoded Required macroblock type information, slice type information, prediction mode information and/or motion vector information. During the generation of quantized frequency coefficient information and/or additional side information, thesymbol translator 405 may receive instructions from theCPU 407 and provide subsequent symbol information to theCPU 407 . Additionally, the symbol translator may use one or more of the following auxiliary modules:FLC module 427,VLC module 429,coefficient construction module 435, and/or vector construction module 437.

逆量化频率系数可从符号翻译器405传送至IQT模块411，可生成预测错误信息。IQT模块411可使用逆锯齿模块439、AC/DC预测模块441、逆量化模块443和/或逆变换模块445生成预测错误信息。来自符号翻译器405的旁信息可被传送至运动补偿模块413，生成预测像素。运动补偿模块413可使用帧缓冲器419以及强度补偿模块449、范围重设模块447、插入模块451、可变块尺寸模块453和/或双向预测模块455生成时间上的预测像素。帧缓冲器419可适于存储和提供至少两个参考帧/画面给运动补偿模块413。The inverse quantized frequency coefficients may be passed from thesign translator 405 to theIQT module 411, which may generate prediction error information.IQT module 411 may use inverse aliasing module 439 , AC/DC prediction module 441 , inverse quantization module 443 and/or inverse transform module 445 to generate prediction error information. The side information from thesign translator 405 may be passed to themotion compensation module 413 to generate predicted pixels.Motion compensation module 413 may generate temporally predicted pixels usingframe buffer 419 along with intensity compensation module 449 , rerange module 447 , interpolation module 451 , variable block size module 453 , and/orbidirectional prediction module 455 . Theframe buffer 419 may be adapted to store and provide at least two reference frames/pictures to themotion compensation module 413 .

而后，重建器415可被多标准解码器600用于使用从运动补偿模块413获得的预测像素信息，以及从IQT模块411获得的预测错误信息，重建当前宏块。重建的宏块可被内部回路滤波器417使用解块模块459和/或重叠变换模块457滤波。滤波后的宏块可进一步被后处理模块421处理。后处理模块421可使用解环模块467、范围重设模块461、尺寸调整模块463和/或解块模块465生成解码的宏块469。而后，该解码的宏块469可被传送至如显示后处理器。The reconstructor 415 can then be used by themulti-standard decoder 600 to reconstruct the current macroblock using the predicted pixel information obtained from themotion compensation module 413 and the prediction error information obtained from theIQT module 411 . The reconstructed macroblocks may be filtered by in-loop filter 417 usingdeblocking module 459 and/or lappedtransform module 457 . The filtered macroblocks may be further processed by apost-processing module 421 .Post-processing module 421 may use deringing module 467 , resizing module 461 , resizingmodule 463 , and/or deblocking module 465 to generate decodedmacroblock 469 . The decodedmacroblock 469 may then be passed, eg, to a display post-processor.

图7是根据本发明的实施例的示例性的当解码MPEG-1或PMEG-2视频数据时，图4所示多标准视频解码器700的运行的结构图。如图7所示，该多标准视频解码器700可适于处理使用MPEG-1或MPEG-2编码技术编码的视频基本码流401。端口编码器403可使用起始码寻找模块423确定MPEG-1或MPEG-2编码视频基本码流401内的起始码和起始码后缀。FIG. 7 is a block diagram illustrating an exemplary operation of themulti-standard video decoder 700 shown in FIG. 4 when decoding MPEG-1 or PMEG-2 video data according to an embodiment of the present invention. As shown in FIG. 7, themulti-standard video decoder 700 may be adapted to process a videoelementary stream 401 encoded using MPEG-1 or MPEG-2 encoding techniques. Theport encoder 403 can use the start code finding module 423 to determine the start code and start code suffix within the MPEG-1 or MPEG-2 encoded videoelementary stream 401 .

符号翻译器405可适于翻译从端口编码器403获得的MPEG-1或MPEG-2未处理的基本流424，以获得量化频率系数信息和/或附加旁信息，如MPEG-1或MPEG-2未处理的基本视频流424解码需要的宏块类型信息、片段类型信息、预测模式信息和/或运动矢量信息。量化频率系数信息和/或附加旁信息生成过程中，符号翻译器405可接收中央处理器407的指令，并向中央处理器407提供后续符号信息。此外，符号翻译器可使用下列辅助模块的一个或多个：FLC模块427、VLC模块429、系数构造模块435和/或矢量构造模块437。Thesymbol translator 405 may be adapted to translate the MPEG-1 or MPEG-2 rawelementary stream 424 obtained from theport encoder 403 to obtain quantized frequency coefficient information and/or additional side information, such as MPEG-1 or MPEG-2 The rawelementary video stream 424 decodes macroblock type information, slice type information, prediction mode information, and/or motion vector information. During the generation of quantized frequency coefficient information and/or additional side information, thesymbol translator 405 may receive instructions from theCPU 407 and provide subsequent symbol information to theCPU 407 . Additionally, the symbol translator may use one or more of the following auxiliary modules:FLC module 427 ,VLC module 429 ,coefficient construction module 435 and/or vector construction module 437 .

逆量化频率系数可从符号翻译器405传送至IQT模块411，可生成预测错误信息。IQT模块411可使用逆锯齿模块439、逆量化模块443和/或逆变换模块445生成预测错误信息。来自符号翻译器405的旁信息可被传送至运动补偿模块413，生成预测像素。运动补偿模块413可使用帧缓冲器419以及插入模块451、可变块尺寸模块453和/或双向预测模块455生成时间上的预测像素。帧缓冲器419可适于存储和提供至少两个参考帧/画面给运动补偿模块413。The inverse quantized frequency coefficients may be passed from thesign translator 405 to theIQT module 411, which may generate prediction error information. TheIQT module 411 may use the inverse aliasing module 439 , the inverse quantization module 443 and/or the inverse transform module 445 to generate prediction error information. The side information from thesign translator 405 may be passed to themotion compensation module 413 to generate predicted pixels.Motion compensation module 413 may generate temporally predicted pixels usingframe buffer 419 and interpolation module 451 , variable block size module 453 , and/orbidirectional prediction module 455 . Theframe buffer 419 may be adapted to store and provide at least two reference frames/pictures to themotion compensation module 413 .

而后，重建器415可被多标准解码器700用于使用从运动补偿模块413获得的预测像素信息，以及从IQT模块411获得的预测错误信息，重建当前宏块。重建的宏块可进一步被后处理模块421处理。后处理模块421可使用解环模块467和/或解块模块465生成解码的宏块469。而后，该解码的宏块469可被传送至如显示后处理器。The reconstructor 415 can then be used by themulti-standard decoder 700 to reconstruct the current macroblock using the predicted pixel information obtained from themotion compensation module 413 and the prediction error information obtained from theIQT module 411 . The reconstructed macroblocks can be further processed by thepost-processing module 421 .Post-processing module 421 may use deringing module 467 and/or deblocking module 465 to generate decodedmacroblock 469 . The decodedmacroblock 469 may then be passed, eg, to a display post-processor.

图8是根据本发明的实施例的示例性的当解码MPEG-4视频数据时，图4所示多标准视频解码器800的运行的结构图。如图8所示，该多标准视频解码器800可适于处理使用MPEG-4编码技术编码的视频基本码流401。端口编码器403可使用起始码寻找模块423确定MPEG-4编码视频基本码流401内的起始码和起始码后缀。FIG. 8 is a block diagram illustrating an exemplary operation of the multi-standard video decoder 800 shown in FIG. 4 when decoding MPEG-4 video data according to an embodiment of the present invention. As shown in FIG. 8, the multi-standard video decoder 800 may be adapted to process a videoelementary stream 401 encoded using MPEG-4 encoding techniques. Theport encoder 403 can use the start code finding module 423 to determine the start code and the start code suffix within the MPEG-4 encoded videoelementary stream 401 .

符号翻译器405可适于翻译从端口编码器403获得的MPEG-4未处理的基本流424，以获得量化频率系数信息和/或附加旁信息，如MPEG-4未处理的基本视频流424解码需要的宏块类型信息、片段类型信息、预测模式信息和/或运动矢量信息。量化频率系数信息和/或附加旁信息生成过程中，符号翻译器405可接收中央处理器407的指令，并向中央处理器407提供后续符号信息。此外，符号翻译器可使用下列辅助模块的一个或多个：FLC模块427、VLC模块429、系数构造模块43 5和/或矢量构造模块437。Thesymbol translator 405 may be adapted to translate the MPEG-4 rawelementary stream 424 obtained from theport encoder 403 to obtain quantized frequency coefficient information and/or additional side information, such as the MPEG-4 rawelementary video stream 424 decoded Required macroblock type information, slice type information, prediction mode information and/or motion vector information. During the generation of quantized frequency coefficient information and/or additional side information, thesymbol translator 405 may receive instructions from theCPU 407 and provide subsequent symbol information to theCPU 407 . Additionally, the symbol translator may use one or more of the following auxiliary modules:FLC module 427,VLC module 429,coefficient construction module 435, and/or vector construction module 437.

逆量化频率系数可从符号翻译器405传送至IQT模块411，可生成预测错误信息。IQT模块411可使用逆锯齿模块439、AC/DC预测模块441、逆量化模块443和/或逆变换模块445生成预测错误信息。来自符号翻译器405的旁信息可被传送至运动补偿模块413，生成预测像素。运动补偿模块413可使用帧缓冲器419以及插入模块451、可变块尺寸模块453和/或双向预测模块455生成时间上的预测像素。帧缓冲器419可适于存储和提供至少两个参考帧/画面给运动补偿模块413。The inverse quantized frequency coefficients may be passed from thesign translator 405 to theIQT module 411, which may generate prediction error information.IQT module 411 may use inverse aliasing module 439 , AC/DC prediction module 441 , inverse quantization module 443 and/or inverse transform module 445 to generate prediction error information. The side information from thesign translator 405 may be passed to themotion compensation module 413 to generate predicted pixels.Motion compensation module 413 may generate temporally predicted pixels usingframe buffer 419 and interpolation module 451 , variable block size module 453 , and/orbidirectional prediction module 455 . Theframe buffer 419 may be adapted to store and provide at least two reference frames/pictures to themotion compensation module 413 .

而后，重建器415可被多标准解码器800用于使用从运动补偿模块413获得的预测像素信息，以及从IQT模块411获得的预测错误信息，重建当前宏块。重建的宏块可进一步被后处理模块421处理。后处理模块421可使用解环模块467和/或解块模块465生成解码的宏块469。而后，该解码的宏块469可被传送至如显示后处理器。The reconstructor 415 can then be used by the multi-standard decoder 800 to reconstruct the current macroblock using the predicted pixel information obtained from themotion compensation module 413 and the prediction error information obtained from theIQT module 411 . The reconstructed macroblocks can be further processed by thepost-processing module 421 .Post-processing module 421 may use deringing module 467 and/or deblocking module 465 to generate decodedmacroblock 469 . The decodedmacroblock 469 may then be passed, eg, to a display post-processor.

图9是根据本发明的实施例的处理视频数据流的示范性方法900的流程图。如图9所示，在步骤901，接收视频基本码流内的打包数据，其中视频基本码流可根据多个编码方法之一编码。在步骤903，确定该打包数据内的起始码，其中该起始码可定义封装视频有效载荷。在步骤905，确定打包数据中的标识符，该标识符定义一种或多种与该视频基本码流中的信息包关联的编码类型。在步骤907，基于所确定的标识符，从多个解码方法中选择一个解码方法。在步骤909，基于所选解码方法，所定义的封装视频有效载荷可被解码。FIG. 9 is a flowchart of an exemplary method 900 of processing a video data stream, according to an embodiment of the invention. As shown in FIG. 9, at step 901, packetized data in a video elementary stream is received, wherein the video elementary stream can be encoded according to one of a plurality of encoding methods. In step 903, a start code within the packetized data is determined, wherein the start code may define a packed video payload. In step 905, an identifier in the packetized data is determined, and the identifier defines one or more encoding types associated with the information packets in the video elementary stream. At step 907, based on the determined identifier, a decoding method is selected from a plurality of decoding methods. At step 909, based on the selected decoding method, the defined encapsulated video payload may be decoded.

因此，本发明可以在硬件、软件、固件或硬件和软件组合中实现。本发明可以在至少一个计算机系统中以集中方式实现或以分布方式实现，该分布方式是指不同元件分布于几个相互连接的计算机系统。任一种计算机或其他适于执行这里所描述的方法的设备都是适合的。一种典型的硬件、软件和固件的结合可以是具有计算机程序的多用途计算机系统，其中计算机程序可以被下载和执行，并控制计算机系统以使计算机系统执行这里所描述的方法。Therefore, the present invention can be implemented in hardware, software, firmware, or a combination of hardware and software. The invention can be implemented in a centralized fashion in at least one computer system or in a distributed fashion, meaning that the different elements are distributed over several interconnected computer systems. Any computer or other apparatus adapted for carrying out the methods described herein is suitable. A typical combination of hardware, software and firmware can be a multipurpose computer system with a computer program that can be downloaded and executed, and which controls the computer system such that the computer system performs the methods described herein.

本发明的一个实施例也可作为组件级产品、作为单一芯片、特殊用途集成电路(ASIC)实现，或者具有集成于单一芯片、与系统的其他部分不同级，作为分开元件实现。该系统的集成度由速度或成本考量初步确定。由于现代处理器种类繁杂，使用商业上可行的处理器是可能的，该处理器可以超出现有系统的ASIC实现方式的方法实现。作为选择，如果处理器作为ASIC核或逻辑块是有效的，那么商业上有效的处理器可作为具有各种功能、作为固件实现的ASIC设备的一部分被实现。An embodiment of the invention may also be implemented as a component level product, as a single chip, application specific integrated circuit (ASIC), or with integration on a single chip, at a different level from the rest of the system, as separate components. The level of integration of the system is initially determined by speed or cost considerations. Due to the wide variety of modern processors, it is possible to use commercially viable processors that can be implemented in ways that go beyond ASIC implementations of existing systems. Alternatively, if the processor is available as an ASIC core or logic block, a commercially available processor may be implemented as part of an ASIC device having various functions implemented as firmware.

本发明也可以被嵌入计算机程序产品中，该计算机程序产品包括所有能够执行这里所描述的方法的特征，且当被下载到计算机系统中时，能够执行这些方法。这里所说的计算机程序可以采用一组指令的任何表达形式，如用任何语言、代码或符号表达，该组指令能够使一具有信息处理能力的系统执行直接或在将该指令以下列方式之一或全部处理后：a)转换成另一种语言、代码或符号，b)用不同材料形式复制，执行特定功能。然而，本领域的普通技术人员来说可以理解的计算机程序的其他方法可被本发明预期。The invention can also be embedded in a computer program product which comprises all the features enabling the implementation of the methods described herein and which, when downloaded into a computer system, is able to perform these methods. The computer program mentioned here may take any form of expression, such as any language, code or symbol, which can cause a system with information processing capabilities to execute the instructions directly or in one of the following ways: or fully processed: a) converted into another language, code or symbol, b) reproduced in a different material form to perform a specific function. However, other means of computer programs as would be understood by one of ordinary skill in the art are contemplated by the present invention.

虽然本发明已参考某些实施例进行了描述，对本领域的普通技术人员来说可以理解，各种改变及等同将不脱离本发明的范围。另外，很多对本发明所述内容的适合特别情况和材料的修改也不脱离本发明的范围。因此，本发明不限于所揭示的特定实施例，本发明将包括所有落入权利要求范围中的实施例。While the invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes and equivalents will be made without departing from the scope of the invention. In addition, many modifications may be made to suit a particular situation and material that are described herein without departing from the scope of the invention. Therefore, it is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

本申请主张申请日为2004年5月21日的美国临时专利申请60/568926(代理机构编号15747US01)的优先权。该申请在此作为本申请的全面参考。This application claims priority to US Provisional Patent Application 60/568926 (Attorney No. 15747US01), filed May 21, 2004. This application is hereby incorporated by reference in its entirety into this application.

本申请与以下申请有关，其中每件申请都可在此作为本申请的全面参考：This application is related to the following applications, each of which is incorporated herein by reference in its entirety:

美国专利申请序列号为10/963,677(代理机构案件编号15748US02)，申请日为2004年10月13日；U.S. Patent Application Serial No. 10/963,677 (Agency Case No. 15748US02), filed on October 13, 2004;

美国专利申请序列号为10/985,501(代理机构案件编号15749US02)，申请日为2004年11月10日；U.S. Patent Application Serial No. 10/985,501 (Agency Case No. 15749US02), filed on November 10, 2004;

美国专利申请序列号为 (代理机构案件编号15750US02)，申请日为2004年；The U.S. patent application serial number is (Agency Case No. 15750US02), filed in 2004 ;

美国专利申请序列号为10/985,110(代理机构案件编号15751US02)，申请日为2004年11月10日；U.S. Patent Application Serial No. 10/985,110 (Agency Case No. 15751US02), filed on November 10, 2004;

美国专利申请序列号为10/981,218(代理机构案件编号15754US02)，申请日为2004年11月04日；U.S. Patent Application Serial No. 10/981,218 (Agency Case No. 15754US02), filed on November 04, 2004;

美国专利申请序列号为10/965,172(代理机构案件编号15756US02)，申请日为2004年10月13日；U.S. Patent Application Serial No. 10/965,172 (Agency Case No. 15756US02), filed on October 13, 2004;

美国专利申请序列号为10/971,931(代理机构案件编号15757US02)，申请日为2004年10月25日；U.S. Patent Application Serial No. 10/971,931 (Agency Case No. 15757US02), filed on October 25, 2004;

美国专利申请序列号为10/974,179(代理机构案件编号15759US02)，申请日为2004年10月27日；U.S. Patent Application Serial No. 10/974,179 (Agency Case No. 15759US02), filed on October 27, 2004;

美国专利申请序列号为10/974,872(代理机构案件编号15760US02)，申请日为2004年10月27日；U.S. Patent Application Serial No. 10/974,872 (Agency Case No. 15760US02), filed on October 27, 2004;

美国专利申请序列号为10/970,923(代理机构案件编号15761US02)，申请日为2004年10月21日；U.S. Patent Application Serial No. 10/970,923 (Agency Case No. 15761US02), filed on October 21, 2004;

美国专利申请序列号为10/963,680(代理机构案件编号15762US02)，申请日为2004年10月13日；U.S. Patent Application Serial No. 10/963,680 (Agency Case No. 15762US02), filed on October 13, 2004;

美国专利申请序列号为 (代理机构案件编号15763US02)，申请日为2004年；The U.S. patent application serial number is (Agency Case No. 15763US02), filed in 2004 ;

美国专利申请序列号为 (代理机构案件编号15792US01)，申请日为2004年；The U.S. patent application serial number is (Agency Case No. 15792US01), filed in 2004 ;

美国专利申请序列号为 (代理机构案件编号15810US02)，申请日为2004年；及The U.S. patent application serial number is (Agency Case No. 15810US02), filed in 2004 ;and

美国专利申请序列号为 (代理机构案件编号15811US02)，申请日为2004年。The U.S. patent application serial number is (Agency Case No. 15811US02), filed in 2004 .