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CN1797997A - Transmission system of parallel 12 routes 10Gb/s very short distance - Google Patents

Transmission system of parallel 12 routes 10Gb/s very short distance
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CN1797997A
CN1797997ACN 200410098997CN200410098997ACN1797997ACN 1797997 ACN1797997 ACN 1797997ACN 200410098997CN200410098997CN 200410098997CN 200410098997 ACN200410098997 ACN 200410098997ACN 1797997 ACN1797997 ACN 1797997A
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陈弘达
周毅
左超
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Institute of Semiconductors of CAS
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一种12路并行10Gb/s甚短距离传输系统,包括:一个OC-192成帧器,生成16路STM-4信号,通过分路转换器变为10路信号,生成1路奇偶校验信号和1路CRC校验信号,然后传入一个传输控制器中调整,使每路信道上都传输数据,然后传入一个8B/10B编码器编码后进入一个并/串转换器,变为串行信号,接收控制器把12路混合信号恢复成10路数据信号和1路奇偶校验信号1路CRC校验信号,同时实现线缆对称交叉检测和帧同步功能,通过检错&纠错器进行检错和纠错后变为16路STM-4信号传给一个OC-192成帧器;12路并行10Gb/s甚短距离传输系统把10路数据信道、1路纠错信道和1路检错信道变为12路同时传输数据和纠错检错信号的混合信道,并行传输数据。

Figure 200410098997

A 12-channel parallel 10Gb/s very short-distance transmission system, including: an OC-192 framer, which generates 16 channels of STM-4 signals, which are converted into 10 channels of signals through a splitter converter, and generates 1 channel of parity check signals and 1 channel of CRC check signal, and then sent to a transmission controller for adjustment, so that data is transmitted on each channel, and then passed to an 8B/10B encoder for encoding and then enters a parallel/serial converter to become serial signal, the receiving controller restores 12 channels of mixed signals into 10 channels of data signals, 1 channel of parity check signals and 1 channel of CRC check signals. After error detection and error correction, 16 channels of STM-4 signals are transmitted to an OC-192 framer; 12 channels of parallel 10Gb/s very short-distance transmission system uses 10 channels of data channels, 1 channel of error correction channels and 1 channel of detection The error channel becomes 12 mixed channels that simultaneously transmit data and error correction and detection signals, and transmit data in parallel.

Figure 200410098997

Description

12 tunnel parallel 10Gb/s very short distance transmission systems
Technical field
The present invention relates to transmit the very short distance transmission system that digit rate is 10Gb/s, particularly the very short distance transmission system of a kind of 12 tunnel parallel 10Gb/s.
Background technology
Along with the paces of global IT application process constantly quicken, network technology obtains fast development, and is also increasing to the demand of Network Transmission bandwidth.The present a kind of 10Gb/s very short distance transmission system that exists, use 12 tunnel vertical-cavity surface-emitting laser array with and parallel light transceiving module 300 meters transfer of data that realize 10Gb/s apart from the lining, but it adopts 10 path channels transmission payload user data, the scheme of 2 path channels transmitting control datas exists channel resource waste, the problem that efficiency of transmission is not high.
Summary of the invention
The purpose of this invention is to provide a kind of 12 tunnel novel parallel 10Gb/s very short distance transmission systems, have more high efficiency, bigger flexibility, 12 tunnel parallel very short distance transmission systems of employing VCSEL and 12 road multimode fiber bands.
The present invention's a kind of 12 tunnel parallel 10Gb/s very short distance transmission systems is characterized in that, comprising:
An OC-192 framer, generate 16 road STM-4 signals, this frame signal is this 16 tunnel conversion of signals that 10 road signals generate 1 tunnel parity signal and 1 tunnel CRC check signal simultaneously by a decommutator, 10 road signals after the conversion and 1 tunnel parity signal are adjusted sequential by a buffer memory, import into simultaneously in the transmission control unit (TCU) with 1 tunnel CRC check signal then, transmission control unit (TCU) is adjusted the data of 12 road signals of input, make all transmitting data information and control informations on every path channels, do not transmitted the dedicated channel of parity signal and CRC check signal this moment, this 12 road signal enters a parallel/serial transducer after importing a 8B/10B encoder encodes into, be converted to serial signal, by a parallel optical transmission module transmission, signal passes to a parallel Optical Receivers, be received the back and be converted to parallel signal by a serial/parallel transducer, parallel signal passes through to import a reception controller after the 8B/10B decoder for decoding, receive controller 12 tunnel mixed signals are reverted to 10 circuit-switched data signals and 1 tunnel parity signal, 1 tunnel CRC check signal, realize cable symmetrical chiasma measuring ability simultaneously, frame synchronization function, realize cable symmetrical chiasma measuring ability simultaneously, frame synchronization function, signal is undertaken importing Jian Cuo ﹠amp after the bit aligned by a buffer queue then; Error-corrector is carried out EDC error detection and correction, and being converted to 16 road STM-4 signals through the data-signal behind the EDC error detection and correction, 16 road STM-4 signals are passed to an OC-192 framer at last;
12 tunnel parallel 10Gb/s very short distance transmission systems become 12 road mixed channels that transmit data and error correcting and detecting signal simultaneously, parallel transmission data to 10 circuit-switched data transmission channels, 1 road error-correcting channel and 1 tunnel error detection channel.
Wherein this transmission system is 12 tunnel parallel very short distance transmission systems of a kind of VCSEL of employing and 12 road multimode fiber bands.
Wherein the defeated device of transmission control is the controller that 16 road STM-4 signals are reset, it is converted to 12 channel parallel data pieces to a STM-64 frame of being made up of 16 road STM-4 frames, its 12969 row bytes that begin are data and the error correction of STM-64,12961 to be listed as 14040 row bytes be the error detection byte, and error correction is inserted in the 12960 row bytes of beginning.
Wherein receiving controller is that 12 tunnel mixed signals that receive are reverted to 10 circuit-switched data signals and 1 tunnel parity signal, 1 tunnel CRC check signal, the signal that receives a frame ofcontroller reception 14040 is listed as totally, from wherein extracting data-signal, be mapped as 10 road parallel signals, extract parity signal and CRC check signal again, be mapped as 1 road signal respectively, 12 road signal parallels transmission of generation.
Wherein receive controller to 12 the bit signals detections of first row of totally 14040 row of first frame signal, normal condition is the 1 the road to the 6 the tunnel to be the A1 byte, the the 7 the road to the 12 the tunnel is the A1 byte, the the 1 the road to the 6 the tunnel is the A1 byte if cable is instead inserted, the the 7 the road to the 12 the tunnel is the A1 byte, can judge the situation that cable connects by this species diversity, realize that the cable symmetrical chiasma detects, avoid cable instead to insert.
Wherein receiving controller by first frame the 3rd row A1 that receives is detected, is A1 in conjunction with 6 bytes of the 1st row, and 6 bytes are the situation of A1, determine frame head, and achieve frame is synchronous.
The present invention adopts the method for transmitting payload user data and control data in 12 tunnel transmission channels simultaneously, has strengthened the harmony of transfer of data, has reduced the bandwidth waste on original 2 tunnel control data transmission channels, is improved on performance and efficient.
Description of drawings
For further specifying concrete technology contents of the present invention, below in conjunction with embodiment and accompanying drawing describes in detail as after, wherein:
Fig. 1 is 12 tunnel novel parallel 10Gb/s very short distance transmission system structure charts;
Fig. 2 is the channel rearrangement figure of novel 12 tunnel parallel 10Gb/s very short distance transmission systems;
Fig. 3 is the transmission frame-form figure of novel 12 tunnel parallel 10Gb/s very short distance transmission systems;
Fig. 4 is the 12 tunnel novel parallel 10Gb/s very short distance transmission system frame assumption diagrams that contain error correction;
Fig. 5 is the 12 tunnel novel parallel 10Gb/s very short distance transmission system frame assumption diagrams that contain error correction and error detection byte.
Embodiment
Of thepresent invention 12 tunnel parallel 10Gb/s very short distance transmission systems, as shown in Figure 1, it comprises transmission and receives two parts.Sending part is to send an OC-192 frame by an OC-192 framer 101, and this frame is 16 road STM-4 signals, and every road frequency is 622MHz.By adecommutator 102 is this 16 tunnel conversion ofsignals 10 road signals, generate 1 tunnel parity signal and 1 tunnel CRC check signal simultaneously, every road signal takies a channel, wherein 10 circuit-switched data signals take 1~10 channel, parity signal takies the 11st channel, and the CRC check signal takies the 12nd channel.10 road signals after the conversion and 1 tunnel parity signal are adjusted sequential by abuffer memory 103, import in the transmission control unit (TCU) 104 with 1 tunnel CRC check signal then.The data of 12 road signals of 104 pairs of inputs of transmission control unit (TCU) are adjusted, and make all transmitting data information and control informations on every path channels, comprise the 11 road and the 12nd path channels, have not transmitted the dedicated channel of parity signal and CRC check signal this moment.This 12 road signal enters a parallel/serial transducer 106 after importing a 8B/10B encoder 105 codings into, is converted to serial signal, by paralleloptical transmission module 107 transmission.Receiving unit is that a parallelOptical Receivers 108 receives the signal that paralleloptical transmission module 107 transmits, and is converted to parallel signal by a serial/parallel transducer 109, byreception controller 111 of a 8B/10B decoder 110 decoding backinputs.Receive controller 111 12 tunnel mixed signals are reverted to 10 circuit-switched data signals and 1 tunnel parity signal, 1 tunnel CRC check signal.Undertaken importing Jian Cuo ﹠amp after the bit aligned by abuffer queue 112 then; Error-corrector 113 is carried out EDC error detection and correction, is 10 circuit-switched data conversion of signals that 16 road STM-4 signals are passed to an OC-192framer 114 at last, has finished the process that sends to reception from data.
The present invention has a transmission control unit (TCU) 104 and a reception controller 111.The major function of transmission control unit (TCU) 104 is to be 10 circuit-switched data signals and 1 tunnel parity signal, 1 tunnel CRC check conversion ofsignals 12 tunnel mixed signals, and receivingcontroller 111 mainly is that 12 tunnel mixed signals are reverted to 10 circuit-switched data signals and 1 tunnel parity signal, 1 tunnel CRC check signal.
One, the course of work of transmission control unit (TCU) 104 as shown in Figure 2, it need realize that 16 road STM-4 signals reset to the channel of 12 road parallel signals, is implemented as follows:
1,16 to 12 tunnel parallel conversion is finished by SERDES.Be the mode of mapping equally.Every road STM-4 signal sequence is mapped in 1~12 channel successively, first byte of the first via is fromchannel 1 transmission, first byte of the second tunnel is shone upon into second channel, the 13rd byte of the first viareturns channel 1, according to such order, mapping up to entire frame is finished, and carries out the operation of next frame again.
2, go tiltedly to move, frame synchronization and cable symmetrical chiasma measuring ability can have two kinds of implementation methods, the one, the frame first byte is replaced, and realizes in the 8B/10B cataloged procedure.The 2nd, in last figure, the 7th~12 tunnel first frame A1 byte negate obtains the A1 byte, realizes cable symmetrical chiasma measuring ability, the whole negates of the 3rd row A1 byte is obtained the A1 byte, with the achieve frame synchronizing function.
3, the realization of fault monitoring function.Each road of previous " block frame " is carried out after BIP-8 calculates, and 12 BC bytes that obtain are inserted the 18th row of this frame successively, promptly after the first row A2 byte.Receiving terminal to each road of this frame carry out BIP-8 calculate after and the 18th row byte of next frame compare, to find whether error code has appearred in a certain road.Do not carry out error correction, the frame structure that transmission control unit (TCU) 104 sends during error detection as shown in Figure 3.
Through after the above-mentioned processing, this 12 road parallel scheme has been realized frame synchronization and cable symmetrical chiasma measuring ability and channel error monitoring function, but not error correction.Behind the 8B/10B coding, every road speed is 1.0368Gb/s.
4, the realization of error correction, this function is optional.Realize error correction, must add more redundant information, can adopt FEC, but the complexity of realization needs special module to design realization.
(1) generation of error correction as shown in Figure 4: on 1,2 basis, 12960 row of each the STM-64 frame among Fig. 3 are carried out vertical bit XOR, obtained the error correction P of 12960 bytes altogether, laterally insert the last of these frame data in turn.Each STM-64 frame expands to 14040 * 12 bytes like this, wherein is listed as 14040 from 12961 and classifies 1080 * 12 error correction as.
The generation of (2) error detection byte is as shown in Figure 5: each road is that unit is divided into one " dummy data block " with 1080 bytes, successively this data block is carried out the CRC check of CCITTCRC 16 generator polynomials (X16+X12+X5+1), each rood is to the verification redundancy of 26 bytes like this, and wherein the 26th byte is the CRC check to error correction.This 26 byte is carried out the CRC check of CCITT CRC 16 once more, 2 bytes that obtain adding, each road obtains the redundant CRC check byte of 28 bytes altogether like this.A block frame obtains the CRC check of 336 bytes altogether.4~16 (A1) of the next frame first via, 18~32 (A2) byte are inserted in 28 byte verifications of the first via in turn.
Two, receivecontroller 111 and carry out following work:
1), carries out frame synchronization and the monitoring of cable symmetrical chiasma according to the parallel 3 row bytes of first frame.Receiving controller 111 passes through 12 the bit signals detections of first row of 14040 row of first frame signal totally, normal condition is the 1 the road to the 6 the tunnel to be the A1 byte, the the 7 the road to the 12 the tunnel is the A1 byte, the the 1 the road to the 6 the tunnel is the A1 byte if cable is instead inserted, the the 7 the road to the 12 the tunnel is the A1 byte, can judge the situation that cable connects by this species diversity, realize that the cable symmetrical chiasma detects, avoid cable instead to insert.Receiving controller 111 by first frame the 3rd row A1 that receives is detected, is A1 in conjunction with 6 bytes of the 1st row, and 6 bytes are A1, determine frame head, and achieve frame is synchronous.
2), latter two byte by CRC check carries out verification to the CRC on each road of this frame, if CRC is correct, then changes next step over to, otherwise thinks that mistake appears in CRC, do not carry out the EDC error detection and correction function, directly changes for the 5th step over to.
3),error correction 12961~14040 row on each road of previous frame are carried out CRC check respectively, compare, judge whether error correction mistake occurs, does not have mistake to change next step over to, go on foot otherwise directly change the 5th over to CRC 26 bytes of this frame.
4), all do not have on the wrong basis picking up mistake and error correction, respectively each road of previous frame is carried out carrying out CRC check according to the size of 1080 bytes " dummy data block ", if occur 1 tunnel mistake in 12 the tunnel, then recover by the corresponding error correction in the previous frame.If the above mistake of two-way then changed for the 5th step over to.
5), do not carry out EDC error detection and correction, the beginning data rearrangement recovers 16 road parallel signals.
The very short distance transmission system of thenovel 12 tunnel parallel 10Gb/s that the present invention produces has been compared following difference with the very short distance transmission system of the 12 tunnel parallel 10Gb/s of VSR4-1.0:
One, the 12 tunnel all is used for data information, at the check information of the last additional redundancy of block frame.The size of whole block frame is 14040 * 12 bytes, and the size of a block frame of OIF-VSR 4-1.0 is 15552 * 12 bytes, has reduced by 1512 * 12 bytes.
Two, utilized A1 and the A2 byte that repeats in the next frame, carried out the CRC check of this frame, OIF-VSR 4-1.0 then is that additional parallel two-way carries out verification, and is redundant big.After this programme was encoded through 8B/10B, redundancy was 35%.
Three, because error correction is optional, for channel situation preferably, can carry out error correction, thenerror correction 12961~14040 row can not add, and in this case, do not have additional redundancy.Behind the 8B/10B coding, every road speed is 1.0368Gb/s.Even and OIF-VSR 4-1.0 does not adopt additional two-way, the link rate on each road still is 1.25Gb/s.

Claims (6)

Translated fromChinese
1、一种12路并行10Gb/s甚短距离传输系统,其特征在于,包括:1. A 12-way parallel 10Gb/s very short-distance transmission system, characterized in that it comprises:一个OC-192成帧器,生成16路STM-4信号,该帧信号通过一个分路转换器把这16路信号转换为10路信号同时生成1路奇偶校验信号和1路CRC校验信号,转换后的10路信号和1路奇偶校验信号通过一个缓存调整时序,然后与1路CRC校验信号同时传入一个传输控制器中,传输控制器对输入的12路信号的数据进行调整,使每路信道上都传输数据信息和控制信息,此时已经没有传输奇偶校验信号和CRC校验信号的专用信道,这12路信号传入一个8B/10B编码器编码后进入一个并/串转换器,转换为串行信号,通过一个并行光发送模块传输,信号传到一个并行光接收模块,被接收后通过一个串/并转换器转换为并行信号,并行信号通过一个8B/10B译码器译码后输入一个接收控制器,接收控制器把12路混合信号恢复成10路数据信号和1路奇偶校验信号1路CRC校验信号,同时实现线缆对称交叉检测功能、帧同步功能,然后信号通过一个队列缓冲进行比特对齐后输入检错&纠错器进行检错和纠错,并把经过检错和纠错后的数据信号转换为16路STM-4信号,16路STM-4信号最后传给一个OC-192成帧器;An OC-192 framer generates 16 channels of STM-4 signals, and the frame signals are converted into 10 channels of signals through a splitter converter and simultaneously generate 1 channel of parity check signal and 1 channel of CRC check signal , the converted 10-way signal and 1-way parity signal pass a buffer to adjust the timing, and then transmit it to a transmission controller at the same time as the 1-way CRC check signal, and the transmission controller adjusts the data of the input 12-way signal , so that data information and control information are transmitted on each channel. At this time, there is no dedicated channel for transmitting parity check signals and CRC check signals. Serial converter, converted to serial signal, transmitted through a parallel optical sending module, the signal is transmitted to a parallel optical receiving module, after being received, it is converted into a parallel signal through a serial/parallel converter, and the parallel signal is transmitted through an 8B/10B translator After decoding, the coder inputs a receiving controller, and the receiving controller restores 12 channels of mixed signals into 10 channels of data signals, 1 channel of parity check signal and 1 channel of CRC check signal, and at the same time realizes the cable symmetrical cross detection function and frame synchronization function, and then the signal is bit-aligned through a queue buffer and then input to the error detection & error correction device for error detection and error correction, and the data signal after error detection and error correction is converted into 16-way STM-4 signal, 16-way STM The -4 signal is finally passed to an OC-192 framer;12路并行10Gb/s甚短距离传输系统把10路数据传输信道、1路纠错信道和1路检错信道变为12路同时传输数据和纠错检错信号的混合信道,并行传输数据。The 12-channel parallel 10Gb/s very short-distance transmission system transforms 10 channels of data transmission, 1 channel of error correction and 1 channel of error detection into 12 channels of mixed channels that simultaneously transmit data and error correction and error detection signals, and transmit data in parallel.2、根据权利要求1所说的12路并行10Gb/s甚短距离传输系统,其特征在于,其中该传输系统是一种采用VCSEL和12路多模光纤带的12路并行甚短距离传输系统。2. The 12-channel parallel 10Gb/s very short-distance transmission system according to claim 1, wherein the transmission system is a 12-channel parallel very short-distance transmission system using VCSEL and 12-channel multimode optical fiber ribbons .3、根据权利要求1所述的12路并行10Gb/s甚短距离传输系统,其特征在于,其中传输控制输器是对16路STM-4信号重排的控制器,它把一个由16路STM-4帧组成的STM-64帧转换为12路并行数据块,其开始的12969列字节是STM-64的数据和纠错字节,12961列到14040列字节为检错字节,纠错字节插入开始的12960列字节中。3. The 12-way parallel 10Gb/s very short-distance transmission system according to claim 1, wherein the transmission control transmitter is a controller for rearranging 16-way STM-4 signals, and it converts a 16-way STM-4 signal The STM-64 frame composed of STM-4 frames is converted into 12 parallel data blocks. The first 12969 column bytes are STM-64 data and error correction bytes, and the 12961 column to 14040 column bytes are error detection bytes. Error correction bytes are inserted in the first 12960 column bytes.4、根据权利要求1所述的12路并行10Gb/s甚短距离传输系统,其特征在于,其中接收控制器是把接收的12路混合信号恢复成10路数据信号和1路奇偶校验信号1路CRC校验信号,接收控制器接收的一个帧的信号共14040列,从其中提取出数据信号,映射为10路并行信号,再提取奇偶校验信号和CRC校验信号,分别映射为1路信号,生成的12路信号并行传输。4. The 12-channel parallel 10Gb/s very short-distance transmission system according to claim 1, wherein the receiving controller recovers the received 12-channel mixed signal into 10-channel data signal and 1-channel parity signal 1 channel CRC check signal, the receiving controller receives a frame signal with a total of 14040 columns, extracts the data signal from it, and maps it to 10 channels of parallel signals, then extracts the parity check signal and CRC check signal, and maps them to 1 channel respectively Signals of 12 channels are generated and transmitted in parallel.5、根据权利要求1所述的12路并行10Gb/s甚短距离传输系统,其特征在于,其中接收控制器对第一个帧信号共14040列的第一列的12个比特信号检测,正常情况为第1路到第6路为A1字节,第7路到第12路为 A1字节,如果线缆反插则第1路到第6路为 A1字节,第7路到第12路为A1字节,通过这种差异可判断线缆连接的情况,实现线缆对称交叉检测,避免线缆反插。5. The 12-way parallel 10Gb/s very short-distance transmission system according to claim 1, wherein the receiving controller detects the 12-bit signals in the first column of the first frame signal with a total of 14040 columns, and it is normal The situation is that the 1st to 6th roads are A1 bytes, and the 7th to 12th roads are A1 byte, if the cable is inserted backwards, the 1st to 6th channels are A1 byte, the 7th to the 12th are A1 bytes, through this difference, the cable connection can be judged, and the symmetrical cross detection of cables can be realized to avoid reverse insertion of cables.6、根据权利要求1所述的12路并行10Gb/s甚短距离传输系统,其特征在于,其中接收控制器通过对接收的首帧第3列 A1检测,结合第1列6个字节为A1,6个字节为 A1的情况,确定帧头,实现帧同步。6. The 12-channel parallel 10Gb/s very short-distance transmission system according to claim 1, wherein the receiving controller controls the third column of the received first frame A1 detection, combined with the 6 bytes in the first column is A1, and the 6 bytes are In the case of A1, the frame header is determined to realize frame synchronization.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
CN101523312B (en)*2006-08-082011-08-03西门子工业公司 Apparatus, system and method for assigning PLC module addresses
CN103023518A (en)*2012-12-262013-04-03中国科学院微电子研究所Error correction method of cyclic Hamming code based on parallel coding and decoding
WO2022179407A1 (en)*2021-02-262022-09-01华为技术有限公司Data encoding method, data decoding method and related device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
CN101523312B (en)*2006-08-082011-08-03西门子工业公司 Apparatus, system and method for assigning PLC module addresses
CN101501586B (en)*2006-08-082012-06-27西门子工业公司 Apparatus, system and method for initializing PLC modules
CN103023518A (en)*2012-12-262013-04-03中国科学院微电子研究所Error correction method of cyclic Hamming code based on parallel coding and decoding
CN103023518B (en)*2012-12-262016-04-27中国科学院微电子研究所Error correction method of cyclic Hamming code based on parallel coding and decoding
WO2022179407A1 (en)*2021-02-262022-09-01华为技术有限公司Data encoding method, data decoding method and related device

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