CN1790735A - Silicon carbide semiconductor device and method for manufacturing the same - Google Patents

Abstract

A silicon carbide semiconductor device includes: a semiconductor substrate having a silicon carbide substrate, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; a trench penetrating the second and the third semiconductor layers to reach the first semiconductor layer; a channel layer on a sidewall and a bottom of the trench; an oxide film on the channel layer; a gate electrode on the oxide film; a first electrode connecting to the third semiconductor layer; and a second electrode connecting to the silicon carbide substrate. A position of a boundary between the first semiconductor layer and the second semiconductor layer is disposed lower than an utmost lowest position of the oxide film.

Description

Manufacturing silicon carbide semiconductor device and manufacture method thereof

Technical field

The present invention relates to the manufacture method of a kind of manufacturing silicon carbide semiconductor device and a kind of manufacturing silicon carbide semiconductor device.

Background technology

Though the current semi-conducting material that has comparative advantage is Si, SiC a kind ofly borrows its physical property and electric property and is better than the semi-conducting material of Si.Particularly, the energy gap of SiC is three times of Si, and the dielectric breakdown voltage of SiC is seven times of Si, and the thermal conductivity of SiC is three times of Si.Therefore, when making the device of high power of future generation and ultra-low calorie loss, SiC is a kind of semi-conducting material of expectation.

For example at United States Patent (USP) 6,570, the groove-shaped vertical power-type mos field effect transistor (power-type MOSFET) of a kind of SiC of use is disclosed in 185, Figure 16 shows the cross section structure of this power-type MOSFET.

As shown in figure 16, in this power-type MOSFET, N^-Type drift layer 102 is formed on N⁺On the surface of type SiC substrate 101.N type district 103 and P type base 104 are formed at N in this order^-On the type drift layer 102.N⁺Type source region 105 is formed on the surface portion of P type base 104.In addition, groove 106 forms and can run through N⁺Type source region 105, P type base 104 and N type district 103, and arrive N^-Type drift layer 102.Grid 108 is formed in the groove 106 by crossing oxidation film of grid 107.P⁺Type layer 109 is formed at the bottom of groove 106.

In having the power-type MOSFET of said structure, because P⁺Type layer 109 is formed at the bottom of groove 106, and when voltage was applied on the grid 108, the electric current of the raceway groove that will form in P type base 104 of flowing through flow through N type district 103.Like this, the situation that does not have N type district 103 with semiconductor device is compared, and can reduce the conducting resistance of power-type MOSFET.This is that promptly, N type district 103 has low resistance because N type district 103 has high impurity concentration.

In addition, because P⁺Type layer 109 is formed on groove 106 bottoms, can prevent that the corner part generation electric field between channel bottom and trenched side-wall from concentrating.Like this, just can protect oxidation film of grid 107 not to be damaged in this part.

But, work as P⁺When type layer 109 is formed at groove 106 bottoms, need be at P⁺(because electricity is therebetween isolated) spaced apart between type layer 109 and the P type base 104, perhaps N type layer 103 need be formed below P type base 104, as shown in figure 16.Therefore, in the previous case, it is big that the degree of depth of groove becomes, and under latter event, needs other step to form N type layer 103.

Summary of the invention

In view of the above problems, the object of the present invention is to provide a kind of SiC semiconductor device and manufacture method thereof.

A kind of manufacturing silicon carbide semiconductor device, comprise: semiconductor chip, it comprise first conductivity type or the second conductive silicon carbide substrate, by first conductive silicon carbide make and its impurity concentration is lower than first semiconductor layer of silicon carbide substrate, second semiconductor layer made by second conductive silicon carbide, by the 3rd semiconductor layer that first conductive silicon carbide is made, they are storehouse in this order; Groove, it is positioned at the cellular zone of semiconductor chip, and runs through the second and the 3rd semiconductor layer, arrives first semiconductor layer; Channel layer, it is first conductivity type, and is positioned on the sidewall and bottom of groove; Oxidation film, it is arranged on the channel layer of groove, and comprises the part as oxidation film of grid; Grid, it is arranged on the surface of groove oxidation film; First electrode, it is electrically connected with the 3rd semiconductor layer; And second electrode, it is electrically connected with silicon carbide substrate.Boundary position between first semiconductor layer and second semiconductor layer is lower than the extreme lower position of oxidation film in the groove.

In said structure, the position of second semiconductor layer that is positioned at the groove both sides is lower than the extreme lower position of oxidation film.Therefore, produce a kind of junction structure, wherein, the first conductive type of channel layer is being clipped on the both sides of this channel layer between two second semiconductor layers of second conductivity type.Therefore, drain potentials is interrupted by this junction structure, thereby depletion layer is difficult to extend through the top of channel layer.

Therefore, can prevent to concentrate at the bottom and the generation electric field of the corner between the sidewall of groove.Like this, just can protect the oxidation film of this corner can not rupture.

In addition, only, just can obtain this structure by the groove of slotting out of the boundary vicinity between first semiconductor layer and second semiconductor layer.Therefore, the degree of depth of groove can not become big.In addition, need be at P⁺Form N type layer below the type base.Like this, just do not need extra step, thereby vertically the manufacturing process of power-type MOSFE can obtain simplifying.

Like this, in this device, base and be positioned at below the groove and to have a layer of identical conduction type electrically isolated from one with the base.In addition, can simplify the manufacture process of this device.

Alternatively, the impurity concentration of second conductivity type, second impurity reduces to the border first semiconductor layer and second semiconductor layer gradually from the height and position of the oxidation film that is positioned at channel bottom in second semiconductor layer, and the impurity concentration of first conductive-type impurity is higher than the impurity concentration of first conductive-type impurity in first semiconductor layer in the channel layer.In said structure, can improve withstand voltage and the threshold value maintenance grid groove.

Alternatively, this device also comprises the first conductivity type conductive formation, and it is formed on below the oxidation film of channel bottom.Length from the extreme lower position of oxidation film to channel bottom is corresponding to the thickness summation of the thickness and the channel layer of conductive formation.

Like this, this device comprises the first conductivity type conductive formation, and this conductive formation is formed at below the oxidation film on the channel bottom.Therefore, because electric current flows through this conductive formation, reduced the conducting resistance of this manufacturing silicon carbide semiconductor device.In addition, in this structure, the length from the extreme lower position of oxidation film to channel bottom becomes the thickness that equals conductive formation and the thickness summation of channel layer.

Herein, the plane orientation of trenched side-wall is set as (1-100) (i.e. (1 100)) surfaces or (11-20) (i.e. (11 20)) surface, and the Thickness Design one-tenth that is positioned at a part of channel layer on the channel bottom is greater than the thickness that is positioned at a part of channel layer on the trenched side-wall.

In this case, for example, the thickness that is formed at a part of channel layer on the channel bottom is that part of 1-5 times that is formed on the trenched side-wall.In addition, the doping content of first conductive-type impurity is that part of one to five times that is formed on the channel bottom in a part of channel layer on being formed at trenched side-wall.

Alternatively, the structure of this device is that silicon carbide substrate is first conductivity type; A plurality of channel shaped are formed in this substrate, each groove from the back side of silicon carbide substrate to the first semiconductor layer setting; These grooves are embedded with the second conductive-type impurity layer; Second electrode contacts with impurity layer with silicon carbide substrate.

When manufacturing silicon carbide semiconductor device was IGBT, this silicon carbide substrate was first conductivity type, and a plurality of channel shaped are formed in this substrate, and each groove is embedded with the second conductive-type impurity layer, can eliminate the threshold value of PN electromotive force.

Alternatively, silicon carbide substrate is second conductivity type, and a plurality of channel shaped are formed in this substrate, and to the first semiconductor layer setting, each groove is embedded with the first conductive-type impurity layer to this groove from the back side of silicon carbide substrate.

A kind of method of making manufacturing silicon carbide semiconductor device, may further comprise the steps: prepare a semiconductor chip, it comprises first conductivity type or the second conductive silicon carbide substrate, is made and impurity concentration is lower than first semiconductor layer of silicon carbide substrate, second semiconductor layer of being made by second conductive silicon carbide and the 3rd semiconductor layer of being made by first conductive silicon carbide by first conductive silicon carbide, and they are storehouse in this order; Form groove in the semiconductor chip cellular zone, this groove runs through the second and the 3rd semiconductor layer and arrives first semiconductor layer; In this groove, form first conductivity type the 4th semiconductor layer by epitaxial growth method, make a part the 4th semiconductor layer that is positioned at channel bottom bigger than that part of thickness that is positioned on the trenched side-wall; Form oxidation film by thermal oxidation process on trench wall, make this oxidation film comprise a part that is used as oxidation film of grid, it contacts with the 4th semiconductor layer, thereby the 4th semiconductor layer produces channel layer; In groove, form grid on the surface of oxidation film; Form first electrode that is electrically connected with the 3rd semiconductor layer; Form second electrode that is electrically connected with silicon carbide substrate.In the step that forms oxidation film, carry out thermal oxidation process, thereby the position on the border between first semiconductor layer and second semiconductor layer is lower than the extreme lower position of oxidation film in the groove.

Said method produces following SiC device.In this device, drain potentials is interrupted by junction structure, thereby depletion layer is difficult to extend through the top of channel layer.Like this, can prevent the oxidation film fracture of corner.In addition, this structure only just can produce by the groove of slotting out of the boundary vicinity between first semiconductor layer and second semiconductor layer.In addition, need be at P⁺Form N type layer below the type base.Like this, just do not need extra step, thereby simplified the manufacturing process of vertical power-type MOSFET.

Description of drawings

According to the detailed description of doing below with reference to accompanying drawing, above-mentioned and other purposes of the present invention, feature and advantage will be more obvious.In these accompanying drawings,

Fig. 1 is the cutaway view of the vertical power-type MOSFET of accumulation type of first embodiment of the invention;

Fig. 2 A is the doping content and the N of the N type impurity that intercepted along the line IIA-IIB among Fig. 1^-The distribution map of the thickness of type channel layer, the N of Fig. 2 B for being intercepted along the line IIC-IID among Fig. 1⁺The distribution map of the doping content of type conductive formation and oxidation film;

Fig. 3 is the cutaway view that shows the equipotential lines of vertical power-type MOSFET under not on-state;

Fig. 4 is the cutaway view according to the manufacture process of the vertical power-type MOSFET of first embodiment;

Fig. 5 is the cutaway view of manufacture process of the vertical power-type MOSFET of and then Fig. 4;

Fig. 6 is the cutaway view of manufacture process of the vertical power-type MOSFET of and then Fig. 5;

Fig. 7 is the cutaway view of manufacture process of the vertical power-type MOSFET of and then Fig. 6;

Fig. 8 is the cutaway view of manufacture process of the vertical power-type MOSFET of and then Fig. 7;

Fig. 9 is the cutaway view of manufacture process of the vertical power-type MOSFET of and then Fig. 8;

Figure 10 is N in the vertical power-type MOSFET of first embodiment^-Type layer and N⁺The cutaway view of the relation between the thickness of type layer;

Figure 11 A is the cutaway view of the vertical power-type MOSFET of second embodiment of the invention; Figure 11 B is the distribution map along the doping content of P conductive-type impurity among the vertical power-type MOSFET of the line XIE-XIF intercepting of Figure 11 A;

Figure 12 A is the cutaway view of the vertical power-type MOSFET of third embodiment of the invention; Figure 12 B is the distribution map along the doping content of P conductive-type impurity among the vertical power-type MOSFET of the line XIIG-XIIH intercepting of Figure 12 A; Figure 12 C is the distribution map along the doping content of N conductive-type impurity among the vertical power-type MOSFET of the line XIII-XIIJ intercepting of Figure 12 A;

Figure 13 is the cutaway view of the vertical power-type MOSFET of accumulation type of fourth embodiment of the invention;

Figure 14 is the cutaway view of the vertical power-type MOSFET of accumulation type of fifth embodiment of the invention;

Figure 15 is the cutaway view of the vertical power-type MOSFET of accumulation type of sixth embodiment of the invention;

Figure 16 is the cutaway view of the vertical power-type MOSFET of prior art.

Embodiment

(first embodiment)

Fig. 1 shows the cutaway view of cellular zone of groove-shaped vertical power-type MOSFET of the conduct accumulation type MOSFET of first embodiment of the invention.Tell about the structure of vertical power-type MOSFET shown in Figure 1 below.

N^-Type drift layer 2 is positioned at N⁺On the type substrate 1.P⁺Type base 3 and N⁺Type source region 4 is formed at N^-On the surface of type drift layer 2.In this embodiment, semiconductor chip is by N⁺Type substrate 1, N^-Type drift layer 2, P⁺Type base 3 and N⁺Type source region 4 is formed.

Groove 5 forms and can run through N⁺Type source region 4 and P⁺Type base 3, and arrive N^-Type drift layer 2.N^-Type channel layer 6 is formed on the inwall of groove 5.N⁺Typeconductive formation 7 is formed at the N that is positioned ongroove 5 bottoms^-On the surface portion oftype channel layer 6.

Oxidation film 8 forms and covers N^-Type channel layer 6, N⁺Typeconductive formation 7 and a part of N⁺Type source region 4.Be arranged ingroove 5 and also promptly be formed at a part ofoxidation film 8 ongroove 5 sidewalls as oxidation film ofgrid.Grid 9 is formed on the surface as thispartial oxide film 8 of oxidation film ofgrid.Grid 9 is made by polysilicon or metal.Thisgrid 9 ingroove 5 embeddings.

Gate line 11 is formed on thegrid 9 by unshowned interlayer dielectric among Fig. 1.Thisgate line 11 is electrically connected on thegrid 9.

Another groove that is used to contact 12 is formed at a part of substrate.This part is different from that part of substrate that forms groove 5.Contact trench 12 runs through N⁺Type source region 4, and arrive P⁺Type base 3.Be used to providefirst electrode 14 of source electrode to be formed on thecontact trench 12 that is used to contact.First electrode 14 is electrically connected to P by unshowned interlayer dielectric andcontact trench 12⁺Type base 3 and N⁺Type source region 4.

In addition,second electrode 19 is formed at N⁺The back side of type substrate 1.Second electrode 19 is as drain electrode.

The groove-shaped vertical power-type MOSFET of this embodiment constructs according to said structure.In this structure, the impurity concentration of each part and size are with as described below among the vertical power-type MOSFET.

N⁺The doping content oftype substrate 1 is 1 * 10¹⁹Cm^-3, N^-The doping content of type drift layer is 5 * 10¹⁵Cm^-3, P⁺The doping content oftype base 3 is 5 * 10¹⁸Cm^-3, N⁺The doping content intype source region 4 is 1 * 10²⁰Cm^-3

P⁺Type base 3 and N⁺The thickness summation intype source region 4 is slightly smaller than the size ofgroove 5 at depth direction.But this summation equals the size ofgroove 5 substantially, and they are for example 4-5 μ m.

N^-Type channel layer 6, N⁺Typeconductive formation 7 andoxidation film 8 are told about with reference to Fig. 2 A and Fig. 2 B.Fig. 2 A and 2B show respectively along the N of line IIA-IIB among Fig. 1 and line IIC-IID intercepting^-Type channel layer 6, N⁺The doping content of N type impurity and the distribution map of thickness in each of typeconductive formation 7 andoxidation film 8.

On the line IIA-IIB of Fig. 1, N^-The thickness oftype channel layer 6 is 0.2-0.5 μ m, and impurity concentration is 1 * 10¹⁶Cm^-3To 1 * 10¹⁷Cm^-3For example, shown in Fig. 2 A, in this embodiment, N^-The impurity concentration ofchannel layer 6 is 2 * 10¹⁶Cm^-3The thickness ofoxidation film 8 is equal to or less than 0.1 μ m, and impurity concentration is equal to or greater than 1 * 10¹⁷Cm^-3For example, shown in Fig. 2 A, in this embodiment, the impurity concentration ofoxidation film 8 is 1 * 10¹⁹Cm^-3On the line IIC-IID in Fig. 1, N^-The thickness ofchannel layer 6 is 0.6-1.5 μ m, and impurity concentration is 2 * 10¹⁵Cm^-3To 2 * 10¹⁶Cm^-3For example, shown in Fig. 2 B, in this embodiment, N^-The impurity concentration ofchannel layer 6 is 4 * 10¹⁵Cm^-3N⁺The thickness of typeconductive formation 7 is equal to or less than 0.2 μ m, and impurity concentration is equal to or greater than 2 * 10¹⁶Cm^-3For example, shown in Fig. 2 B, in this embodiment, N⁺The impurity concentration of typeconductive formation 7 is 2 * 10¹⁸Cm^-3The thickness ofoxidation film 8 is equal to or less than 1 μ m, and impurity concentration is equal to or greater than 2 * 10¹⁶Cm^-3For example, shown in Fig. 2 B, in this embodiment, the impurity concentration ofoxidation film 8 is 2 * 10¹⁸Cm^-3

Like this, in the vertical power-type MOSFET of this embodiment, the extreme lower position ofoxidation film 8 fromgroove 5 surface ofgroove 5 bottoms (that is, in the face of) to the length of the bottom ofgroove 5 greater than from as a part ofoxidation film 8 of oxidation film of grid length to the sidewall of groove 5.Particularly, the length from the extreme lower position ofoxidation film 8 to the bottom ofgroove 5 equals N^-The thickness oftype channel layer 6 and N⁺The length summation of the thickness of type conductive formation 7.For example, they are 0.8-1.7 μ m.In addition, from equaling to be positioned at N ongroove 5 sidewalls to the length of the sidewall ofgroove 5 as a part ofoxidation film 8 of oxidation film of grid^-The thickness of type channel layer 6.They for example are 0.2-0.5 μ m.

In this vertical power-type MOSFET with said structure, when voltage is applied on thegrid 9, at N^-Form accumulation type channel region in the type channel layer 6.Electric current flows betweenfirst electrode 14 andsecond electrode 19 by this channel region.

In this vertical power-type MOSFET, be positioned at the P ongroove 5 both sides according to this embodiment⁺The position oftype base 3 is lower than the extreme lower position of oxidation film 8.Therefore produce junction structure.In this junction structure, N^-The both sides of thischannel layer 6 oftype channel layer 6 fromgroove 5 bottoms are clipped in two P⁺Between the type base 3.Therefore, as shown in Figure 3, the junction structure that drain potentials is switched under the state interrupts, thereby depletion layer is difficult to extend through N^-The top oftype channel layer 6.

Therefore, can prevent to concentrate at the bottom and the generation electric field of the corner between the sidewall of groove 5.Like this, can protect theoxidation film 8 of this corner not ruptured.

In addition, only need pass through according to the structure of this embodiment at N^-Type drift layer 2 and P⁺Boundary vicinity between thetype base 3groove 5 of slotting out just can produce.Like this, just can not increase the degree of depth ofgroove 5 greatly.In addition, do not need as prior art at P⁺Form N type layer below the type base 3.Therefore, unnecessary employing forms the additional step of N type layer.Like this, simplified the manufacturing process of vertical power-type MOSFET.

Next, with reference to the process drawing of the vertical power-type MOSFET shown in Fig. 4-9 manufacture method according to the vertical power-type MOSFET of this embodiment is described.

(step shown in Figure 4)

At first, prepare substrate.In this substrate, N^-Type drift layer 2, P⁺Type base 3 andN⁺4 epitaxial growths of type source region are at N⁺On the surface of type substrate 1.This N⁺Type substrate 1 has the primary flat on skew surface, [1-100] (i.e. [1100]).For example, N⁺The doping content oftype substrate 1 is 1 * 10¹⁹Cm^-3, N^-The doping content oftype drift layer 2 is 5 * 10¹⁵Cm^-3, P⁺The doping content oftype base 3 is 5 * 10¹⁸Cm^-3, N⁺The doping content intype source region 4 is 1 * 10²⁰Cm^-3The surface of substrate is [1-100]-skew surface, because every layer occupies N⁺The surface state oftype substrate 1.

(step shown in Figure 5)

Prepare a mask with opening, opening be arranged on substrate surface on the corresponding position of part of groove to be formed on.By mask with the about 4-5 μ of substrate etching m.Like this, form groove 5.At this moment, for example the layout of mask be arranged to make the sidewall of groove with (1-100)-surface or (11-20)-surface coincides.

(step shown in Figure 6)

After used mask is removed in the step that will formgroove 5, form N by the CVD method^-Type layer 31.Then, form N⁺Type layer 32.For example, N^-Type layer 31 and N⁺Type layer 32 forms on following condition: temperature is 1600 ℃, and the speed of growth is equal to or less than 1.0 for the raw-material introducing rate of 1.0 μ m, gas C and Si per hour.At this moment, for example, nitrogen is incorporated in the atmosphere, thereby N impurity is introduced in N^-Type layer 31 and N⁺In thetype layer 32.

Like this, just form ongroove 5 inwalls that to have doping content for example be 1 * 10¹⁶Cm^-3N^-Type layer 31 and doping content are 1 * 10²⁰Cm^-3N⁺Type layer 32.

In this case, forgroove 5, be formed ongroove 5 bottoms, be formed ongroove 5 sidewalls or be formed at N on the substrate surface^-Type layer 31 and N⁺The thickness and the doping content oftype layer 32 are mutually the same.Particularly, the thickness of a part that is formed at each impurity layer ongroove 5 sidewalls is thinner than the thickness that is formed ongroove 5 bottoms, and the doping content of a part that is formed at each impurity layer ongroove 5 sidewalls is than the height that is formed ongroove 5 bottoms.In addition, be formed at the thickness of a part of each impurity layer ongroove 5 bottoms than being formed at thick on the substrate surface.

Why being designed to above-mentioned relation, is because be difficult to accomplish impurity layer is deposited on above the sidewall ofgroove 5 and be not deposited on the bottom of groove 5.In addition, this is because the deposition of impurity layer ongroove 5 bottoms becomes greater than the deposition on the substrate surface, because be not deposited on the bottom that a part of impurity layer ongroove 5 sidewalls can be deposited ongroove 5.

In this case, the relation between thickness and the doping content just depends on the plane orientation of substrate surface and the plane orientation ofgroove 5 sidewalls.In this embodiment, it is restricted to and has following relation.Figure 10 is the schematic diagram that is used to explain this relation.

For N^-Type layer 31 and N⁺The degree oftype layer 32, as shown in figure 10, the thickness that is formed at the impurity layer ongroove 5 bottoms is defined as d2, and the thickness that is formed at the impurity layer on the substrate surface is defined as d1, and the thickness that is formed at the impurity layer ongroove 5 sidewalls is defined as d3.These thickness just have following relation so:

(formula 1) d2=2 * d1

(formula 2) d2=3 * d3

Here, above-mentioned thickness relationship can change according to sedimentary condition etc.For example,formula 2 shows thatthickness d 2 becomes three times of thickness d 3.In fact,thickness d 2 bethickness d 3 1-5 doubly.Because N^-Type layer 31 and N⁺The speed of growth oftype layer 32 ongroove 5 sidewalls is for example 100nm per hour, and their speeds of growth ongroove 5 bottoms are 100nm-500nm per hour, like this, just obtain above-mentioned relation.

In addition, to N^-Type layer 31 and N⁺The doping content oftype layer 32, the concentration that is formed at the part ongroove 5 sidewalls be formed at the part ongroove 5 bottoms concentration 1-5 doubly.

(step shown in Figure 7)

By carrying out etchback step, remove being formed at a part of N on the substrate surface^-Type layer 31 and N⁺The type layer.Like this, just expose N⁺Type source region 4 is retained in the N in thegroove 5 in addition^-Type layer 31 just constitutes N^-Type channel layer 6.

(step shown in Figure 8)

If necessary, carry out technologies such as sacrificial oxidation.After this, N⁺Type layer 32 is oxidized in thermal oxidation technology, thereby forms theoxidation film 8 that is doped with N type impurity.The concentration that is entrained in the N type impurity in theoxidation film 8 is generally equal to and is included in the N that treats oxidation⁺The concentration of the N type impurity in thetype layer 32.

At this moment, the process time and the technological temperature of control thermal oxidation technology make that part of N that is formed ongroove 5 sidewalls⁺Type layer 32 complete oxidation.Like this, on the sidewall of groove, N^-Type channel layer 6 andoxidation film 8 just remain, and N⁺Type layer 32 disappears.On the bottom ofgroove 5, N not only^-Type channel layer 6 andoxidation film 8, and N⁺Type layer 32 all remains.This N⁺Type layer 32 provides N⁺Typeconductive formation 7.

(step shown in Figure 9)

Be doped with the polysilicon layer of impurity or the surface that metal level is formed at oxidation film 8.Then, polysilicon layer or metal level are eat-back, thereby, a part of polysilicon layer or metal level are kept, be used to embed groove 5.Like this, just producegrid 9.

Though the step of not shown back also in the drawings, but to carry out that interlayer dielectric forms step, the contact hole that is used to contact interlayer dielectric forms step, lead forms step etc.Therefore, be formed for being electrically connected to the gate line on thegrid 9, and be formed for being electrically connected to N⁺First electrode 14 intype source region 4, then, at N⁺Form backplate 19 on the back side of type substrate 1.Like this, just finished vertical power-type MOSFET shown in Figure 1.

Vertical power-type MOSFET according to this embodiment produces as mentioned above, thereby can prevent that the corner's generation electric field betweengroove 5 bottoms and sidewall is concentrated, and has prevented to be positioned at oxide-film 8 fractures of this corner.

In addition, said structure only passes through at N^-Type drift layer and P⁺Boundary vicinity between thetype base 3groove 5 of slotting out just can produce.Like this, just needn't increase the degree of depth of groove 5.In addition, also unnecessary as prior art at P⁺Form N type layer below the type base 3.Therefore, the extra step of unnecessary increase forms N type layer, thereby has simplified the manufacture process of this vertical power-type MOSFET.

(second embodiment)

The second embodiment of the present invention is described below, and Figure 11 A shows the cutaway view as the MOSFET of the manufacturing silicon carbide semiconductor device of this embodiment, and Figure 11 B is the distribution map along the doping content of P conductive-type impurity among the MOSFET of the intercepting of the line XIE-XIF among Figure 11 A.MOSFET according to this embodiment describes with reference to Figure 11 A and Figure 11 B following.Therefore similar among the basic structure of the MOSFET of this embodiment and first embodiment, only describe difference part wherein.

Similar to first embodiment, in second embodiment of the invention, be positioned at the P ongroove 5 both sides⁺Type base 3 is arranged to be positioned on the more downside ofoxidation film 8 extreme lower positions.P⁺The impurity concentration of p type impurity is from corresponding to N in thetype base 3⁺The height and position of typeconductive formation 7 bottoms is to N^-Type drift layer 2 and P⁺The boundary that the type base is 3 reduces gradually, shown in Figure 11 A and 11B.In addition, N^-The impurity concentration of N type impurity is lower than N in thetype channel layer 6⁺The impurity concentration of N type impurity in the typeconductive formation 7, and be higher than N^-The impurity concentration of N type impurity in thetype drift layer 2.

Like this, said structure just can improve withstand voltage and keep the threshold value of grid groove among the MOSFET of first embodiment.

(the 3rd embodiment)

The third embodiment of the present invention is described below, and Figure 12 A is the cutaway view as the MOSFET of manufacturing silicon carbide semiconductor device according to this embodiment.Figure 12 B is the distribution map along the doping content of P conductive-type impurity among the MOSFET of Figure 12 A center line XIIG-XIIH intercepting.Figure 12 C is the distribution map along the doping content of N conductive-type impurity among the MOSFET of Figure 12 A center line XIII-XIIJ intercepting.The MOSFET of this embodiment is described below with reference to Figure 12 A-12C.Therefore similar according among the MOSFET of this embodiment and first embodiment, only describe its difference.

Different with first embodiment is that in the third embodiment of the present invention, its structure does not comprise N⁺Type conductive formation 7.Similar to first embodiment is to be positioned at the P ongroove 5 both sides⁺Type base 3 is arranged to be positioned on the more downside ofoxidation film 8 extreme lower positions.From withgroove 5 the corresponding height and position ofoxidation film 8 bottommosts to N^-Type drift layer 2 and P⁺The boundary that the type base is 3, P⁺The impurity concentration of the p type impurity in thetype base 3 reduces gradually.In addition, N^-The impurity concentration of the N type impurity in thetype channel layer 6 is greater than N^-The impurity concentration of N type impurity in thetype drift layer 2.

Like this, though because this structure does not comprise N⁺Typeconductive formation 7 and make conducting resistance become higher, but that said structure can improve is withstand voltage, and keep threshold value according to grid groove among the MOSFET of first embodiment.

(the 4th embodiment)

The fourth embodiment of the present invention is described below, and Figure 13 is the cutaway view as the insulated gate bipolar transistor IGBT of manufacturing silicon carbide semiconductor device according to this embodiment.

In first embodiment, manufacturing silicon carbide semiconductor device is to have the N that is made by carborundum⁺The vertical power-type MOSFET of type substrate 1.On the other hand, as shown in figure 13, this device comprises P⁺Type substrate 61 replaces substrate 1.Like this, this device is IGBT rather than power-type MOSFET just.Herein, in this case, at the N described in first embodiment⁺Type source region 4 is just as N⁺Type emitter region,first electrode 14 are as emission electrode, andsecond electrode 19 is as passive electrode.

Under situation with this IGBT, similar to first embodiment, be positioned at the P ongroove 5 both sides⁺The position oftype base 3 is lower than the extreme lower position ofoxidation film 8, has N thereby form^-The junction structure oftype channel layer 6, this N^-Type channel layer 6 is clipped in two P from the both sides of thischannel layer 6⁺Between the type base 3.Like this, drain potentials is just interrupted by this junction structure, thereby prevents that depletion layer from running through N^-The top oftype channel layer 6.

Like this, just prevent that the corner's generation electric field betweengroove 5 bottoms and sidewall from concentrating, thereby preventoxidation film 8 fractures in this corner.Like this, the 4th embodiment just has the effect identical with first embodiment.

(the 5th embodiment)

The fifth embodiment of the present invention is described below, and Figure 14 is the cutaway view as the IGBT of manufacturing silicon carbide semiconductor device according to present embodiment.The IBGT of present embodiment is described with reference to Figure 14.Basic structure according to the IBGT of this embodiment is similar to the 4th embodiment, therefore, only describes difference part therebetween.

As shown in figure 14, in the IBGT according to this embodiment, the substrate of being made bycarborundum 1 is N⁺Conductivity type.A plurality of groove 40 is from N⁺The back side oftype substrate 1 forms in vertical direction, thereby groove arrives N^-Type drift layer 2.P⁺Type layer 41 is embedded in each groove 40, and said structure is different with the 4th embodiment's.

Each P⁺Type layer 41, promptly the distance of each groove 41 and width are for example about 100 μ m.This P⁺The degree of depth of type 41 is for example 60-300 μ m.

A kind of like this structure below this structure is equal to, wherein, by a plurality of P⁺The collecting region that type layer 41 is formed comprises a plurality of N⁺The type zone.Therefore, basically, this P⁺Type layer 41 is as collecting region, thereby IGBT is operated.Because collecting region comprises a plurality of N⁺The type zone is at SiC PN junction place, promptly at P⁺Type layer 41 and N^-The threshold voltage that produces in the PN electromotive force between thetype drift layer 2 can be eliminated.Herein, under the situation that adopts 4H-SIC, this threshold voltage is 2.9eV.

IGBT with said structure can make like this, that is, and and a plurality of P⁺Type layer 41 is formed at the N shown in Figure 4 of first embodiment⁺Fig. 5-manufacturing step shown in Figure 9 then, is carried out in the back side of type substrate 1.Particularly, the mask with a plurality of openings is positioned at this N⁺The back side oftype substrate 1, described opening is corresponding to a plurality of grooves to be formed position.Then, to N⁺Etching is carried out at the back side oftype substrate 1, thereby forms a plurality of grooves 41.Remove mask afterwards, then, with P⁺The type film is deposited on this N⁺The back side of type substrate 1.To this P⁺The type film eat-backs, thereby forms P⁺Type layer 41.

(the 6th embodiment)

The sixth embodiment of the present invention is described below, and Figure 15 is the cutaway view as the IGBT of manufacturing silicon carbide semiconductor device according to this embodiment, describes the IGBT of this embodiment below with reference to Figure 15.Basic structure according to the IGBT of this embodiment is similar to the 5th embodiment, therefore, only describes its difference part.

IGBT according to this embodiment comprises P⁺Conductive silicon carbide substrate 1.A plurality ofgrooves 50 are formed at P in vertical direction⁺The back side of type substrate 1.Groove 50 arrives N^-Type drift layer 2.N⁺Type layer 51 embeds in each groove 50.Said structure is different with the 3rd embodiment's.

Each N⁺Type layer 51, i.e. eachgroove 51, distance and width be for example about 100 μ m.This N⁺The degree of depth oftype layer 51 is for example 60-300 μ m.

This structural equivalents is in following a kind of structure, wherein, and by a plurality of P⁺The collecting region that typesubstrate 1 is formed comprises a plurality of N⁺Type district 51.Therefore, basically, P⁺Type substrate 61 is as collecting region, thereby IGBT is operated.Because collecting region comprises a plurality of N⁺Type zone 51, at SiC PN junction place, that is, and P⁺Type substrate 1 and N^-The threshold voltage that produces in the PN electromotive force between thetype drift layer 2 can be eliminated.

IGBT with said structure can easily manufacture and make P⁺Different among conductive silicon carbide substrate and the 5th embodiment, and N⁺Type layer 51 is embedded into and is formed at P⁺In thegroove 50 attype substrate 1 back side.

(modification)

In each embodiment, first conductivity type is the N type, and second conductivity type is the P type.In addition, though described as example and to have had vertical power-type MOSFET of the N channel-type that is used to form N type raceway groove and IGBT, but, first conductivity type also can be the P type, second conductivity type also can be the N type, has vertical power-type MOSFET of the P channel-type that is used to form P type raceway groove and IGBT thereby produce.

In each embodiment, substrate comprises the P that forms by epitaxial growth method⁺Type base 3 and N⁺Type source region 4, but they also can form by ion implantation.

Herein, in expression during crystal orientation, usually, stripe shape symbol (that is,-) should be added to the numeral that will add above.But the restriction in the statement that brings because of the electronics submission system, in this specification, the stripe shape symbol has been added in before the numeral that will be added.

Though the present invention is described with reference to preferred embodiments, should be appreciated that the present invention is not limited to these preferred embodiments and structure, this invention is intended to contain various modifications and equivalent structure.In addition, though preferred various combinations and configuration,, other combinations and configuration (comprise more, still less or only the structure of a separate part arranged) all are positioned within the spirit and scope of the present invention.

Claims (16)

1. manufacturing silicon carbide semiconductor device comprises:

Semiconductor chip, it comprises first conductivity type or the second conductive silicon carbide substrate (1,61), make and impurity concentration is lower than silicon carbide substrate (1 by first conductive silicon carbide, 61) first semiconductor layer (2), second semiconductor layer of making by second conductive silicon carbide (3), by the 3rd semiconductor layer (4) that first conductive silicon carbide is made, they are storehouse in this order;

Groove (5), it is arranged in the unit area of semiconductor chip, and runs through the second and the 3rd semiconductor layer (3,4), arrives first semiconductor layer (2);

Channel layer (6), it is first conductivity type, and is positioned on the sidewall and bottom of groove (5);

Oxidation film (8), it is arranged on the channel layer (6) of groove (5), and comprises the part as oxidation film of grid;

Grid (9), it is arranged on the surface of oxidation film (8) of groove (5);

First electrode (14), it is electrically connected to the 3rd semiconductor layer (4); And

Second electrode (19), it is electrically connected to silicon carbide substrate (1,61), wherein

Boundary position between first semiconductor layer (2) and second semiconductor layer (3) is lower than the extreme lower position of oxidation film (8) in the groove (5).

2. manufacturing silicon carbide semiconductor device according to claim 1 is characterized in that:

To the boundary first semiconductor layer (2) and second semiconductor layer (3), the impurity concentration of second conductive-type impurity reduces gradually in second semiconductor layer (3) from the height and position of the oxidation film (8) that is positioned at groove (5) bottom, and

The impurity concentration of first conductive-type impurity is higher than the impurity concentration of first conductive-type impurity in first semiconductor layer (2) in the channel layer (6).

3. manufacturing silicon carbide semiconductor device according to claim 1 is characterized in that, also comprises:

Conductive formation (7), it is first conductivity type, and is positioned at below the oxidation film (8) on groove (5) bottom, wherein

The length of bottom is corresponding to the summation of the thickness of the thickness of conductive formation (7) and channel layer (6) from the extreme lower position of oxidation film (8) to groove (5).

4. manufacturing silicon carbide semiconductor device according to claim 3 is characterized in that:

To the boundary first semiconductor layer (2) and second semiconductor layer (3), the impurity concentration of second conductive-type impurity reduces gradually in second semiconductor layer (3) from the height and position bottom conductive formation (7), and

The impurity concentration of first conductive-type impurity is lower than the impurity concentration of first conductive-type impurity in the conductive formation (7) in the channel layer (6), and is higher than the impurity concentration of first conductive-type impurity in first semiconductor layer (2).

5. according to each described manufacturing silicon carbide semiconductor device among the claim 1-4, it is characterized in that:

The plane orientation of groove (5) sidewall is (1-100) (i.e. (1100)) surfaces or (11-20) (i.e. (1120)) surface, and

The thickness that is positioned at a part of channel layer (6) on groove (5) bottom is greater than that part of thickness that is positioned on groove (5) sidewall.

6. manufacturing silicon carbide semiconductor device according to claim 5 is characterized in that:

The thickness that is positioned at that part of channel layer (6) on groove (5) bottom is 1-5 times that is formed on groove (5) sidewall.

7. manufacturing silicon carbide semiconductor device according to claim 5 is characterized in that:

The doping content that is arranged in that part of channel layer (6) first conductive-type impurities on groove (5) sidewall is 5 times that are positioned on groove (5) bottom.

8. according to each described manufacturing silicon carbide semiconductor device among the claim 1-4, it is characterized in that:

Described silicon carbide substrate (1) is first conductivity type,

A plurality of second grooves (40) are arranged in this silicon carbide substrate (1), and each second groove (40) is provided with to first semiconductor layer (2) from the back side of silicon carbide substrate (1),

Second groove (40) is embedded with the second conductive-type impurity layer (41), and

Second electrode (19) contact silicon carbide substrate (1) and impurity layer (41).

9. according to each described manufacturing silicon carbide semiconductor device among the claim 1-4, it is characterized in that:

Described silicon carbide substrate (61) is second conductivity type,

A plurality of second grooves (50) are arranged in this substrate (61), and each second groove (50) is provided with from silicon carbide substrate (61) back side to first semiconductor layer (2),

Second groove (50) is embedded with the first conductive-type impurity layer, and

Second electrode (19) contact silicon carbide substrate (61) and impurity layer (51).

10. method of making manufacturing silicon carbide semiconductor device said method comprising the steps of:

Prepare a semiconductor chip, it comprises first conductivity type or the second conductive silicon carbide substrate (1,61), make and its impurity concentration is lower than silicon carbide substrate (1 by first conductive silicon carbide, first semiconductor layer (2) of impurity concentration 61), second semiconductor layer of making by second conductive silicon carbide (3) and the 3rd semiconductor layer of making by first conductive silicon carbide (4), they are storehouse in this order;

Form groove (5) in the unit area of semiconductor chip, this groove (5) runs through the second and the 3rd semiconductor layer (3,4) and arrives first semiconductor layer (2);

In groove (5), form first conductivity type the 4th semiconductor layer (31) by epitaxial growth method, thereby make that part of the 4th semiconductor layer (31) that is positioned on groove (5) bottom be thicker than the part that is positioned on groove (5) sidewall;

Form oxidation film (8) by thermal oxidation method on the inwall of groove (5), thereby make this oxidation film (8) comprise a part that is used for oxidation film of grid, it contacts with the 4th semiconductor layer (31), thereby the 4th semiconductor layer (31) produces channel layer (6);

In groove (5), form grid (9) on the surface of oxidation film (8);

Be formed for being electrically connected first electrode (14) of the 3rd semiconductor layer (4); And

Be formed for being electrically connected to second electrode (19) of silicon carbide substrate (1,61), wherein

In the step that forms oxidation film (8), thermal oxidation process is carried out like this, that is, make the boundary position of the semiconductor layer of winning (2) and second semiconductor layer (3) be lower than the extreme lower position of the middle oxidation film (8) of groove (5).

11. the method for manufacturing manufacturing silicon carbide semiconductor device according to claim 10 is characterized in that, also comprises:

The 4th semiconductor layer (31) on groove (5) sidewall and bottom is gone up and is formed the 5th semiconductor layer (32), and the doping content of first conductive-type impurity of the 5th semiconductor layer (32) is higher than the 4th semiconductor layer (31), wherein

In the step that forms oxidation film (8), carry out thermal oxidation process, up to being formed at a part the 5th semiconductor layer (32) on groove (5) sidewall by complete oxidation, thereby form oxidation film (8), and thereby the first conductivity type conductive formation (7) is formed at below the oxidation film (8) on groove (5) bottom, keeps the 5th semiconductor layer (32) not oxidized simultaneously.

12. the method for manufacturing manufacturing silicon carbide semiconductor device according to claim 10 is characterized in that:

In the step that forms groove (5), the plane orientation of groove (5) sidewall is set as surperficial or (11-20) (i.e. (11 20)) surface, (1-100) (i.e. (1 100)).

13. the method for manufacturing manufacturing silicon carbide semiconductor device according to claim 11 is characterized in that:

In the step that forms the 4th semiconductor layer (31), the thickness that is formed at that part of the 4th semiconductor layer (31) on groove (5) bottom is made as that part of 1-5 times that is formed on groove (5) sidewall.

14. the method for manufacturing manufacturing silicon carbide semiconductor device according to claim 11 is characterized in that:

In the step that forms the 4th semiconductor layer (31), the doping content that is formed at first conductive-type impurity in that part of the 4th semiconductor layer (31) on groove (5) sidewall is made as that part of 1-5 times that is formed on groove (5) bottom.

15. the method according to each described manufacturing manufacturing silicon carbide semiconductor device among the claim 10-14 is characterized in that:

At silicon carbide substrate (1) is under the situation of first conductivity type, and the step of preparing semiconductor chip may further comprise the steps:

Form a plurality of second grooves (40) at the back side of this substrate (1), each second groove (40) arrives first semiconductor layer (2); And

Second groove (40) is packed with the second conductive-type impurity layer (41).

16. the method according to each described manufacturing manufacturing silicon carbide semiconductor device among the claim 10-14 is characterized in that:

At silicon carbide substrate (61) is under the situation of second conductivity type, and the step of preparing semiconductor chip may further comprise the steps:

Form a plurality of second grooves (50) at the back side of substrate (61), each second groove (50) arrives first semiconductor layer (2); And

Second groove (50) is packed with the first conductive-type impurity layer (51).

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