CN1722810A

Movatterモバイル変換

Info

Publication number: CN1722810A
Application number: CN 200510082734
Authority: CN
Inventors: 李茂堂
Original assignee: China Institute of Water Resources and Hydropower Research
Current assignee: China Institute of Water Resources and Hydropower Research
Priority date: 2005-07-11
Filing date: 2005-07-11
Publication date: 2006-01-18
Anticipated expiration: 2025-07-11
Also published as: CN100361523C

Abstract

一种数字相机实时采集系统，属于电子技术中的数据传输与处理技术领域。为了克服现有的图像采集卡分辨率较低、传输速率较低的缺点，本发明提供了一种数字相机实时采集系统，包括数字相机、PCI图像采集卡和计算机。其核心部分PCI图像采集卡采用高速PCI接口芯片，结合高速缓存和CPLD逻辑控制芯片，实现了数字相机与PCI总线间的高速数据实时传输，很好地解决了计算机从外部设备进行高速、大数据量采集的难题。本发明具有采集速率高、实时性能好，操作简单、使用方便，工作稳定、可靠，可扩展性强等优点。

A digital camera real-time acquisition system belongs to the technical field of data transmission and processing in electronic technology. In order to overcome the disadvantages of low resolution and low transmission rate of existing image acquisition cards, the invention provides a digital camera real-time acquisition system, which includes a digital camera, a PCI image acquisition card and a computer. Its core PCI image acquisition card adopts high-speed PCI interface chip, combined with high-speed cache and CPLD logic control chip, realizes high-speed data real-time transmission between digital camera and PCI bus, and solves the problem of high-speed, large-scale data transfer from external devices to computers. problem of mass collection. The invention has the advantages of high acquisition rate, good real-time performance, simple operation, convenient use, stable and reliable work, strong expandability and the like.

Description

Translated fromChinese

一种数字相机实时采集系统A digital camera real-time acquisition system

技术领域technical field

本发明属于数据传输与处理技术领域，尤其涉及数字相机中图像数据的实时采集系统。The invention belongs to the technical field of data transmission and processing, in particular to a real-time collection system of image data in a digital camera.

背景技术Background technique

随着各种新型数字相机的不断出现，数字相机越来越多地成为实时数据采集、图形图像处理、遥感监测、自动检测等系统中的探测器，广泛应用于民用、商业、工业、医疗、科研等诸多领域。但与此同时，数字相机的海量数据输出也对数据采集系统的采集速度提出了更高的要求。With the continuous emergence of various new digital cameras, digital cameras have increasingly become detectors in systems such as real-time data acquisition, image processing, remote sensing monitoring, and automatic detection, and are widely used in civil, commercial, industrial, medical, scientific research and many other fields. But at the same time, the massive data output of the digital camera also puts forward higher requirements on the acquisition speed of the data acquisition system.

目前，市场上的图像采集卡大多只能用于一些低速场合，对低分辨率相机进行图像采集，而且实时性差，在图像帧率及分辨率要求比较高的场合下，无法获得令人满意的效果。因此急需设计一种高效的数字相机实时采集系统，实现对高精度相机数据的高速采集和传输，满足现代工业生产、生活以及科学研究中日益增长的高速、高精度的数据采集要求。At present, most of the image acquisition cards on the market can only be used in some low-speed occasions to collect images from low-resolution cameras, and the real-time performance is poor. In the occasions where the image frame rate and resolution requirements are relatively high, satisfactory results cannot be obtained. Effect. Therefore, it is urgent to design an efficient digital camera real-time acquisition system to realize high-speed acquisition and transmission of high-precision camera data, and to meet the increasing high-speed and high-precision data acquisition requirements in modern industrial production, life and scientific research.

发明内容Contents of the invention

为了克服现有的图像采集卡分辨率较低、传输速率较低的缺点，本发明提供了一种数字相机实时采集系统，它可以实现对高分辨率(1024×768)、高帧率(30fps)的数字图像的实时采集、显示和存储，速率可以达到480Mbps。In order to overcome the disadvantages of low resolution and low transmission rate of existing image acquisition cards, the invention provides a real-time acquisition system for digital cameras, which can realize high resolution (1024*768), high frame rate (30fps ) real-time collection, display and storage of digital images, the rate can reach 480Mbps.

本发明提供的数字相机实时采集系统，包括计算机、插在所述计算机PCI插槽上的PCI图像采集卡，以及通过数据总线与所述PCI图像采集卡连接的数字相机：The digital camera real-time acquisition system provided by the present invention includes a computer, a PCI image acquisition card inserted in the PCI slot of the computer, and a digital camera connected to the PCI image acquisition card by a data bus:

所述PCI图像采集卡实现了数字相机到计算机的高速数据采集和传输，具体包括CPLD逻辑控制芯片、高速缓存、PCI接口芯片及其配置E²PROM；The PCI image acquisition card realizes the high-speed data acquisition and transmission from the digital camera to the computer, and specifically includes a CPLD logic control chip, a cache memory, a PCI interface chip and configuration E² PROM thereof;

所述数字相机通过数据总线和控制线与CPLD逻辑控制芯片相连；所述CPLD逻辑控制芯片分别与所述高速缓存和PCI接口芯片相连；所述配置E²PROM与PCI接口芯片相连；所述PCI接口芯片通过PCI总线与计算机相连接；Described digital camera links to each other with CPLD logic control chip by data bus and control line; Described CPLD logic control chip links to each other with described cache memory and PCI interface chip respectively; Described configuration E² PROM links to each other with PCI interface chip; Described PCI The interface chip is connected to the computer through the PCI bus;

所述CPLD逻辑控制芯片通过控制线实现计算机对数字相机的同步控制，由CPLD逻辑控制芯片输出一个宽度由计算机给出的触发信号来触发数字相机开始积分、采集并输出图像数据；The CPLD logic control chip realizes the synchronous control of the computer to the digital camera through the control line, and the CPLD logic control chip outputs a trigger signal whose width is given by the computer to trigger the digital camera to start integrating, collecting and outputting image data;

所述CPLD逻辑控制芯片对数字相机采集到的图像数据首先进行整合处理，将数据变换成为32bit数据格式并实时存储在所述高速缓存中，然后等待高速缓存半满时，将存储在所述高速缓存中的数据实时读出到PCI接口芯片，经由PCI总线送入计算机；The CPLD logic control chip first integrates the image data collected by the digital camera, converts the data into a 32bit data format and stores it in the high-speed cache in real time, and then waits for the cache to be half full, then stores it in the high-speed cache. The data in the cache is read out to the PCI interface chip in real time, and sent to the computer via the PCI bus;

所述CPLD逻辑控制芯片控制高速缓存在每帧数据的开头置高速缓存复位，同时设置“可编程快满”偏移量和“可编程快空”偏移量，然后等待数字相机发来的行同步信号由低变高，开始保存一行有效数据，从而保证高速缓存中数据始终是从一帧图像的帧头开始，不会造成图像错位，并保证高速缓存不会因溢出而造成象素数据丢失；The CPLD logic control chip controls the cache to reset the cache at the beginning of each frame of data, set the "programmable almost full" offset and the "programmable fast empty" offset at the same time, and then wait for the row sent by the digital camera The synchronization signal changes from low to high, and starts to save a line of valid data, so as to ensure that the data in the cache always starts from the frame header of a frame of image, which will not cause image misalignment, and ensure that the cache will not cause pixel data loss due to overflow ;

所述CPLD逻辑控制芯片通过读取高速缓存的状态到计算机，来确定对所述高速缓存进行相应的读出或写入操作。The CPLD logic control chip determines to perform a corresponding read or write operation on the cache by reading the state of the cache to the computer.

在本发明中，所述数字相机输出的若是LVDS格式的数据，则所述PCI图像采集卡还设有驱动转换接口，将所述数字相机输出的LVDS格式的数据转换成TTL格式的数据后再输出给CPLD逻辑控制芯片进行处理。In the present invention, if the output of the digital camera is data in the LVDS format, the PCI image acquisition card is also provided with a drive conversion interface, and the data in the LVDS format output by the digital camera is converted into data in the TTL format. Output to the CPLD logic control chip for processing.

在本发明中，所述高速缓存采用高速同步先进先出缓存器(FIFO)，以保证数据的高速存取。In the present invention, the high-speed cache adopts a high-speed synchronous first-in-first-out buffer (FIFO) to ensure high-speed access of data.

在本发明中，所述计算机用来控制CPLD逻辑控制芯片对数字相机进行单帧图像捕获、将单帧图像数据实时显示在计算机显示器上、将单帧图像数据实时保存到计算机硬盘中、对所述数字相机进行连续时间的图像采集、在计算机显示器上实时显示连续图像数据、将连续图像数据实时保存到计算机硬盘中、实时读取所述高速缓存的状态、实时置高速缓存复位。In the present invention, the computer is used to control the CPLD logic control chip to capture a single-frame image of the digital camera, display the single-frame image data on the computer monitor in real time, save the single-frame image data to the hard disk of the computer in real time, The digital camera performs continuous image acquisition, displays continuous image data on a computer monitor in real time, saves continuous image data to a computer hard disk in real time, reads the state of the cache in real time, and resets the cache in real time.

本发明解决了目前图像采集卡对于数字相机的海量数据输出无法实现实时采集与传输的难题，系统具有以下特点：采集速率高、实时性能好；操作简单、使用方便；工作稳定、可靠。而且，系统具有广泛的应用前景，只需稍作改动即可用于其它信号的采集处理。The invention solves the problem that the current image acquisition card cannot realize real-time acquisition and transmission for massive data output of digital cameras, and the system has the following characteristics: high acquisition rate, good real-time performance; simple operation, convenient use; stable and reliable work. Moreover, the system has wide application prospects, and can be used for acquisition and processing of other signals only with a slight modification.

附图说明Description of drawings

图1是数字相机实时采集系统的第一个实施例的系统结构图，其中各数字标识说明如下： 1-数字相机 2-数据总线 3-控制线 4-PCI图像采集卡 5-CPLD逻辑控制芯片 6-高速缓存 7-PCI接口芯片 8-配置E²PROM 9-PCI总线 10-计算机Fig. 1 is the system structural diagram of the first embodiment of digital camera real-time acquisition system, wherein each digital mark is described as follows: 1- Digital camera 2- Data bus 3- Control line 4-PCI image acquisition card 5-CPLD logic control chip 6- Cache 7-PCI interface chip 8- Configure E² PROM 9-PCI bus 10 - computer

图2是数字相机实时采集系统的第二个实施例的系统结构图，其中各数字标识说明如下：Fig. 2 is the system structural diagram of the second embodiment of digital camera real-time acquisition system, wherein each digital identification is described as follows:

1-数字相机 1-digital camera 2-数据总线 2-Data bus 3-控制线 3- Control line 4-PCI图像采集卡 4-PCI image acquisition card 5-CPLD逻辑控制芯片 5-CPLD logic control chip 6-高速异步FIFO 6-High-speed asynchronous FIFO 7-PCI接口芯片 7-PCI interface chip 8-配置E²PROM8- Configure E² PROM 9-PCI总线 9-PCI bus 10-计算机 10-Computer 11-驱动转换接口 11-drive conversion interface

图3是计算机中的软件程序流程图。Figure 3 is a flow chart of the software program in the computer.

图4是数字相机实时采集系统的工作流程图。Fig. 4 is the working flowchart of the digital camera real-time acquisition system.

具体实施方式Detailed ways

下面结合附图和实施例来进一步说明本发明。The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

图1显示了本发明所述的数字相机实时采集系统的第一个实施例，此实施例是为一般的输出为TTL格式数据的数字相机而设计的，包括：数字相机1、数据总线2、控制线3、PCI图像采集卡4、PCI总线9、计算机10。其中，PCI图像采集卡4是一块集成了多种芯片和接口的印刷电路板卡，它由CPLD逻辑控制芯片(简称CPLD)5、高速缓存6、PCI接口芯片7和配置E²PROM8共同组成。Fig. 1 has shown the first embodiment of the digital camera real-time acquisition system of the present invention, and this embodiment is designed for the digital camera that general output is TTL format data, comprises:digital camera 1,data bus 2,Control line 3, PCIimage acquisition card 4,PCI bus 9,computer 10. Among them, PCIimage acquisition card 4 is a printed circuit board integrated with various chips and interfaces, and it is composed of CPLD logic control chip (CPLD for short) 5,cache memory 6,PCI interface chip 7 and configuration E² PROM 8.

PCI图像采集卡4直接插在计算机10的PCI插槽上；数字相机1与PCI图像采集卡4由数据总线2和控制线3连接：数字相机1通过数据总线2将拍摄到的图像数据送给PCI图像采集卡4，PCI图像采集卡4通过控制线3发送触发脉冲给数字相机1，控制数字相机1开始积分采集数据；PCI图像采集卡4在CPLD逻辑控制芯片5的控制下实时采集、整理相机数据并送给计算机10；计算机10通过设备驱动程序实现与PCI图像采集卡4的软件接口，通过应用程序实现实时显示、实时存盘等操作。The PCIimage acquisition card 4 is directly inserted on the PCI slot of thecomputer 10; thedigital camera 1 is connected with the PCIimage acquisition card 4 by thedata bus 2 and the control line 3: thedigital camera 1 sends the image data captured by thedata bus 2 to PCIimage acquisition card 4, PCIimage acquisition card 4 sends trigger pulse todigital camera 1 throughcontrol line 3, controlsdigital camera 1 to start integrating and collecting data; PCIimage acquisition card 4 collects and arranges in real time under the control of CPLDlogic control chip 5 The camera data is also sent to thecomputer 10; thecomputer 10 realizes the software interface with the PCIimage acquisition card 4 through the device driver, and realizes operations such as real-time display and real-time storage through the application program.

PCI图像采集卡4内部各芯片连接关系如下：数字相机1通过数据总线2与CPLD 5相连；CPLD5与高速缓存6相连，也与PCI接口芯片7相连；高速缓存6与PCI接口芯片7相连接；配置E²PROM8与PCI接口芯片7相连；最后，PCI接口芯片7通过PCI总线9与计算机10相连接。The connection relationship of each chip in the PCIimage acquisition card 4 is as follows: thedigital camera 1 is connected with theCPLD 5 through thedata bus 2; the CPLD5 is connected with thecache memory 6, and is also connected with thePCI interface chip 7; thecache memory 6 is connected with thePCI interface chip 7; The configuration E² PROM 8 is connected with thePCI interface chip 7 ; finally, thePCI interface chip 7 is connected with thecomputer 10 through thePCI bus 9 .

在第一个实施例中，数字相机1采用输出为TTL格式的普通数字相机，数字相机1输出的数据可以直接送入CPLD 5处理。In the first embodiment, thedigital camera 1 adopts an ordinary digital camera whose output is in TTL format, and the data output by thedigital camera 1 can be directly sent to theCPLD 5 for processing.

图2显示了本发明所述的数字相机实时采集系统的第二个实施例，此实施例是为输出为LVDS(全称：Low Voltage Differential Signal)格式数据的数字相机而设计的，其组成部件与第一个实施例基本相同，只是在第一个实施例的基础上，PCI图像采集卡4中还增加了驱动转换接口11。Fig. 2 has shown the second embodiment of the digital camera real-time acquisition system of the present invention, and this embodiment is designed for the digital camera outputting as LVDS (full name: Low Voltage Differential Signal) format data, and its constituent parts and The first embodiment is basically the same, except that on the basis of the first embodiment, adrive conversion interface 11 is added to the PCIimage acquisition card 4 .

在第二个实施例中数字相机1输出的是LVDS格式的数据，因此PCI图像采集卡4中设有驱动转换接口11，如采用LVDS接口转换芯片DS90C32，将数字相机1输出的LVDS数据转换成适合CPLD 5处理的TTL信号后，再送到CPLD 5进行处理。In the second embodiment, whatdigital camera 1 outputs is the data of LVDS format, so PCIimage acquisition card 4 is provided withdrive conversion interface 11, as adopting LVDS interface conversion chip DS90C32, the LVDS data thatdigital camera 1 outputs is converted into After the TTL signal suitable forCPLD 5 processing, it is sent toCPLD 5 for processing.

PCI图像采集卡4是整个数字相机实时采集系统中的核心部分，它的功能是实现数字相机1与计算机10之间的数据的高速采集和传输。PCI图像采集卡4直接插在计算机10的PCI插槽上，由计算机10通过PCI总线9为其供电。其各部分的具体实施如下：The PCIimage acquisition card 4 is the core part of the whole digital camera real-time acquisition system, and its function is to realize high-speed acquisition and transmission of data between thedigital camera 1 and thecomputer 10 . The PCIimage acquisition card 4 is directly inserted on the PCI slot of thecomputer 10, and is powered by thecomputer 10 through thePCI bus 9. The specific implementation of each part is as follows:

PCI接口芯片7与PCI总线9的信号一一对应，它们之间的接口只需将对应信号相连即PCI图像采集卡4直接插在计算机10的PCI插槽上即可，因此，设计时主要考虑PCI接口芯片局部总线的工作方式，在上述两个实施例中，PCI接口芯片均选用了通用的PCI接口芯片-PCI9054。在实施例中，PCI9054的工作时钟为33MHz，其局部总线采用数据和地址非复用的C模式，总线宽度为32位，从本地地址空间映射到PCI存储器空间的空间大小为4MB；PCI9054采用直接存储访问(DMA)工作方式，既是PCI总线的主控制器，又是局部总线的主控制器，利用其主控功能，通过DMA突发传输模式将数字相机数据传送到计算机中。PCI9054与局部总线通过地址线、数据线、控制信号线连接。这部分属于PCI图像采集卡内部电路，已经在印刷电路板上连接好。ThePCI interface chip 7 corresponds to the signals of thePCI bus 9 one by one, and the interface between them only needs to be connected with the corresponding signals, that is, the PCIimage acquisition card 4 is directly inserted on the PCI slot of thecomputer 10. Therefore, when designing, the main consideration As for the working mode of the local bus of the PCI interface chip, in the above two embodiments, the PCI interface chip all selects the general PCI interface chip-PCI9054. In an embodiment, the operating clock of PCI9054 is 33MHz, and its local bus adopts the C mode of data and address non-multiplexing, and the bus width is 32 bits, and the space size mapped to PCI memory space from the local address space is 4MB; PCI9054 adopts direct Memory access (DMA) working mode is not only the main controller of PCI bus, but also the main controller of local bus. Using its main control function, the digital camera data is transmitted to the computer through DMA burst transfer mode. PCI9054 is connected with local bus through address line, data line and control signal line. This part belongs to the internal circuit of the PCI image acquisition card and has been connected on the printed circuit board.

两个实施例均采用IDT公司生产的高速同步FIFO IDT72V251作为高速缓存(简称FIFO)，由于IDT72V251输入/输出端口宽度只有9bit，而PCI总线宽度为32bit，为此，实施例中采用4个IDT72V251，每个IDT72V251使用其8个输入/输出端口，并行构成32bit的外部FIFO，与PCI9054的32位数据总线进行通信。该FIFO具有标准的“满”标志位(FF)、“空”标志位(EF)，可禁止数据继续写入或读出；同时，还有“可编程的快满”标志(PAF)以及“可编程的快空”标志(PAE)，系统根据这些标志位来控制对FIFO的读写操作。在WEN有效时，在WCLK的每一个上升沿，FIFO会把输入数据线上的数据存入内部存储器。同样，在REN有效，并且输出允许OE有效时，在RCLK的每一个上升沿，FIFO会把内部存储器中的数据输出到输出数据线上。Two embodiments all adopt the high-speed synchronous FIFO IDT72V251 that IDT Company produces as high-speed cache (referred to as FIFO), because IDT72V251 input/output port width has only 9bit, and PCI bus width is 32bit, for this reason, adopt 4 IDT72V251 in the embodiment, Each IDT72V251 uses its 8 input/output ports to form a 32-bit external FIFO in parallel to communicate with the 32-bit data bus of PCI9054. The FIFO has a standard "full" flag (FF) and an "empty" flag (EF), which can prohibit data from being written or read; at the same time, there are also "programmable almost full" flags (PAF) and " Programmable "fast empty" flag (PAE), the system controls the read and write operations to FIFO according to these flag bits. When WEN is valid, at each rising edge of WCLK, FIFO will store the data on the input data line into the internal memory. Similarly, when REN is valid and the output allows OE to be valid, at each rising edge of RCLK, the FIFO will output the data in the internal memory to the output data line.

CPLD 5是整个PCI图像采集卡的核心，它实现了对数字相机1的控制、对高速缓存6的控制、对PCI接口芯片7的应答以及这三者之间的逻辑协调工作。两个实施例均采用ALTERA公司的EPM7192作为逻辑控制芯片，其内部逻辑控制功能采用硬件编程语言Verilog来编程实现，利用ALTERA公司的MaxPlusII软件进行逻辑设计、调试和仿真。CPLD 5 is the core of the entire PCI image acquisition card, which realizes the control of thedigital camera 1, the control of thecache 6, the response to thePCI interface chip 7 and the logical coordination between the three. Both embodiments use ALTERA's EPM7192 as a logic control chip, and its internal logic control function is programmed and implemented using the hardware programming language Verilog, and uses ALTERA's MaxPlusII software for logic design, debugging and simulation.

配置E²PROM8是PCI接口芯片7的配置芯片，选用美国国家半导体公司的串行E²PROM 93C56，用于在系统加电时配置PCI9054，主要配置了厂家标识、设备标识以及本地总线的基地址空间、I/O空间、中断控制信号等等信息。配置信息预先烧入E²PROM中，上电后PCI9054将依次读取E²PROM的内容来初始化内部寄存器。Configuration E² PROM8 is the configuration chip ofPCI interface chip 7. The serial E² PROM 93C56 of National Semiconductor Corporation is used to configure PCI9054 when the system is powered on. It mainly configures the manufacturer identification, device identification and the base address of the local bus Space, I/O space, interrupt control signal and other information. The configuration information is burned into E² PROM in advance, and PCI9054 will read the contents of E² PROM in turn to initialize the internal registers after power on.

PCI总线9是计算机中央处理器与高速外围设备之间互连的纽带，它支持高数据传输率，可以在33M主频、32位数据总线的条件下达到峰值132MB/s的带宽，且可扩展为64位，是当今PC领域中的主流总线。PCI bus 9 is the link between the computer central processing unit and high-speed peripheral devices. It supports high data transmission rate and can reach a peak bandwidth of 132MB/s under the condition of 33M main frequency and 32-bit data bus, and it can be expanded It is 64-bit and is the mainstream bus in the PC field today.

计算机10是数字相机图像数据的接收终端，它为整个采集系统提供终端显示设备、数据存储设备等硬件设备，同时也为数字相机的图像数据最终与用户见面提供了软件实现。软件部分主要包括底层的设备驱动程序和上层的应用程序。设备驱动程序提供了计算机连接到PCI板卡的软件接口，它主要完成以下了工作：对设备的初始化、对端口的读写操作、对中断的处理、对内存的访问、对DMA的处理等，可以根据Windows驱动程序模型(WDM)来设计。应用程序可以采用Visual C++6.0进行开发，它提供了良好的用户界面，用户可以方便地对数字相机图像进行单帧采集、连续采集、实时显示、实时存盘等操作。Thecomputer 10 is the receiving terminal of digital camera image data. It provides hardware devices such as terminal display device and data storage device for the entire acquisition system, and also provides software implementation for the digital camera image data to finally meet with users. The software part mainly includes the device driver at the bottom layer and the application program at the upper layer. The device driver provides the software interface for the computer to connect to the PCI board. It mainly completes the following tasks: initialization of the device, read and write operations on the port, processing of interrupts, access to memory, processing of DMA, etc. Can be designed according to the Windows Driver Model (WDM). The application program can be developed with Visual C++6.0, which provides a good user interface, and users can conveniently perform operations such as single-frame acquisition, continuous acquisition, real-time display, and real-time storage of digital camera images.

计算机中软件部分的工作流程如图3所示，计算机启动后，操作系统首先检测是否存在PCI设备，如果不存在，则不加载驱动程序。如果操作系统检测到存在PCI设备，则为PCI设备加载驱动程序，初始化PCI设备，配置PCI9054，为DMA分配内存缓冲区等，为数字相机数据的实时采集工作做好准备，DMA操作准备就绪。计算机开始实时采集数字相机图像数据时，先判断向计算机发来的数据是否是新一帧数据，如果不是，则不断循环等待，一直等到有新一帧数据到来，从一帧的开头将数据写入FIFO，这样保证了FIFO中数据始终都是从一帧图像的帧头开始的，不会造成图像错位。一直向FIFO中写数据，直到FIFO半满的时候，开始DMA传输，将FIFO中数据读出，直接送至计算机内存，这样，数字相机的图像数据连续不断地写入FIFO，而FIFO中的图像数据又以DMA方式高速实时地送入计算机，实现了数字相机数据的实时采集。而且可根据实际的需要，对相机图像数据进行实时显示或实时存储。对相机数据的实时采集工作将连续进行，直至用户选择退出。The workflow of the software part in the computer is shown in Figure 3. After the computer is started, the operating system first detects whether there is a PCI device, and if it does not exist, the driver is not loaded. If the operating system detects that there is a PCI device, it loads the driver for the PCI device, initializes the PCI device, configures the PCI9054, allocates memory buffers for the DMA, etc., and prepares for the real-time acquisition of digital camera data, and the DMA operation is ready. When the computer starts to collect digital camera image data in real time, it first judges whether the data sent to the computer is a new frame of data, if not, it waits in a loop until a new frame of data arrives, and writes the data from the beginning of a frame Into the FIFO, which ensures that the data in the FIFO always starts from the frame header of a frame of image, and will not cause image misalignment. Write data to the FIFO until the FIFO is half full, start DMA transmission, read the data in the FIFO, and send it directly to the computer memory, so that the image data of the digital camera is continuously written into the FIFO, and the image in the FIFO The data is sent to the computer in high-speed and real-time by DMA, which realizes the real-time collection of digital camera data. Moreover, the camera image data can be displayed or stored in real time according to actual needs. The real-time collection of camera data will continue until the user chooses to exit.

下面以第二个实施例为例详细说明本发明的工作过程，第一个实施例只是少了驱动转换接口11进行电平转换处理的部分，其工作机理与第二个实施例均相同，整个系统的工作流程图如图4所示。The following takes the second embodiment as an example to describe the working process of the present invention in detail. The first embodiment only lacks the part that drives theconversion interface 11 to perform level conversion processing, and its working mechanism is the same as that of the second embodiment. The workflow of the system is shown in Figure 4.

整个系统可以实现以下操作：实时读相机数据、读FIFO状态以及写FIFO复位。The whole system can realize the following operations: read camera data in real time, read FIFO status and write FIFO reset.

1.实时读数字相机1的图像数据。1. Read the image data of thedigital camera 1 in real time.

计算机10在实时读取数字相机1的数据的同时，也实现了对数字相机1的同步控制。由计算机10给出脉冲宽度值，经过PCI总线9和PCI接口芯片7送到CPLD5，CPLD5根据这个脉冲宽度值输出相应宽度的触发脉冲，由控制线3发给数字相机1，触发数字相机1开始积分、采集图像，输出图像数据、行同步、帧同步以及时钟信号。While thecomputer 10 reads the data of thedigital camera 1 in real time, it also realizes the synchronous control of thedigital camera 1 . The pulse width value is given by thecomputer 10, and sent to the CPLD5 through thePCI bus 9 and thePCI interface chip 7, and the CPLD5 outputs a trigger pulse of a corresponding width according to the pulse width value, which is sent to thedigital camera 1 by thecontrol line 3, and thedigital camera 1 is triggered to start Integrate, collect images, output image data, line synchronization, frame synchronization and clock signals.

数字相机1将采集到的图像数据(包括同步信号)送到PCI图像采集卡4，PCI图像采集卡4收到数据后，首先经过驱动转换接口11进行电平转换处理，处理后的数据送到CPLD5处进行整合处理，将数据变换成为适合于PCI总线9传输的32bit的数据格式并实时存储在FIFO6中，等待FIFO达到半满状态后，将数据以DMA的方式实时地送入计算机，实现对数字相机数据的实时采集。具体操作如下：Digital camera 1 sends the collected image data (including synchronous signal) to PCIimage acquisition card 4, and after PCIimage acquisition card 4 receives the data, it first carries out level conversion processing throughdrive conversion interface 11, and the data after processing is sent to The CPLD5 is integrated and processed, and the data is converted into a 32-bit data format suitable forPCI bus 9 transmission and stored in FIFO6 in real time. After waiting for the FIFO to reach a half-full state, the data is sent to the computer in real time in the form of DMA. Real-time acquisition of digital camera data. The specific operation is as follows:

CPLD5首先要对数字相机发来的数据进行判断“是否是新一帧图像的开头”，如果是，CPLD5就置FIFO6复位，同时设置“可编程快满”偏移量和“可编程快空”偏移量，这就保证了在接收一帧数据的过程中高速缓存不会溢出，从而不会有丢象素的现象发生。然后等待图像的行同步信号由低变高，这时开始传输一行有效数据，CPLD5将每两个象元的数据整合成一组32bit的数据，放到FIFO6的输入数据线上，同时设定FIFO6的写允许信号WEN有效，并给出WCLK信号，在WCLK信号的上升沿把FIFO6输入数据线上的数据写入FIFO6中。CPLD5 first needs to judge "whether it is the beginning of a new frame image" on the data sent by the digital camera, if so, CPLD5 resets FIFO6, and sets the "programmable fast full" offset and "programmable fast empty" at the same time Offset, which ensures that the cache will not overflow during the process of receiving a frame of data, so that no pixel loss will occur. Then wait for the line synchronization signal of the image to change from low to high, and then start to transmit one line of valid data. CPLD5 integrates the data of each two pixels into a group of 32bit data, puts it on the input data line of FIFO6, and sets the data of FIFO6 at the same time The write permission signal WEN is effective, and the WCLK signal is given, and the data on the FIFO6 input data line is written into FIFO6 at the rising edge of the WCLK signal.

向FIFO中写数据写到半满的时候，开始DMA传输，从FIFO6中读出数据，直接送至计算机内存。读FIFO6中数据到计算机10时，CPLD5置FIFO6的读允许信号REN有效，输出允许信号OE有效，同时给出RCLK，在RCLK的每一个上升沿，FIFO6会把内部存储器中的数据顺序输出到PCI接口芯7片的数据线上，经由PCI总线9，将数字相机的图像数据送入计算机10的内存缓冲区，最后可根据实际需要，对相机图像数据进行单帧采集、连续采集或实时显示在计算机屏幕上。When writing data to FIFO and writing to half full, start DMA transmission, read data from FIFO6, send directly to computer memory. When reading the data in FIFO6 to thecomputer 10, CPLD5 sets the read enable signal REN of FIFO6 to be valid, the output enable signal OE is valid, and RCLK is given at the same time. On each rising edge of RCLK, FIFO6 will sequentially output the data in the internal memory to PCI On the data lines of the 7 interface chips, the image data of the digital camera is sent to the memory buffer of thecomputer 10 via thePCI bus 9, and finally the camera image data can be collected in a single frame, continuously collected or displayed in real time according to actual needs. on the computer screen.

以上向FIFO中写数据和读FIFO数据是同时进行的，一旦DMA传输开始后，数字相机的图像数据就连续不断地写入FIFO，而FIFO中的图像数据又以DMA方式实时地送入计算机，实现数字相机数据的实时采集。这里置WEN信号有效与否要受FIFO6的满信号(FF)控制，只有在FIFO6不满的情况下才允许数据写入；RCLK信号的给出与否要受FIFO6空信号(EF)的控制，只有在FIFO6非空的情况下才能将其中数据读出。当本行的数据传输完毕时，行同步信号就变低，CPLD5将等待行同步信号再次变高，即下一行有效数据到来时再开始对下一行象元数据进行同样的操作。当帧同步信号和行同步信号都变低时，表示一帧图像数据已经传输完毕。The above writing data to FIFO and reading FIFO data are carried out at the same time. Once the DMA transfer starts, the image data of the digital camera is continuously written into FIFO, and the image data in FIFO is sent to the computer in real time by DMA. Realize the real-time collection of digital camera data. Whether the WEN signal is valid or not is controlled by the full signal (FF) of FIFO6, and data writing is allowed only when FIFO6 is not full; whether the RCLK signal is given or not is controlled by the empty signal (EF) of FIFO6, only Only when FIFO6 is not empty can the data be read out. When the data transmission of this line is completed, the line synchronization signal becomes low, and the CPLD5 will wait for the line synchronization signal to become high again, that is, when the next line of valid data arrives, the same operation will be performed on the next line of pixel data. When both the frame synchronization signal and the line synchronization signal become low, it means that a frame of image data has been transmitted.

计算机10通过CPLD5，可以不断向数字相机1发送宽度由计算机10指定的触发脉冲，来触发数字相机1不断积分、采集图像，数字相机不断地输出图像数据、行同步、帧同步以及时钟信号，速率可达以30fps，这样，由计算机10同步控制数字相机1，实现了数字相机图像连续采集并传输的效果。等到帧同步信号再次变高时，CPLD5就如上所述开始采集下一帧图像。Thecomputer 10 can continuously send the trigger pulse whose width is specified by thecomputer 10 to thedigital camera 1 through the CPLD5 to trigger thedigital camera 1 to continuously integrate and collect images, and the digital camera continuously outputs image data, line synchronization, frame synchronization and clock signals, and the rate It can reach 30fps. In this way, thedigital camera 1 is synchronously controlled by thecomputer 10, realizing the effect of continuous acquisition and transmission of digital camera images. When the frame synchronization signal becomes high again, CPLD5 begins to collect the next frame image as mentioned above.

2.计算机10除了进行读相机数据的操作外，还可以读FIFO6的状态到计算机10，来决定对所述FIFO进行正确的操作。这时，CPLD5直接将此时FIFO6的四个状态(FULL、Almost FULL、EMPTY、Almost EMPTY)发送给PCI接口芯片7，经由PCI总线9送入计算机10。2. In addition to the operation of reading camera data, thecomputer 10 can also read the state of the FIFO6 to thecomputer 10 to determine the correct operation of the FIFO. At this time, CPLD5 directly sends four states (FULL, Almost FULL, EMPTY, Almost EMPTY) of FIFO6 toPCI interface chip 7, and sends it tocomputer 10 viaPCI bus 9.

3.若计算机10要写FIFO6复位，则计算机10发出一个FIFO复位指令，经过PCI总线9和PCI接口芯片7到CPLD5，由CPLD5发出一个复位脉冲到FIFO6，使高速缓存FIFO6回到复位状态。3. reset ifcomputer 10 will write FIFO6, thencomputer 10 sends a FIFO reset instruction, throughPCI bus 9 andPCI interface chip 7 to CPLD5, sends a reset pulse to FIFO6 by CPLD5, makes cache memory FIFO6 get back to reset state.

整个系统采用了高速PCI接口芯片，结合CPLD灵活的现场可更改性、可再配置能力，成功实现了数字相机到计算机的海量数据实时传输、显示和存储，采集速率可达480Mbps。系统具有采集速率高、实时性能好，操作简单、使用方便，工作稳定可靠等特点，用户可以方便地对数字相机进行单帧图像实时捕获、单帧图像数据实时显示、单帧图像数据实时保存、连续帧图像实时采集、连续帧图像实时显示、连续帧图像实时保存、实时读取图像采集卡中FIFO状态、实时置图像采集卡中FIFO复位。系统在数字图像采集及传输方面取得了积极的成果，而且，本系统具有广泛的应用前景，只需稍作改动即可用于其它信号的采集处理。The whole system uses a high-speed PCI interface chip, combined with the flexible on-site changeability and reconfigurability of CPLD, successfully realizes the real-time transmission, display and storage of massive data from the digital camera to the computer, and the acquisition rate can reach 480Mbps. The system has the characteristics of high acquisition rate, good real-time performance, simple operation, convenient use, stable and reliable work, etc. Users can conveniently capture single-frame images in real time, display single-frame image data in real time, save single-frame image data in real time, Real-time acquisition of continuous frame images, real-time display of continuous frame images, real-time storage of continuous frame images, real-time reading of FIFO status in the image acquisition card, real-time reset of FIFO in the image acquisition card. The system has achieved positive results in digital image acquisition and transmission. Moreover, this system has a wide application prospect and can be used for acquisition and processing of other signals with only a slight modification.

Claims

1. a real-time acquisition system for digital camera comprises computer, is inserted in the PCI image pick-up card on the described computer PCI slot, and the digital camera by data/address bus and described PCI IMAQ card connection; It is characterized in that:

Described PCI image pick-up card has been realized high-speed data acquisition and the transmission of digital camera to computer, specifically comprises CPLD logic control chip, high-speed cache, pci interface chip and configuration E thereof²PROM;

Described digital camera links to each other with CPLD logic control chip with control line by data/address bus; Described CPLD logic control chip links to each other with pci interface chip with described high-speed cache respectively; Described configuration E²PROM links to each other with pci interface chip; Described pci interface chip is connected with computer by pci bus;

Described CPLD logic control chip is realized the Synchronization Control of computer to digital camera by control line, comes the triggered digital camera to begin integration, gather and output image data by the triggering signal that width of CPLD logic control chip output is provided by computer;

Described CPLD logic control chip at first carries out integration processing to the view data that digital camera collects, data conversion is become 32bit data format and real-time storage in described high-speed cache, wait for when high-speed cache is half-full then, the data in real time that is stored in the described high-speed cache is read into pci interface chip, send into computer via pci bus;

The beginning that described CPLD logic control chip controls is cached at every frame data is put high-speed cache and is resetted, " able to programme fast full " side-play amount and " fast sky able to programme " side-play amount is set simultaneously, wait for that then the line synchronizing signal that digital camera is sent is uprised by low, begin to preserve delegation's valid data, thereby data are the frame head since a two field picture all the time in the assurance high-speed cache, can not cause image offset, and guarantee that high-speed cache can not cause pixel data to lose because of overflowing;

The state of described CPLD logic control chip by reading high-speed cache determined described high-speed cache is read or write operation to computer.

2. real-time acquisition system for digital camera according to claim 1, it is characterized in that: if the data of the LVDS form of described digital camera output, then described PCI image pick-up card also is provided with the driving translation interface, the data transaction of the LVDS form of described digital camera output is become export to CPLD logic control chip again after the data of TTL form and handle.

3. real-time acquisition system for digital camera according to claim 1 is characterized in that: described high-speed cache adopts high-speed synchronous first in first out buffer, to guarantee the zero access of data.

4. real-time acquisition system for digital camera according to claim 1 is characterized in that: described computer is used for controlling CPLD logic control chip to carry out single-frame images to digital camera and catches, the single-frame images data in real time is presented on the computer display, the single-frame images data in real time is saved in the hard disc of computer, described digital camera is carried out the IMAQ of continuous time, on computer display, show the consecutive image data in real time, the consecutive image data in real time is saved in the hard disc of computer, read the state of described high-speed cache in real time, read the line number at pixel place in real time.