CN1713164A - DMA controller capable of autonomously processing multi-transaction transmission requirements and data transmission method - Google Patents
DMA controller capable of autonomously processing multi-transaction transmission requirements and data transmission methodDownload PDFInfo
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Abstract
Description
Translated fromChinese技术领域technical field
本发明属微电子技术领域，具体涉及一种DMA(Direct Memory Access，直接存储器存取)控制器以及多事务传输的数据传输方法，尤其涉及一种可根据传输描述符自主处理多事务传输要求的DMA控制器以及数据传输方法。The invention belongs to the field of microelectronics technology, and in particular relates to a DMA (Direct Memory Access) controller and a data transmission method for multi-transaction transmission, in particular to a DMA (Direct Memory Access, direct memory access) controller which can independently process multi-transaction transmission requirements according to a transmission descriptor DMA controller and data transfer method.
背景技术Background technique
在传统的系统芯片设计中，DMA控制器(DMAC)是系统总线上的一个附加模块，它能在处理器不需要占用总线时代替处理器控制数据在存储器与存储器之间，或者存储器与数据通信模块之间，或者数据通信模块与数据通信模块之间进行传输。其优点是在数据传输过程中避免了处理器对每一个I/O传输都要进行控制，将处理器从繁重的数据传输任务中解放出来。传统的带有DMA控制器的芯片系统结构如图1所示，系统总线与设备总线通过专门的桥模块(107)连接，DMA控制器(103)不在数据通道上，而是通过专门的控制线对各个数据通信模块进行控制，接收和响应它们的传输请求，如USB模块(106)，并且，DMA控制器在其内部寄存器接受处理器(101)的写配置后，可以独立安排一次数据传输过程，传输完成后DMA控制器将传输结果通过处理器读寄存器的方式返回给处理器。In the traditional system chip design, the DMA controller (DMAC) is an additional module on the system bus, which can replace the processor to control data between memory and memory, or memory and data communication when the processor does not need to occupy the bus Between modules, or between data communication modules and data communication modules. The advantage is that the processor is prevented from controlling each I/O transmission during data transmission, and the processor is freed from heavy data transmission tasks. The structure of a traditional chip system with a DMA controller is shown in Figure 1, the system bus and the device bus are connected through a special bridge module (107), and the DMA controller (103) is not on the data channel, but through a special control line Control each data communication module, receive and respond to their transmission requests, such as the USB module (106), and the DMA controller can independently arrange a data transmission process after its internal register accepts the write configuration of the processor (101) After the transfer is completed, the DMA controller returns the transfer result to the processor by means of the processor reading the register.
根据系统结构的不同，每个数据通信模块可以各自带有一个DMA控制器，也可以几个数据通信模块复用一个DMA控制器。不管是哪一种系统结构，其DMA工作流程都如图2所示。首先数据通信模块发出传输请求(201)，DMA发出总线申请(202)；处理器响应DMA总线申请，等待总线空闲的时候配置DMA控制器中的寄存器，授权DMA控制器开始发起一次传输(203)，这一步需要处理器的参与；随后，DMA控制开始替代处理器处理安排一次数据传输过程(204)，包括存储器地址的更换，数据的缓冲，传输过程的监视等。在一次传输完成后(205)，处理器再次参与传输过程，读入DMA控制器的状态寄存器中的信息，判断是否安排重传(206)，或者是否安排下一此传输(207)，或者结束此次传输(208)，在前两种情况下，处理器都需要再次写DMA控制器的操作寄存器。Depending on the system structure, each data communication module can have a DMA controller, or several data communication modules can multiplex a DMA controller. No matter what kind of system structure, its DMA workflow is shown in Figure 2. First, the data communication module sends a transmission request (201), and the DMA sends a bus application (202); the processor responds to the DMA bus application, waits for the register in the DMA controller to be configured when the bus is free, and authorizes the DMA controller to initiate a transmission (203) , this step requires the participation of the processor; then, the DMA control starts to replace the processor to process and arrange a data transmission process (204), including the replacement of memory addresses, data buffering, and monitoring of the transmission process. After a transmission is completed (205), the processor participates in the transmission process again, reads the information in the status register of the DMA controller, and judges whether to arrange retransmission (206), or whether to arrange the next transmission (207), or end For this transfer (208), in the first two cases, the processor needs to write the operation register of the DMA controller again.
现在的集成电路片上系统(SOC)往往是包含多事务传输要求的系统，如带有USB主机控制器模块的系统，由于按照USB协议要求，每次事务传输的数据长度有最大值(如在USB2.0的批量传输条件下是512byte)，那么每次接收或者发送512byte的数据，处理器就必须响应一次DMA请求。这样，传统的DMA控制器以及数据传输控制方法虽然在一定程度上减少了处理器在数据传输过程中的工作，提高了系统效率，但这只适合传输事务较少的情况下。在经常有多个传输事务，且传输事务的个数不定的系统中，需要处理器一次性将所有事务都安排好，然后等到这些事务完成后再响应DMA请求，才能最大限度的提高系统效率。因此，传统的向DMA控制器中的有限个寄存器写传输事务信息的方式就不再适合这样的系统要求。The current integrated circuit system-on-chip (SOC) is often a system that includes multiple transaction transmission requirements, such as a system with a USB host controller module. According to the requirements of the USB protocol, the data length of each transaction transmission has a maximum value (such as in USB2 .0 bulk transfer condition is 512byte), then every time 512byte data is received or sent, the processor must respond to a DMA request. In this way, although the traditional DMA controller and data transmission control method reduce the work of the processor in the data transmission process to a certain extent and improve the system efficiency, it is only suitable for the case of fewer transmission transactions. In a system that often has multiple transfer transactions and the number of transfer transactions is indefinite, the processor needs to arrange all transactions at one time, and then wait until these transactions are completed before responding to DMA requests, in order to maximize system efficiency. Therefore, the traditional method of writing and transferring transaction information to a limited number of registers in the DMA controller is no longer suitable for such system requirements.
发明内容Contents of the invention
本发明的目的在于提供一种应用于有多事务传输要求的系统中的可自主处理多事务传输要求的DMA控制器，以及一种使用这种DMA控制器来进行数据传输控制的方法，以减少传输过程中处理器资源的消耗，降低处理器响应DMA请求的频率，同时又可以保证数据传输的带宽要求，最大化提高系统芯片的整体性能。The purpose of the present invention is to provide a kind of DMA controller that can autonomously handle the multi-transaction transmission requirement in the system that is applied to multi-transaction transmission requirement, and a kind of method that uses this DMA controller to carry out data transmission control, to reduce The consumption of processor resources during the transmission process reduces the frequency of the processor responding to DMA requests, while ensuring the bandwidth requirements of data transmission and maximizing the overall performance of the system chip.
本发明提供的可自主处理多事务传输要求的DMA控制器，包括：The DMA controller that can autonomously handle multi-transaction transmission requirements provided by the present invention includes:
一个系统总线的从设备接口，用于接收处理器写入到存储器中的事务传输链表的初始地址，也可用于接收处理器发起和结束数据传输的命令。A slave device interface of the system bus, which is used to receive the initial address of the transaction transmission linked list written by the processor into the memory, and can also be used to receive commands from the processor to initiate and end data transmission.
一个系统总线的主设备接口，用于从存储器中读出或向存储器写入传输描述符和传输数据。A master device interface of the system bus, used to read from the memory or write the transfer descriptor and transfer data to the memory.
一个设备总线的桥设备接口，作为系统总线与设备总线间的桥设备把存储器中的数据向各个数据通信模块输出，或者把各个数据通信模块接收到的数据送往存储器。为了数据在两条总线之间正确传输，桥设备接口带有专门的时钟域转换电路。A bridge device interface of the device bus, as a bridge device between the system bus and the device bus, outputs the data in the memory to each data communication module, or sends the data received by each data communication module to the memory. In order to transmit data correctly between the two buses, the bridge device interface has a dedicated clock domain conversion circuit.
多个与各设备通信模块相连的控制信号线，配合传输数据对各设备通信模块进行控制。A plurality of control signal lines connected to the communication modules of each device are used to control the communication modules of each device in cooperation with data transmission.
上述系统总线一般为片内高速总线，上述设备总线一般为片内低速总线，但不排除系统总线的传输速度与设备总线的传输速度相当，甚至比设备总线的传输速度更低。The above-mentioned system bus is generally an on-chip high-speed bus, and the above-mentioned device bus is generally an on-chip low-speed bus, but it does not rule out that the transmission speed of the system bus is equivalent to the transmission speed of the device bus, or even lower than the transmission speed of the device bus.
上述存储器中带有一个可供处理器和DMA控制器共同访问的共享内存区，它是一块专门的地址段。并且在存储器的总线接口带有仲裁电路，使得处理器和DMA控制器同时访问存储器时，调整处理器和DMA控制器的优先级。The above-mentioned memory has a shared memory area that can be accessed by the processor and the DMA controller, which is a special address segment. And the bus interface of the memory has an arbitration circuit, so that when the processor and the DMA controller access the memory at the same time, the priorities of the processor and the DMA controller are adjusted.
上述处理器能够根据数据通信模块的传输请求，将包含传输信息的特定的传输描述符组织成链表的形式写入到存储器的共享内存区中，同时也可以从共享内存区中读入传输描述符获知传输完成的情况。According to the transmission request of the data communication module, the above-mentioned processor can organize the specific transmission descriptor containing the transmission information into a linked list and write it into the shared memory area of the memory, and can also read the transmission descriptor from the shared memory area Notified of transfer completion.
上述存储器中事务传输链表是以一种或多种数据结构组织而成的数据组织方式，其链表的基本单元是传输描述符，各个传输描述符之间通过指针相互连接，其实际物理地址可以连续也可以不连续。The transaction transfer linked list in the above memory is a data organization method organized by one or more data structures. The basic unit of the linked list is the transfer descriptor, and the transfer descriptors are connected to each other through pointers, and their actual physical addresses can be continuous. It can also be discontinuous.
上述存储器中传输描述符是以一种或多种数据结构组织而成，用于描述一个传输事务的所有信息的集合，其中必然包括的信息有：传输数据在存储器中的初始地址、传输数据的长度、传输数据的方向，可选包括的信息有：进行此次传输的数据通信模块、与此次传输相对应的远程设备地址、其它与特定数据传输协议相关的信息。The transfer descriptor in the above-mentioned memory is organized by one or more data structures, and is used to describe a collection of all information of a transfer transaction. The information that must be included in it is: the initial address of the transfer data in the memory, the address of the transfer data The length, the direction of the data to be transmitted, the optional information included: the data communication module for this transmission, the address of the remote device corresponding to this transmission, and other information related to the specific data transmission protocol.
上述存储器中传输描述符的长度可固定或浮动，如果长度浮动，需要有一个结束标志来通知DMA控制器完成此次传输描述符的读入。传输描述符的实际物理地址可连续或不连续，如果不连续，各个物理字节之间需要有指针来连接。The length of the transfer descriptor in the above memory can be fixed or floating. If the length is floating, an end flag is required to notify the DMA controller to complete the reading of the transfer descriptor. The actual physical address of the transfer descriptor can be continuous or discontinuous. If not, pointers are needed to connect each physical byte.
上述存储器中传输描述符可由DMA控制器读入并解析其中包含的信息，也可由DMA控制器在传输完成或中止后写回，写回的传输描述符中包含此次传输完成或中止的情况，可由处理器在需要的时候进行了解。The transfer descriptor in the above memory can be read by the DMA controller and parse the information contained therein, and can also be written back by the DMA controller after the transfer is completed or terminated, and the written-back transfer descriptor includes the completion or termination of the transfer, Can be learned by the processor when needed.
上述DMA控制器带有一个能写入事务传输链表首址的寄存器，可以不直接从处理器获得一次或多次传输数据在存储器中的地址，而是仅从处理器获得在存储器中事务传输链表的初始地址，根据这个地址，从存储器的共享内存区中按照数据传输链表的连接顺序依次读入各个传输描述符。The above-mentioned DMA controller has a register that can be written into the first address of the transaction transmission linked list, and can not directly obtain the address of one or more transmission data in the memory from the processor, but only obtain the transaction transmission linked list in the memory from the processor According to this address, each transfer descriptor is sequentially read in from the shared memory area of the memory according to the connection sequence of the data transfer linked list.
上述DMA控制器带有一个能对传输描述符进行解析的结构单元，能够按照传输描述符的类型进行解析，从中提取数据传输长度，数据首地址，数据传输方向等信息，能够按照当前相应的数据通信模块的状态，适时发起数据传输，安排数据在系统总线与设备总线间无间断的传输，并能对已传输的数据量进行跟踪。The above-mentioned DMA controller has a structural unit capable of parsing the transfer descriptor, which can be parsed according to the type of the transfer descriptor, and information such as data transfer length, data first address, and data transfer direction can be extracted from it, and can be used according to the current corresponding data The status of the communication module can initiate data transmission in a timely manner, arrange for uninterrupted transmission of data between the system bus and the device bus, and can track the amount of transmitted data.
上述DMA控制器可作为系统总线与设备总线的数据桥，数据在两条总线间传输时都要通过DMA控制器，这样所有的数据传输都可以由DMA控制器发起、跟踪和控制。The above-mentioned DMA controller can be used as a data bridge between the system bus and the device bus. When data is transmitted between the two buses, it must pass through the DMA controller, so that all data transmissions can be initiated, tracked and controlled by the DMA controller.
一种可自主处理多事务传输要求的DMA控制器的数据传输方法，应用于通过存储器中的传输描述符来进行事务传输请求的信息传递，由DMA控制器动态安排多个事务传输发起和结束时间的系统芯片中，包括处理器、存储器、DMA控制器/桥、系统总线、设备总线和数据通信模块，其特征在于，包括如下步骤：A data transmission method of a DMA controller that can autonomously handle multi-transaction transfer requirements, applied to the information transfer of transaction transfer requests through the transfer descriptor in the memory, and the DMA controller dynamically arranges the start and end times of multiple transaction transfers In the system chip, comprise processor, memory, DMA controller/bridge, system bus, equipment bus and data communication module, it is characterized in that, comprises the following steps:
首先处理器根据数据通信模块的传输需要，从驱动库中找到相应的驱动程序、将传输描述符组织成传输链表写入到存储器的共享内存区中；处理器把传输链表的初始地址写入到DMA控制器的相应寄存器中；First, according to the transmission needs of the data communication module, the processor finds the corresponding driver program from the driver library, organizes the transmission descriptor into a transmission linked list and writes it into the shared memory area of the memory; the processor writes the initial address of the transmission linked list into In the corresponding register of the DMA controller;
然后DMA控制器根据传输链表的初始地址在存储器的共享内存区中找到第一个传输描述符；DMA控制器根据这个传输描述符的信息发起数据在存储器与数据通信模块之间的传输；Then the DMA controller finds the first transfer descriptor in the shared memory area of the memory according to the initial address of the transfer linked list; the DMA controller initiates the transmission of data between the memory and the data communication module according to the information of the transfer descriptor;
如果传输没有完成，DMA控制器继续更新访问存储器的地址，并对传输的数据进行计数；If the transfer is not completed, the DMA controller continues to update the address of the access memory and count the transferred data;
如果传输完成，并且在传输过程中出现错误，则由传输描述符中解析出来的信息要求保证传输正确性，DMA控制器安排重传；If the transfer is complete and an error occurs during the transfer, the information parsed from the transfer descriptor is required to ensure the correctness of the transfer, and the DMA controller arranges retransmission;
如果传输完成，并且在传输过程中没有出现错误，或者即使出现错误但是传输描述符中解析出来的信息不要求保证传输正确性，DMA控制器不安排重传，把此次传输信息写回到共享内存区中的传输描述符中；If the transfer is complete and there is no error during the transfer, or even if an error occurs but the information parsed from the transfer descriptor does not require the correctness of the transfer, the DMA controller does not arrange retransmission and writes the transfer information back to the shared In the transfer descriptor in the memory area;
如果由传输描述符中解析出来的信息表明还有下一次的传输事务，DMA控制器根据链接指针找到下一个传输描述符，从中解析出传输信息，安排总线数据传输；If the information parsed from the transfer descriptor indicates that there is a next transfer transaction, the DMA controller finds the next transfer descriptor according to the link pointer, parses the transfer information from it, and arranges the bus data transfer;
如果由传输描述符中解析出来的信息表明没有下一次的传输事务，DMA控制器的此次传输结束，向处理器报告。If the information parsed from the transfer descriptor indicates that there is no next transfer transaction, the transfer of the DMA controller ends and reports to the processor.
上述的可自主处理多事务传输要求的DMA控制器的数据传输方法中，DMA控制器能够根据一次传输完成或未完成的情况，安排下一事务的传输或此次事务的重传，不需要处理器来干预。In the above-mentioned data transmission method of the DMA controller that can autonomously handle the requirements of multi-transaction transmission, the DMA controller can arrange the transmission of the next transaction or the retransmission of this transaction according to the completion or incompleteness of one transmission without processing device to intervene.
本发明的独到优势在于：在有多事务传输要求的系统中，处理器可以一次性把所有事务传输要求以传输描述符的形式写入到存储器的共享内存区中，然后由DMA控制器来自主的安排各个事务的传输，包括出错重传机制。直到所有的传输事务都完成后，DMA控制器才向处理器进行报告。这样可以减少传输过程中处理器资源的消耗，降低处理器响应DMA请求的频率，同时又可以保证数据传输的带宽要求，最大化提高系统芯片的整体性能。The unique advantage of the present invention is that: in a system with multiple transaction transfer requirements, the processor can write all transaction transfer requirements into the shared memory area of the memory in the form of transfer descriptors at one time, and then the DMA controller will automatically Arrange the transmission of each transaction, including the error retransmission mechanism. The DMA controller does not report to the processor until all transfer transactions are complete. This can reduce the consumption of processor resources during the transmission process, reduce the frequency of the processor responding to DMA requests, and at the same time ensure the bandwidth requirements of data transmission, and maximize the overall performance of the system chip.
附图说明Description of drawings
图1为传统的带有DMA控制器的系统结构示意图；Fig. 1 is a traditional system structure diagram with a DMA controller;
图2为传统的DMA控制器工作流程图；Fig. 2 is a traditional DMA controller work flow chart;
图3为本发明的带有DMA控制器的系统结构示意图；Fig. 3 is a schematic structural diagram of a system with a DMA controller of the present invention;
图4为本发明的DMA控制器控制数据传输方式流程图；Fig. 4 is the flow chart of DMA controller control data transmission mode of the present invention;
图5为图3中的共享内存区中传输描述符范例；FIG. 5 is an example of a transfer descriptor in the shared memory area in FIG. 3;
图6为图3中DMA控制器范例。Figure 6 is an example of the DMA controller in Figure 3 .
图中标号如下：The numbers in the figure are as follows:
101为片内处理器，102为片内存储器，103为DMA控制器，104为系统总线，105为设备总线，106为数据通信模块(如USB)，107为总线桥。101 is an on-chip processor, 102 is an on-chip memory, 103 is a DMA controller, 104 is a system bus, 105 is a device bus, 106 is a data communication module (such as USB), and 107 is a bus bridge.
201为数据通信模块发出传输请求，202为DMA控制器发出总线申请，203为处理器配置DMA控制器中的寄存器，204为DMA控制器控制总线传输，205为DMA控制器判断传输是否完成，206为处理器判断是否进行重传，207为判断处理器是否进行下一步传输，208为传输结束。201 sends a transmission request for the data communication module, 202 sends a bus application for the DMA controller, 203 configures registers in the DMA controller for the processor, 204 controls the bus transmission for the DMA controller, and 205 judges whether the transfer is completed for the DMA controller, 206 Step 207 is for the processor to judge whether to perform retransmission, step 207 is for the processor to judge whether to perform the next transmission, and step 208 is for the end of the transfer.
301为片内处理器，302为片内存储器(其中包含一块共享内存区)，303为DMA控制器/总线桥模块，304为系统总线，305为设备总线，306为数据通信模块(如USB)。301 is an on-chip processor, 302 is an on-chip memory (including a shared memory area), 303 is a DMA controller/bus bridge module, 304 is a system bus, 305 is a device bus, and 306 is a data communication module (such as USB) .
401为数据通信模块发出传输请求，402为DMA控制器发出总线申请，403为处理器向共享内存区中写入传输事务链表，404为DMA控制器从共享内存区中读入传输描述符，405为DMA控制器控制总线传输，406为DMA控制器判断传输是否完成，407为DMA控制器判断是否进行重传，408为DMA控制器判断是否进行下一步传输，409为传输结束。401 is for the data communication module to send a transfer request, 402 is for the DMA controller to send a bus request, 403 is for the processor to write the transfer transaction list into the shared memory area, 404 is for the DMA controller to read the transfer descriptor from the shared memory area, 405 406 is for the DMA controller to judge whether the transmission is completed, 407 is for the DMA controller to judge whether to retransmit, 408 is for the DMA controller to judge whether to perform the next transmission, and 409 is for the end of the transmission.
具体实施方式Detailed ways
以下参照附图详细描述本发明的具体实施方式。Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
图3为本发明的DMA控制器与系统其它模块连接的系统结构图，DMA控制器(303)与系统各个模块的连接关系如下：Fig. 3 is the system structural diagram that DMA controller of the present invention is connected with other modules of the system, and the connection relation of DMA controller (303) and each module of system is as follows:
与系统总线(304)：DMA控制器(303)既可作为系统总线的主设备，也可作为系统总线的从设备工作。With the system bus (304): the DMA controller (303) can work as both the master device of the system bus and the slave device of the system bus.
与系统总线上的片内处理器(301)：处理器可通过系统总线寻址访问到DMA控制器内部的设置和状态寄存器，处理器可以向DMA控制器写入传输链表首址，处理器可以向DMA控制器写入开始或中止传输标志位，但是处理器不直接向DMA控制器写入每次传输数据在存储器中的地址和数据长度，以及与一次传输事务相关的信息。On-chip processor (301) on the system bus: the processor can access the internal setting and status registers of the DMA controller through the system bus addressing, the processor can write the first address of the transmission linked list to the DMA controller, and the processor can Write the start or stop transfer flag bit to the DMA controller, but the processor does not directly write the address and data length of the data in the memory for each transfer to the DMA controller, as well as information related to a transfer transaction.
与系统总线上的片内存储器(302)：存储器内部专门有一个地址段称为共享内存区，可由处理器和DMA控制器访问。存储器可以是双口存储器，也可以是单口存储器，如果存储器是单口存储器，那么存储器与系统总线连接处需要有一个仲裁电路来对处理器和DMA控制器的访问请求进行仲裁。DMA控制器可以通过系统总线，从存储器的共享内存区中读出或写入传输描述符和传输数据。On-chip memory (302) on the system bus: there is an address segment called a shared memory area inside the memory, which can be accessed by the processor and the DMA controller. The memory can be a dual-port memory or a single-port memory. If the memory is a single-port memory, an arbitration circuit is required at the connection between the memory and the system bus to arbitrate the access requests of the processor and the DMA controller. The DMA controller can read or write the transfer descriptor and transfer data from the shared memory area of the memory through the system bus.
与设备总线(305)：DMA控制器作为设备总线与系统总线之间的桥设备，能够完成数据在两个时钟域之间转换时的同步功能。And device bus (305): The DMA controller, as a bridge device between the device bus and the system bus, can complete the synchronization function when data is converted between two clock domains.
与设备总线上的数据通信模块(306)：DMA控制器与这些数据通信模块之间的控制信号有专门控制线连接，传输数据通过设备总线连接，DMA控制器能够根据传输描述符的信息向特定的数据通信模块(如USB)发出数据输入输出命令，并提供相应的传输信息，如目标地址，目标设备等。With the data communication module (306) on the device bus: the control signal between the DMA controller and these data communication modules has a special control line connection, and the transmission data is connected through the device bus. The data communication module (such as USB) issues data input and output commands, and provides corresponding transmission information, such as target address, target device, etc.
在本发明中，DMA控制器包含专门的解析单元，能够对共享内存区中的传输描述符进行解析，并从中提取出与一次数据传输事务相关的传输信息，如传输数据地址，传输数据长度，传输方向，传输类型等。并且，DMA控制器能够从一个传输描述符中找到下一个传输描述符的地址，或者判断这个传输描述符是否是最后一个。In the present invention, the DMA controller includes a special analysis unit, which can analyze the transfer descriptor in the shared memory area, and extract the transfer information related to a data transfer transaction, such as the address of the transfer data, the length of the transfer data, Transmission direction, transmission type, etc. And, the DMA controller can find the address of the next transfer descriptor from a transfer descriptor, or judge whether the transfer descriptor is the last one.
在本发明中，DMA控制器包含一组寄存器，仅用来接收从处理器写入的事务传输链表首地址。In the present invention, the DMA controller includes a set of registers, which are only used to receive the head address of the transaction transmission linked list written from the processor.
在本发明中，DMA控制器包含传输控制单元，能够在一次传输完成或因异常而中止后，根据传输描述符的信息自主决定重传或者下一次传输。In the present invention, the DMA controller includes a transmission control unit, which can independently decide to retransmit or next transmission according to the information of the transmission descriptor after one transmission is completed or suspended due to abnormality.
在本发明中，DMA控制器能够在传输完成时通过状态寄存器或者中断的方式向处理器报告。In the present invention, the DMA controller can report to the processor through a status register or an interrupt when the transfer is completed.
在本发明中，DMA控制器能够根据传输的需要，自主选择连续传输方式(burst)或者单个传输方式(single)。In the present invention, the DMA controller can independently select a continuous transmission mode (burst) or a single transmission mode (single) according to transmission requirements.
图4为本发明的DMA控制器控制的数据传输方式流程图，DMA工作的步骤如下：Fig. 4 is the flow chart of the data transmission mode controlled by the DMA controller of the present invention, and the steps of DMA work are as follows:
步骤401：设备总线上的数据通信模块将传输请求发到DMA控制器，这通过DMA控制器与数据通信模块之间专门的控制线完成。Step 401: The data communication module on the device bus sends a transmission request to the DMA controller, which is completed through a dedicated control line between the DMA controller and the data communication module.
步骤402：DMA控制器向处理器发出传输请求，这可以却不局限于通过向处理器申请中断的方式实现。Step 402: The DMA controller sends a transfer request to the processor, which can be implemented by but not limited to requesting an interrupt from the processor.
步骤403：处理器根据DMA控制器发出的传输申请的类型，从驱动程序库中找到相应的驱动程序，一次性把这次传输请求分解为多个传输描述符，以传输事务链表的方式写入存储器的共享内存区中，然后把传输事务链表的首地址写入DMA控制器的寄存器中。Step 403: According to the type of transfer request sent by the DMA controller, the processor finds the corresponding driver program from the driver library, decomposes this transfer request into multiple transfer descriptors at one time, and writes them in the form of a transfer transaction linked list In the shared memory area of the memory, then write the first address of the transfer transaction linked list into the register of the DMA controller.
步骤404：DMA控制器从共享内存区中读入一个传输描述符，从中解析出相应的传输信息。Step 404: The DMA controller reads a transfer descriptor from the shared memory area, and parses out corresponding transfer information from it.
步骤405：DMA控制器控制数据在存储器与数据通信模块之间的传输，数据经过DMA控制器作为的桥在系统总线与设备总线之间流动。Step 405: the DMA controller controls the transmission of data between the memory and the data communication module, and the data flows between the system bus and the device bus through the DMA controller as a bridge.
步骤406：DMA控制器根据需要传输的数据长度和实际传输的数据长度，以及传输过程中发生异常的情况，判断这次传输是否完成，如果没有完成，则继续传输，如果完成或因为异常而中止，进入下一步判断。Step 406: The DMA controller judges whether the transfer is completed according to the length of the data to be transferred and the length of the actual data to be transferred, as well as the abnormal situation during the transfer process. If not, continue the transfer. If it is completed or stop due to an exception , enter the next step of judgment.
步骤407：DMA控制器在一次传输事务完成后，判断是否需要重传。如果在传输过程中出现错误，而由传输描述符中解析出来的信息要求保证传输正确性，DMA控制器安排重传，回到步骤405；如果在传输过程中没有出现错误，或者即使出现错误但是传输描述符中解析出来的信息不要求保证传输正确性，DMA控制器不安排重传，把此次传输信息写回到共享内存区中的传输描述符中，进入下一步判断；Step 407: The DMA controller determines whether a retransmission is required after a transaction is completed. If there is an error in the transmission process, and the information parsed out from the transmission descriptor requires to ensure the correctness of the transmission, the DMA controller arranges retransmission and returns to step 405; if there is no error in the transmission process, or even if there is an error but The information parsed from the transfer descriptor is not required to ensure the correctness of the transfer, and the DMA controller does not arrange retransmission, and writes the transfer information back to the transfer descriptor in the shared memory area, and enters the next step of judgment;
步骤408：DMA控制器判断是否进行下一次传输。如果由传输描述符中解析出来的信息表明还有下一次的传输事务，DMA控制器根据链接指针回到步骤404，安排总线数据传输；如果由传输描述符中解析出来的信息表明没有下一次的传输事务，DMA控制器的此次传输结束。Step 408: The DMA controller judges whether to perform the next transmission. If the information parsed out from the transfer descriptor shows that there is a next transfer transaction, the DMA controller returns to step 404 according to the link pointer to arrange bus data transmission; if the information parsed out from the transfer descriptor shows that there is no next time Transfer transaction, the transfer of the DMA controller ends.
步骤409：DMA控制器传输结束，向处理器报告。Step 409: The DMA controller transfers and reports to the processor.
图5和图6为本发明提供了一个范例。Figures 5 and 6 provide an example of the present invention.
图5为图3所述的共享内存区中传输描述符的范例。找个传输描述符由存储在4个连续的地址中的数据构成，包含了不同的字段，包括：FIG. 5 is an example of a transfer descriptor in the shared memory area shown in FIG. 3 . A transfer descriptor consists of data stored in 4 consecutive addresses and contains different fields, including:
Next Pointer：指向下一个传输描述符地址的指针。Next Pointer: A pointer to the address of the next transfer descriptor.
V(Value)：说明这个传输描述符的有效性，在DMA控制器未执行前由处理器置1，表示有效；在DMA控制器执行完后由DMA控制器置0，表示无效。V (Value): Indicates the validity of this transfer descriptor. It is set to 1 by the processor before the DMA controller is executed, indicating that it is valid; it is set to 0 by the DMA controller after the DMA controller is executed, indicating that it is invalid.
H(Head)：说明这个传输描述符是否是传输事务链表的表头。如果为1，表示是表头，如果是0，则表示不是表头。在环形链表中，如果两次出现这个字段为1，则可认为所有的传输都已完成。H(Head): Indicates whether this transfer descriptor is the head of the transfer transaction linked list. If it is 1, it means it is a header, if it is 0, it means it is not a header. In the circular linked list, if this field is 1 twice, it can be considered that all transmissions have been completed.
Data Length：这次传输的数据长度。Data Length: The data length of this transmission.
Data PageL：这次传输的数据在存储器中的页面号。这可用于在多页面管理的存储系统中。Data PageL: The page number of the data transferred this time in the memory. This can be used in multi-page managed storage systems.
I/O：这次传输的方向。如果为1，则表示对存储器来说是输入，数据由数据通信模块输入到存储器中；如果为0，则表示对存储器来说是输出，数据由存储器输入到数据通信模块中。I/O: The direction of this transfer. If it is 1, it means that it is an input to the memory, and the data is input to the memory by the data communication module; if it is 0, it means that it is an output to the memory, and the data is input from the memory to the data communication module.
Data Offset：这次传输的数据在存储器中的页内偏移。这可用于在多页面管理的存储系统中。Data Offset: The data transferred this time is offset within the page in the memory. This can be used in multi-page managed storage systems.
T(Terminate)：传输链表结束标志。如果为1，则表示传输链表已至表尾；否则，则表示传输链表未完。这可用于在非环形链表中判断事务传输链表的结束。T (Terminate): The end flag of the transmission linked list. If it is 1, it means that the transmission linked list has reached the end; otherwise, it means that the transmission linked list is not finished. This can be used to determine the end of the transaction transfer linked list in a non-circular linked list.
图6为图3所述的DMA控制器内部结构范例。内部结构包括：FIG. 6 is an example of the internal structure of the DMA controller shown in FIG. 3 . The internal structure includes:
一组系统总线主设备的数据口(ram_data_i、ram_data_o)和地址口(ram_addr_o)，用来从存储器中读写数据和传输描述符。A set of data ports (ram_data_i, ram_data_o) and address ports (ram_addr_o) of the system bus master are used to read and write data and transfer descriptors from the memory.
一组系统总线从设备的数据接口(register_i、register_o)，用来接收处理器写入的传输事务链表首址。A group of data interfaces (register_i, register_o) of the system bus slave devices are used to receive the first address of the transmission transaction linked list written by the processor.
一组设备总线桥设备的数据口(txdata、rxdata)和控制线(control lines)，用来对设备总线上的数据通信模块进行数据和控制信号的输出或输入。A set of data ports (txdata, rxdata) and control lines (control lines) of the device bus bridge device are used to output or input data and control signals to the data communication modules on the device bus.
一对系统总线和设备总线上的缓存单元(Data Buffer)。A pair of cache units (Data Buffer) on the system bus and the device bus.
一个数据通道上的桥结构，包括时钟域转换电路(Data Bridge)。A bridge structure on a data channel, including a clock domain conversion circuit (Data Bridge).
一个传输描述符的存储单元(DP Buffer)，用来临时保存从共享内存区中读入的传输描述符，可以从中解析出传输事务信息；另外在传输完成后，也可以更新其中相应信息，并写回到共享内存区中。A transfer descriptor storage unit (DP Buffer) is used to temporarily save the transfer descriptor read from the shared memory area, from which the transfer transaction information can be parsed; in addition, after the transfer is completed, the corresponding information can also be updated, and Write back to the shared memory area.
一个传输描述符的解析单元(DP Decode)，用来从传输描述符中解析出有用信息，控制数据通信模块的控制线和DMA控制器内部逻辑。A transfer descriptor analysis unit (DP Decode), used to parse useful information from the transfer descriptor, control the control line of the data communication module and the internal logic of the DMA controller.
一个寄存器单元(DP Address Register)，用来接收处理器写入的传输事务链表首地址。A register unit (DP Address Register) is used to receive the first address of the transmission transaction list written by the processor.
一个存储器读写地址控制单元，包括页面控制单元(Page Control)和偏移控制单元(Offset Control)，用来在读写传输描述符和读写传输数据时实时产生相应的存储器物理地址。处理器写入的事务传输链表首地址也保存在这里。A memory read and write address control unit, including a page control unit (Page Control) and an offset control unit (Offset Control), used to generate corresponding memory physical addresses in real time when reading and writing transfer descriptors and reading and writing transfer data. The first address of the transaction transmission linked list written by the processor is also stored here.
一个传输控制单元(Transfer Control)，用来根据传输事务的要求和传输的实际情况，自主安排重传机制及传输进程控制。A transfer control unit (Transfer Control), which is used to independently arrange the retransmission mechanism and transfer process control according to the requirements of the transfer transaction and the actual situation of the transfer.
最后所应说明的是：以上实施例仅用以说明而非限制本发明的技术方案，尽管参照上述实施例对本发明进行了详细说明，本领域的普通技术人员应当理解：依然可以对本发明进行修改或者等同替换，而不脱离本发明的精神和范围的任何修改或局部替换，其均应涵盖在本发明的权利要求范围当中。Finally, it should be noted that the above embodiments are only used to illustrate and not limit the technical solutions of the present invention, although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: the present invention can still be modified Or an equivalent replacement, any modification or partial replacement without departing from the spirit and scope of the present invention shall fall within the scope of the claims of the present invention.
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| CN113296899A (en)* | 2021-06-04 | 2021-08-24 | 海光信息技术股份有限公司 | Transaction master machine, transaction slave machine and transaction processing method based on distributed system |
| CN113590512A (en)* | 2021-07-30 | 2021-11-02 | 眸芯科技（上海）有限公司 | Self-starting DMA device capable of directly connecting peripheral equipment and application |
| CN113986533A (en)* | 2021-10-15 | 2022-01-28 | 山东云海国创云计算装备产业创新中心有限公司 | A data transmission method, DMA controller and computer-readable storage medium |
| CN114741345A (en)* | 2022-04-24 | 2022-07-12 | 苏州雄立科技有限公司 | USB DMA data transmission device and method |
| CN114924855A (en)* | 2022-05-23 | 2022-08-19 | 中国电子科技集团公司第五十八研究所 | Method and device for realizing multi-core cooperative controller |
| CN115422101A (en)* | 2022-11-04 | 2022-12-02 | 山东云海国创云计算装备产业创新中心有限公司 | DMA driving system, method, equipment and readable storage medium |
| CN115563038A (en)* | 2022-10-24 | 2023-01-03 | 苏州雄立科技有限公司 | Data processing system, method and data processing equipment based on DMA controller |
| CN115827523A (en)* | 2022-12-06 | 2023-03-21 | 苏州盛科通信股份有限公司 | Method, device and electronic equipment for diagnosing abnormal operation of DMA controller |
| CN116303221A (en)* | 2023-05-22 | 2023-06-23 | 太初(无锡)电子科技有限公司 | Data transmission method of multi-core processor network-on-chip system |
| CN117009265A (en)* | 2023-09-28 | 2023-11-07 | 北京燧原智能科技有限公司 | Data processing device applied to system on chip |
- 2005
- 2005-07-21CNCN 200510027972patent/CN1713164A/enactivePending
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