CN1697172A - Chip Lead Frame Module - Google Patents
Chip Lead Frame ModuleDownload PDFInfo
- Publication number
- CN1697172A CN1697172ACN 200410044203CN200410044203ACN1697172ACN 1697172 ACN1697172 ACN 1697172ACN 200410044203CN200410044203CN 200410044203CN 200410044203 ACN200410044203 ACN 200410044203ACN 1697172 ACN1697172 ACN 1697172A
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- lead frame
- chip
- circuit board
- pins
- frame unit
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- 239000002184metalSubstances0.000claimsdescription11
- 238000006243chemical reactionMethods0.000claimsdescription7
- 230000001681protective effectEffects0.000claimsdescription4
- 230000005540biological transmissionEffects0.000claimsdescription3
- 238000004806packaging method and processMethods0.000claimsdescription3
- 238000003466weldingMethods0.000claimsdescription3
- 150000001875compoundsChemical class0.000claims1
- 238000007789sealingMethods0.000claims1
- 238000010586diagramMethods0.000description8
- 238000004519manufacturing processMethods0.000description6
- 239000010410layerSubstances0.000description5
- 230000000694effectsEffects0.000description3
- 230000006870functionEffects0.000description3
- 239000000565sealantSubstances0.000description3
- 239000000463materialSubstances0.000description2
- 238000000034methodMethods0.000description2
- 238000005476solderingMethods0.000description2
- 239000004020conductorSubstances0.000description1
- 230000005611electricityEffects0.000description1
- 238000005538encapsulationMethods0.000description1
- 239000011229interlayerSubstances0.000description1
- 230000008054signal transmissionEffects0.000description1
- 235000012431wafersNutrition0.000description1
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Classifications
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
Translated fromChinese技术领域technical field
本发明涉及一种晶片导线架模组，特别涉及一种可提供复数晶片直接连结共同讯号，并可独立与其它印刷电路板或挠性电路板等设备连结讯号的晶片导线架模组。The invention relates to a chip lead frame module, in particular to a chip lead frame module which can provide a plurality of chips to directly connect common signals and independently connect signals with other printed circuit boards or flexible circuit boards and other equipment.
背景技术Background technique
传统的特定功能电路板卡的组成，例如：暂存记忆体(RAM)、显示卡或主机板等，是于电路板焊接有复数电晶体及电子元件，利用电晶体及电子元件的讯号连结，以达成逻辑运算或记忆存取等功能；但是，习知数电晶体间讯号传输的技术，是使电晶体的复数接脚均需独立透过电路板接通，因此，电路板必须对应电晶体复数电性接脚，而在板面及夹层设置复杂的印刷电路及焊接点，从而导致制造或设计的电路板布局规划困难，尤其在电路板空间有限，并需组接许多功能性电晶体时，往往被迫使用较贵的多层印刷电路板，不仅成本无法低廉，且扩充或实施电路板其它结构或功能性装置时，均受到空间局限。The composition of traditional specific function circuit boards, such as: temporary memory (RAM), display card or motherboard, etc., is soldered with a plurality of transistors and electronic components on the circuit board, using the signal connection of transistors and electronic components, To achieve functions such as logic operations or memory access; however, the conventional signal transmission technology between digital transistors requires that the multiple pins of the transistors need to be connected independently through the circuit board. Therefore, the circuit board must correspond to the transistors Multiple electrical pins, and complex printed circuits and soldering points are arranged on the board surface and the interlayer, which makes it difficult to plan the layout of the circuit board for manufacture or design, especially when the space of the circuit board is limited and many functional transistors need to be assembled. , often forced to use more expensive multi-layer printed circuit boards, not only the cost cannot be low, but also the expansion or implementation of other structural or functional devices of the circuit board is limited by space.
究上述电路板设计及制造的困难，是导因于电晶体的电性接脚均独立于电路板焊接的形态，即如图1、图2所示，是习见电晶体的导线架10结构及预定并排焊接于电路板的状态，各导线架10均有复数电性接脚101结构，藉此利用电性接脚101一端与功能性晶片20连接，而外端或底端则与电路板30构成焊接，由于此种结构形态设计，使电路板的布局规划或制造产生上述缺点。The difficulty in designing and manufacturing the above-mentioned circuit board is due to the fact that the electrical pins of the transistor are independent of the soldering form of the circuit board, that is, as shown in Figures 1 and 2, the lead frame 10 structure and In the state of being soldered on the circuit board side by side, each lead frame 10 has a plurality of electrical pins 101, so that one end of the electrical pins 101 is connected to the functional chip 20, and the outer or bottom end is connected to the circuit board 30. Composition welding, due to the design of this structural form, makes the layout planning or manufacturing of the circuit board produce the above-mentioned shortcomings.
发明内容Contents of the invention
本发明的目的是要解决上述习见的电路板布局规划不合理，致使成本高且扩充或实施电路板其它结构或功能性装置时空间受到局限的问题，而提供一种可克服上述缺点的晶片导线架模组。The purpose of the present invention is to solve the above-mentioned unreasonable circuit board layout planning, resulting in high cost and limited space when expanding or implementing other structures or functional devices of the circuit board, and to provide a chip wire that can overcome the above-mentioned shortcomings rack module.
本发明是由并排的复数导线架单元所组成，各导线架单元中间具有一镂空部，在镂空部侧边形成有间隔排列的复数接脚，各接脚具有第一导接端供与晶片连接，及第二导接端供与其它设备焊接；各导线架单元的选定接脚间设为直接相连结结构的共同电性接脚，其它接脚形成为不直接相连结而依赖电路板传输的独立电性接脚，藉此组成晶片共同讯号可由共同电性接脚通道连接，再传递于电路板，而独立讯号以独立电性接脚经由电路板通道，连接晶片导线架模组，以降低电路板如印刷电路板的使用层数及电路布局数量，使电路板体积轻薄且使用成本低廉，尤其能节约电路板空间，以达成易于规划实施其它功能性结构或设备的效果。The present invention is composed of a plurality of lead frame units arranged side by side, each lead frame unit has a hollow part in the middle, and a plurality of pins arranged at intervals are formed on the side of the hollow part, and each pin has a first lead terminal for connecting with the chip, And the second lead end is for welding with other equipment; the selected pins of each lead frame unit are set as common electrical pins with a direct connection structure, and other pins are formed as independent ones that are not directly connected but rely on circuit board transmission Electrical pins, so that the common signal of the chip can be connected by the common electrical pin channel, and then transmitted to the circuit board, and the independent signal is connected to the chip lead frame module through the circuit board channel through the independent electrical pin, so as to reduce the circuit The number of layers used and the number of circuit layouts of boards such as printed circuit boards make the boards light and thin and the cost of use is low. In particular, it can save the space of the boards, so as to achieve the effect of easy planning and implementation of other functional structures or equipment.
所述的导线架单元之共同电性接脚可为不直接相连接状，而是分别独立连接于一具有电性通道的转换介质，以转换介质构成共同电性连接，再传递于电路板，使独立电性接脚仍可直接与电路板连接，藉由该转换介质预先规划设置的共同通道，实现不需依靠电路板而连接的效果。The common electrical pins of the lead frame unit may not be directly connected, but are independently connected to a conversion medium with an electrical channel, and the conversion medium forms a common electrical connection, and then transmits it to the circuit board. The independent electrical pins can still be directly connected to the circuit board, and through the pre-planned and set common channel of the conversion medium, the effect of connecting without relying on the circuit board is realized.
所述的共同电性接脚可为在各导线架单元相邻部位处构成直接连通状；所述的共同电性接脚可为在各导线架单元周围选定侧设有连结架，以与选定的接脚连接而形成。The common electrical pins can form a direct connection at the adjacent parts of each lead frame unit; the common electrical pins can be provided with connecting frames on selected sides around each lead frame unit, to selected pins are connected.
所述的各导线架单元上面固着晶片，晶片与导线架单元的第一导接端实施金属导线连接，并于金属导线连接部位实施有局部封胶体的封装结构。Chips are fixed on each of the lead frame units, and the chip is connected to the first lead end of the lead frame unit by metal wires, and a partial encapsulation structure is implemented at the connecting parts of the metal wires.
所述的各导线架单元上面固着晶片，晶片与导线架单元的第一导接端实施金属导线连接，导线架单元与电路板一面或二面构成组装，利用一护盖分别或共同包覆住导线架单元及晶片，藉此组成制造成本低廉的电晶体形态。Chips are fixed on each of the lead frame units, and the chip is connected to the first lead end of the lead frame unit by metal wires. The lead frame unit is assembled with one or both sides of the circuit board, and is covered separately or jointly by a protective cover. The lead frame unit and the chip form a transistor form with low manufacturing cost.
附图说明Description of drawings
图1为习见电路板与电晶体组合的立体示意图。FIG. 1 is a three-dimensional schematic diagram of a conventional combination of a circuit board and a transistor.
图2为习见电晶体的导线架结构状态示意图。FIG. 2 is a schematic diagram of the state of the lead frame structure of a conventional transistor.
图3为本发明导线架单元间共同电性接脚结构的示意图。FIG. 3 is a schematic diagram of a common electrical pin structure between lead frame units of the present invention.
图4为本发明导线架单元间共同电性接脚结构的另一实施示意图。FIG. 4 is a schematic diagram of another implementation of the common electrical pin structure between the lead frame units of the present invention.
图5为本发明导线架单元边侧共同电性接脚结构的示意图。FIG. 5 is a schematic diagram of the common electrical pin structure on the sides of the lead frame unit of the present invention.
图6为本发明导线架单元边侧共同电性接脚结构的另一实施示意图。FIG. 6 is a schematic diagram of another implementation of the common electrical pin structure on the sides of the lead frame unit of the present invention.
图7为本发明打线部位局部封胶体的结构示意图。Fig. 7 is a schematic structural view of the partial sealant at the wire-bonding part of the present invention.
图8为本发明利用护盖保护晶片及导线架的结构示意图。FIG. 8 is a schematic diagram of the structure of the present invention using a protective cover to protect the chip and the lead frame.
图9为本发明共同电性接脚利用转换介质实现的实施例示意图。FIG. 9 is a schematic diagram of an embodiment of the present invention in which the common electrical pin is realized by using a conversion medium.
具体实施方式Detailed ways
请参阅各附图所示，本发明为一种可供复数晶片2置放组装的金属导体(花架)，其是由数个并排的导线架单元1所构成，其中，导线架单元1为中间具有一镂空部11，该镂空部11二侧边或四侧边形成有间隔排列状复数接脚12的结构形态，其中各接脚12具有第一导接端121与晶片2连接，及第二导接端122而焊接于电路板；但是，本发明是依晶片2或电路板的电路布局需求，而使各导线架单元1的选定接脚12间设有直接相连结结构的共同电性接脚A，并令各导线架单元1的接脚12具有不直接相连结而依赖外部电路板(例如印刷电路板或挠性电路板)传输电性的独立电性接脚B，藉此，即组成各导线架单元1可分别提供晶片2组装的导线架模组。See also shown in each accompanying drawing, the present invention is a kind of metal conductor (floor frame) that can be placed and assembled for a plurality of
如上所述，本发明各导线架单元1间的共同电性接脚A及分别所设的独立电性接脚B实施状态，可为在各导线架单元1相邻部位处构成有直接连通状的共同电性接脚A，及可与电路板焊接的独立电性接脚B，如图3、图4所示；也可为在所述各导线架单元1周围选定侧设有连结架13，以与选定的接脚12连接形成共同电性接脚A，并设有可与电路板焊接的独立电性接脚B，如图5、图6所示，藉此组成各晶片2共同讯号可先直接由共同电性接脚A连接，再传递于电路板等设备，而独立讯号则以独立电性接脚B经由电路板传递于晶片的导线架模组。As mentioned above, the implementation state of the common electrical pins A and the independent electrical pins B between the
利用导线架单元1间直接相连的共同电性接脚A及不相连的独立电性接脚B结构设计，可使各晶片2共同讯号先直接由共同电性接脚A连接，再传递于电路板等设备而降低使用经过电路板传递的通道(电路板印刷电路)，而各晶片2的独立讯号仍直接由独立电性接脚B与电路板连接，由此可见，本发明可达成电路板的电路布局容易且空间充裕的效果，以及可减少多层电路板如多层印刷电路板的层数，而获得电路板整体结构轻薄的效益，尤其因本发明之导线架模组结构可降低电路板通道的使用量，自可将节约的电路板空间用来实施其它功能的电晶体或结构，而使规划设计更臻容易且降低成本。Utilizing the structural design of the common electrical pin A directly connected between the
但是，本发明的实施并不以上述形态为限，如图9所示，也可令各导线架单元1的共同电性接脚A呈不直接相连状，而是分别连接于一具有电性通道的转换介质7，例如软性薄板，以该转换介质7构成共同电性连接作用，再传递于电路板6等设备，藉此使共同电性接脚A也达成不需依赖外部电路板传输，而独立电性接脚B仍直接与电路板6连接的相同的功效。However, the implementation of the present invention is not limited to the above-mentioned forms. As shown in FIG. The conversion medium 7 of the channel, such as a flexible thin plate, forms a common electrical connection with the conversion medium 7, and then transmits it to the
另外，本发明可供复数晶片2分别固着于导线架单元1上，藉此使晶片2与导线架单元1的第一导接端121直接导接，或进一步选定第一导接端121与晶片2实施金属导线3连接结构即所说的打线，藉此即可选定晶片2与导线架单元1的打线部位(金属导线3连接部位)实施有局部封胶体4的封装结构，如图7所示，以保护各金属导线3打线部位的稳定性，并免除习知的晶片周围整体封装结构，以降低制造及材料使用成本；也可在导线架模组与晶片2组装完成后，而未实施该局部封胶体4结构形态，将导线架模组与电路板6的一面或二面构成组装，藉此应用一护盖5分别或共同包覆住导线架单元1，如图8所示，藉此组成可保护导线架模组、晶片2及金属导线3打线部位的结构，以免除习知晶片分别于周围整体封装的制程，以降低制造及材料使用成本。In addition, the present invention can provide a plurality of
Claims (6)
Translated fromChinesePriority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410044203CN1697172A (en) | 2004-05-12 | 2004-05-12 | Chip Lead Frame Module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410044203CN1697172A (en) | 2004-05-12 | 2004-05-12 | Chip Lead Frame Module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1697172Atrue CN1697172A (en) | 2005-11-16 |
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ID=35349792
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200410044203PendingCN1697172A (en) | 2004-05-12 | 2004-05-12 | Chip Lead Frame Module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1697172A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101207972B (en)* | 2006-12-22 | 2010-05-19 | 鸿富锦精密工业（深圳）有限公司 | A circuit board and photosensitive device using the same |
| CN103187381A (en)* | 2011-12-30 | 2013-07-03 | 联咏科技股份有限公司 | Lead frame packaging structure |
- 2004
- 2004-05-12CNCN 200410044203patent/CN1697172A/enactivePending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101207972B (en)* | 2006-12-22 | 2010-05-19 | 鸿富锦精密工业（深圳）有限公司 | A circuit board and photosensitive device using the same |
| CN103187381A (en)* | 2011-12-30 | 2013-07-03 | 联咏科技股份有限公司 | Lead frame packaging structure |
| CN103187381B (en)* | 2011-12-30 | 2015-09-16 | 联咏科技股份有限公司 | Lead frame encapsulation structure |
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