CN1655362A - Dielectric layer for semiconductor device and manufacturing method thereof - Google Patents
Dielectric layer for semiconductor device and manufacturing method thereofDownload PDFInfo
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- CN1655362A CN1655362ACN200510006411.2ACN200510006411ACN1655362ACN 1655362 ACN1655362 ACN 1655362ACN 200510006411 ACN200510006411 ACN 200510006411ACN 1655362 ACN1655362 ACN 1655362A
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Abstract
Translated fromChineseDescription
Technical field
This invention relates generally to field of semiconductor devices, and more specifically, relate to the multilayer dielectric medium structure, use the semiconductor device and the manufacture method thereof of this multilayer dielectric medium structure.
Background technology
Along with the generation of metal-oxide semiconductor (MOS) (MOS) integrated circuit (IC) each time, size of devices is successively decreased constantly, so that high density and high performance device to be provided.Particularly, owing to the reduction of the drive current in MOS field-effect transistor (FET) along with the thickness of gate-dielectric increases, the thickness of gate-dielectric becomes as much as possible little.Like this, in order to improve the performance of device, provide as thin as a wafer, gate-dielectric reliable and low defective become already and become more and more important.
In decades, thermal oxide layer, for example silicon dioxide (SiO2), be used as gate-dielectric always because the silicon dioxide thermal oxide layer be used as at the bottom of the underlying silicon substrate be stable and manufacture craft quite simple.
Yet, because silicon dioxide has low-k (k), for example 3.9, the thickness that further reduces silicon dioxide gate dielectric has become more and more difficult.For example, if the thickness of silicon dioxide gate dielectric less than 40 dusts, direct Tunneling (direct tunneling) may take place.As a result, the grid-channel leakage stream (gate-to-channel leakagecurrent) that passes thin silicon dioxide gate dielectric increases, and causes undesirable power dissipation concerns.
But these problems cause considering to be made into than thick other the alternative dielectric substances that still can produce the thicker layer of identical or more performance of silicon dioxide.This performance can be expressed as " equivalent oxide thickness (EOT) ".
In order to improve the device performance of dielectric substance, done a lot of the trial.For example, United States Patent (USP) the 6th, 020 discloses a kind of oxynitride that is arranged between silicon base and the high-k dielectric floor No. 024.United States Patent (USP) the 6th, 013 discloses a kind of zirconium oxynitride floor or the oxynitriding hafnium layer that is used as gate-dielectric No. 553.In addition, the pct international patent application discloses WO and discloses silicon dioxide and oxynitride boundary layer for No. 00/01008.Also have, United States Patent (USP) the 6th, 020 discloses a kind of silicon oxynitride zirconium (zirconium silicon-oxynitride) or hafnium silicon oxynitride (hafniumsilicon-oxynitride) gate-dielectric of high-k No. 243.
Yet these attempt not solving the problem relevant with traditional dielectric substance.For example, silicon nitride layer between high-k dielectric layer and silicon base or the polysilicon gate or silicon oxynitride layer cause the electric charge capture of high interface state density, thereby have reduced channel mobility and reduced device performance.In addition, the formation of silicon nitride layer or silicon oxynitride layer needs sizable heat budget (heat budget).
Therefore, still keeping demand, so that the equivalent oxide thickness for example by reducing dielectric layer and improve interface performance and improve device performance to improved dielectric layer structure and manufacture method.
Summary of the invention
In one embodiment, a kind of semiconductor device comprises that a silicate boundary layer and covers the high-k dielectric layer on this silicate boundary layer.This high-k dielectric layer comprises metal alloy oxide.
Description of drawings
Fig. 1 is the profile of explanation semiconductor device according to an embodiment of the invention.
Fig. 2 is the profile that semiconductor device according to another embodiment of the invention is described.
Fig. 3 is the profile that semiconductor device according to still another embodiment of the invention is described.
Fig. 4 explanation is used for one embodiment of the present of invention of MOS transistor.
Fig. 5 explanation is used for one embodiment of the present of invention of nonvolatile memory.
Fig. 6 explanation is used for one embodiment of the present of invention of capacitor.
Fig. 7 is the structural analysis that illustrates the structure of utilizing an embodiment formation of being discussed with reference to figure 4.
Embodiment
The invention provides a kind of stable (noble) dielectric layer structure and manufacture method thereof.In the following description, many concrete details have been set forth, to provide to comprehensive understanding of the present invention.But those skilled in the art should be appreciated that the present invention does not utilize these details still can implement.In some example, known processing step, device architecture and technology no longer are shown specifically, to avoid making indigestion of the present invention.
With reference to figure 1, according to one embodiment of present invention, thesilicate boundary layer 12 that is formed by silicate material can be arranged on the conductive layer or the semiconductor-basedend 10, for example on the silicon base.The dielectric constant ofsilicate boundary layer 12 is preferably greater than any among silica, silicon nitride or the silicon oxynitride.Preferably,silicate boundary layer 12 has the thickness of about 5-50 dust.More preferably,silicate boundary layer 12 has the thickness (EOT of 2-4 dust) of about 5-10 dust.Silicate boundary layer 12 is preferably by chemical formula M1-XSixO2The metal metasilicate salt material of expression constitutes.Here, metal " M " can be hafnium (Hf), zirconium (Zr), tantalum (Ta) titanium (Ti), yttrium (Y), lanthanum (La) and aluminium (Al).Yet this catalogue is not exhaustive or does not limit the present invention.Within design of the present invention and scope, can also use any other metal suitable of the present invention.
According to an aspect of the present invention, metal metasilicate salt material (M1-XSixO2) demonstrate in the optimum value of value " 1-x " more than or equal to about 0.1 o'clock dielectric constant.Preferably, value " 1-x " is not more than about 0.5 more preferably, and value " 1-x " is from about 0.2 to about 0.4.
In addition, high-k dielectric layer 14 is set on thesilicate boundary layer 12, to form multilayer dielectric medium structure 15.The dielectric constant of high-k dielectric layer 14 is greater than SiO2Dielectric constant.Preferably, the dielectric constant of high-k dielectric layer 14 is greater than the dielectric constant of silicate boundary layer 12.And, the high-k dielectric layer preferably have splendid and the coherence of followingsilicate boundary layer 12 and not with covered structure, for example gate electrode or the reaction of control grid.
In the present invention,silicate boundary layer 12 has improved interface performance in fact.This is becausesilicate boundary layer 12 has stoped at the high-k dielectric layer 14 for example and the following semiconductor-basedend 10 in fact or high-k dielectric layer and be used to form reaction between the bottom electrode of capacitor.In addition, becausesilicate boundary layer 12 has the formation energy more passive than silicon dioxide,, thereby help to form reliable semiconductor device so it has chemical stability on silicon base.Therefore, compare with the method for prior art, the present invention has reduced the interface bulk trap densities and has had the interfacial characteristics that has improved in fact.
Further, because metalsilicate boundary layer 12 has and is approximately 10 to 12 quite high dielectric constant, so compare with the method for prior art, EOT can be held or reduce.
In addition, even it is believed that in follow-up heat treatment process under 900 ℃ high temperature, metalsilicate boundary layer 12 also can keep non-crystal state basically.Therefore, in metalsilicate boundary layer 12, produce crystal boundary hardly, thereby reduced Leakage Current.
Now, turn around with reference to high-k dielectric layer 14, it comprises metal alloy oxide again.The metal alloy oxide of high-k dielectric layer 14 preferably includes at least two kinds of metallic elements of diffusion mutually.The metal alloy oxide of high-k dielectric layer 14 can be the mixture of at least two kinds of metal oxides.More preferably, at least two kinds of metallic elements evenly mix, and the most preferably, are the mixing of atomic level.Yet according to application, these at least two kinds of metallic elements cannot evenly mix, but are mixed to the effect that is enough to play electrolyte in design of the present invention and scope.
According to an aspect of the present invention, at least two kinds of metal oxides that form high-k dielectric layer 14 can be chosen as has minimum clean fixed charge in high-k dielectric layer 14, promptly near zero.About this point, this metal oxide can include, but are not limited to, hafnium oxide, zirconia, tantalum oxide, aluminium oxide, titanium oxide, yittrium oxide, strontium oxide strontia, scandium oxide, lanthana or barium monoxide.
What on the other hand, metal alloy oxide referred to can be hafnium-oxidized aluminum alloy thing, zirconium-oxidized aluminum alloy thing, tantalum-oxidized aluminum alloy thing, Ti-Al alloy oxide, yttrium-oxidized aluminum alloy thing or hafnium-zirconium-oxidized aluminum alloy thing.Yet this catalogue is not exhaustive or restriction the present invention.Within design of the present invention and scope, can also use any other metal alloy oxide suitable of the present invention.Those skilled in the art will understand, and metal-oxidized aluminum alloy thing can be expressed as metal-aluminate, for example hafnium (HfAlO).
The high-k dielectric layer 14 that comprises metal alloy oxide can have the dielectric constant bigger than the dielectric constant ofsilicate boundary layer 12.
In addition, this metal alloy oxide can be by chemical formula AyB1-yOz(0＜y＜1) expression.Preferably, A is identical with M discussed above or come from identical periodic group.In other words, preferably the metal with metal alloy oxide (high-k dielectric layer 14) is identical for the metal of silicate boundary layer 12.For example, if multilayerdielectric medium structure 15 comprises hafniumsilicate boundary layer 12, high-k dielectric layer 14 can comprise hafnium-oxidized aluminum alloy thing layer, i.e. mixture of hafnium oxide and aluminium oxide so.In addition, ifsilicate boundary layer 12 comprises zirconiumsilicate boundary layer 12, high-k dielectric layer 14 comprises zirconium-oxidized aluminum alloy thing layer, i.e. mixture of zirconia and aluminium oxide so.As a result, device property improves.For example, because the electric coherence between the high-k dielectric layer 14 ofsilicate boundary layer 12 and covering, interfacial characteristics improves.
More preferably, A and M are IV family metals, and B is the III-th family metal.For example, A is zirconium or hafnium, and B is an aluminium.
According to an aspect, " y " can be for about 0.5 to about 0.9, to have high-k and high crystallization temperature.
According on the other hand, the ratio of components of A and B is between about 1: 1 and about 5: 1.This is because the content of A is high more, and dielectric constant is high more, but crystallization temperature is low more, and this causes the increase of Leakage Current.In ideal conditions, high-k dielectric layer 14 has amorphous crystal structure substantially, to reduce from the Leakage Current that wherein passes through.More preferably, because the clean fixed charge of formed high-k dielectric layer 14 can approach zero, so the ratio of components of A and B is about 2: 1.In this case, preferably hafnium or zirconium, and B is preferably aluminium.High-k dielectric layer 14 can have the thickness that is approximately the 2-60 dust.Here, 2 dusts are the basic thickness of an atomic layer, and 60 dusts are illustrated in the upper thickness limit that prevents explosion (popping) in subsequently annealing (annealing) process.Just as known in the art, captive hydroxyl can explosion in annealing process subsequently in dielectric layer in the process that forms, thereby damages dielectric layer, promptly stays next hole in dielectric layer.If such explosion phenomenon takes place, can suppress processing step subsequently significantly, for example the deposition of grid polycrystalline silicon (gate poly deposition).
Fig. 2 explanation is used to make the above-described method that is used for the multilayerdielectric medium structure 15 of semiconductor device.The details of manufacturing step is if traditional or because it is clear and simply and as everyone knows then omitted.
As discussed above like that,silicate boundary layer 12 can be formed on conductive layer or at the semiconductor-based end 10.Metalsilicate boundary layer 12 is preferably formed by the material of being discussed with reference to figure 1.More preferably, metalsilicate boundary layer 12 can use the ALD technology to form.Like this, compared with the method for the big thermally equilibrated prior art of needs, by means of the present invention, the low-heat balancing processing is possible.In addition, by using the ALD technology, can use more precursor of wide region (precursor) and film to form and have the thickness of tightly being controlled, and this is impossible by traditional chemical vapor deposition technology (CVD).
Particularly, as being known in the art, the ALD technology that is used to form metalsilicate boundary layer 12 can be undertaken by source metal, silicon source and oxygen source alternately and repeatedly being carried out pulse and purging (pulsing and purging) step.Under the situation of zirconiumsilicate boundary layer 12, can use ZrCl4As source metal.Equally, under the situation of hafnium silicate boundary layer, can use HfCl4As source metal.In addition, the silicon source comprises SiH4Or SiCl4H2Oxygen source can comprise H2O, ozone, oxygen radical, alcohol, for example IPA, D2O or H2O2In addition, within design of the present invention and scope, can use and be suitable for other precursor of the present invention.Typical precursor like this is shown in Table 1.
Table 1
| The Hf source | The Zr source | The Si source | |
| Halide (Halide) | HfCl4 | ZrCl4 | SiCl4 |
| Alkoxide (Alkoxide) | Hf(OC4H9)4Hf(OC2H5)4 | Zr(OC4H9)4 | Si(OC4H9)4Si(OCH3)4Si(OC2H5)4 |
| Acid amides (Amide) | Hf(N(C2H5)2)4Hf(N(CH3)2)4Hf(N(CH3C2H5))4 | Zr(N(C2H5)2)4Zr(N(CH3)2)4Zr(N(CH3C2H5))4 | Si(N(C2H5)2)4Si(N(CH3)2)4Si(N(CH3)2)3H HfCl2(hmds)2 |
| Alkoxyamine (Alkoxyamine) | Hf(dmae)4 | Zr(dmae)4 | Si(dmae)4 |
| ETC | SiH4，SiCl4H2， Si2Cl6 |
*Dmae (dimethylamine, dimethylamine)
*Hmds (hexamethyldisiloxane, hexamethyldisilazane)
Replacedly, if Organometallic Chemistry gas deposition technology (MOCVD) technology or reactive sputtering technology are providing the controlling level same with the ALD technology aspect thickness or the composition, metalsilicate boundary layer 12 also can use MOCVD or reactive sputtering technology to form.The MOCVD technology can be used for example Hf (O-Si-R3)4Or Zr (O-Si-R3)4(R=C2H5) precursor carry out.In addition, can use for example tert-butoxy hafnium, Zr source for example positive silane of tetraethoxy or tetraethoxy orthosilicate (TEOS) of tert-butoxy zirconium and Si source for example of Hf source.
Secondly, discuss with reference to figure 1 like that as above, the high-k dielectric layer 14 that formation is made of metal alloy oxide is to cover on the silicate boundary layer 12.According to an aspect, in the further details that forms high-k dielectric layer 14, theground floor 18 with first metallic element utilizes the ALD technology to form.Then, also utilizing the ALD technology to form the second layer 20 with second metallic element covers on the ground floor 18.First and second metallic elements can be a kind ofly can form oxide, for example hafnium oxide, zirconia, tantalum oxide, aluminium oxide, titanium oxide, yittrium oxide, strontium oxide strontia, scandium oxide, lanthana or barytic metal.
On the other hand, ifsilicate boundary layer 12 is formed by zirconium silicate, the high-k dielectric layer 14 of covering is preferably by stacked ZrO alternately2Layer and Al2O3Layer and in addition follow-up heat treatment, this will be described further below.In this situation, because the metal ofsilicate boundary layer 12 is identical with metal in being included in metal alloy oxide layer (high-k dielectric layer 14), so such as mentioned above, interfacial characteristics is owing to the electric coherence between the high-k dielectric layer 14 ofsilicate boundary layer 12 and covering can improve.Equally, ifsilicate boundary layer 12 is formed by hafnium silicate, high-k dielectric layer 14 is preferably by stacked HfO alternately2Layer and Al2O3Layer and in addition follow-up heat treatment, this will be described further below.
More preferably,ground floor 18 has the first predetermined electric charge and the second layer 20 and has and second of the opposite charge of theground floor 18 predetermined electric charge.More preferably, the first predetermined electric charge is that the positive fixed charge and the second predetermined electric charge is the fixed charge of bearing.As mentioned above,ground floor 18 can be formed by hafnium oxide, zirconia, tantalum oxide, aluminium oxide, titanium oxide, yittrium oxide, strontium oxide strontia, scandium oxide, lanthana or barium monoxide, and the second layer 20 can be formed by aluminium oxide.
Therefore, according to an aspect of the present invention, the clean fixed charge of high-k dielectric layer 14 can be minimized.At this on the one hand, in the prior art, have the problem relevant with fixed charge, this causes reducing the Coulomb scattering (coulomb scattering) of channel mobility.Yet, by means of one aspect of the present invention, particularly when metal oxide evenly mixes with atomic level or spreads mutually in follow-up process for making, the fixed charge of bearing in the second layer 20 that is formed by the material of for example above-mentioned aluminium oxide by the positive fixed charge compensation of using in theground floor 18 that is formed by for example above-mentioned hafnium oxide or zirconic material can overcome the fixed charge problem of prior art.
The thickness of the second layer 20 is approximately half of thickness of ground floor 18.Ifground floor 18 is to be formed by for example hafnium oxide or zirconic material, and the second layer 20 forms by aluminium oxide, and then this is especially real, because the fixed charge amount in aluminium oxide is considered to approximately to many twice than hafnium oxide or zirconic fixed charge amount.For example,ground floor 18 can be formed up to the thickness of about 10 dusts, and the second layer 20 can be formed up to the thickness of about 5 dusts.
Subsequent the structure that is produced is annealed or heat treatment, shown in Figure 1 to form according to multilayer dielectricmedium structure 15 of the present invention.For example, annealing temperature can be greater than about 900 ℃, make theground floor 18 shown in Fig. 2 and the second layer 20 in conjunction with or mix, comprise the high-k dielectric layer 14 of the metallic element of at least two kinds of phase counterdiffusion with formation.Preferably, annealing temperature is about 950 ℃.More preferably, annealing temperature will be enough high, make that at least two kinds of metallic elements evenly mix with atomic level in high-k dielectric layer 14, form metal alloy oxide layer.
With reference to figure 3, according on the other hand, before heat treatment or annealing form multilayerdielectric medium structure 15 shown in Figure 1, on the structure that is produced, form the one or moreadditional ground floors 18 and the second layer 20.Other conductive layer 24 can be formed on the high-k dielectric layer 14, to form various semiconductor device.High-k dielectric layer 14 in addition, before annealing, the superiors 22 can be made of aluminium oxide, to improve the interface performance between high-k dielectric layer 14 and the conductive layer 24.
In another embodiment, high-k dielectric layer 14 can utilize the MOCVD technology to form.Preferably, supply with two kinds of metallic element sources simultaneously, comprise the high-k dielectric layer 14 of metal alloy oxide with formation.Replacedly, can use the reactive sputtering technology to form metal alloy oxide layer.The reactive sputtering technology is by will carrying out in oxygen injection technology chamber (process chamber) in metal deposition process.
Above-described the present invention can be used to form the MOS transistor of the following stated.In addition, the present invention can be used for any dielectric of semiconductor device equally, the dielectric layer of for example intergate dielectric layer of nonvolatile semiconductor memory member, or holding capacitor, and all these technical schemes all are included among design of the present invention and the scope.
Particularly, with reference to Figure 14,MOS transistor 41 comprises the semiconductor-basedend 100, is formed on thesilicate boundary layer 120a on thesubstrate 100 and is formed on thesilicate boundary layer 120a to form the high-kdielectric layer 120b of gate dielectric layer 120.Each ofsilicate boundary layer 120a and high-kdielectric layer 120b all is by forming in conjunction with the dielectric substance that Fig. 1 discussed.In addition,MOS transistor 41 can also comprise by forexample polysilicon layer 130a and silicide layer 130b constitute gate electrode 130 and with the gate electrode 130 adjacent source/drain regions that form.Gate electrode 130 can be formed by metal.Selectively, can formpartition 150 along the opposition side of gate electrode 130, to finishsemiconductor device 41 withchannel region 107.
With reference to figure 5, according to another embodiment, nonvolatile semiconductor memory member 51 comprises the semiconductor-based end 200, have the floating grid 210 of the gate insulator 209 in substrate of covering 200, be formed on the silicate boundary layer 220a on the floating grid 210 and be formed on the silicate boundary layer 220a to form the high-k dielectric layer 220b of intergate dielectric layer (intergate dielectric layer) 220.Silicate boundary layer 220a and high-k dielectric layer 220b each all by forming in conjunction with the dielectric substance that Fig. 1 discussed.In addition, control grid 230 covers on the intergate dielectric layer 220.As known in the prior art, control grid 230 can be made of polysilicon layer 230a and silicide layer 230b.Can be additionally formed other traditional structure, for example partition 250 and source/drain regions 206 are to finish the nonvolatile semiconductor memory member 51 with channel region 207.In this embodiment, only can be applied to intergate dielectric layer 220 or gate insulator 209 in conjunction with the multilayer dielectric medium structure that Fig. 1 discussed.Replacedly, the multilayer dielectric medium structure can be applied to intergate dielectric layer 220 and gate insulator 209 in the middle of both.
With reference to figure 6, according to another one embodiment, capacitor 61 comprises bottom electrode 310, is formed on the silicate boundary layer 320a on the bottom electrode 310 and is formed on silicate boundary layer 320a to form the high-k dielectric layer 320b of capacitor dielectric 320.Silicate boundary layer 320a and high-k dielectric layer 320b are by constituting in conjunction with the dielectric substance that Fig. 1 discussed.Capacitor 61 additionally comprises the top electrode 330 that covers on the capacitor dielectric 320.Capacitor 61 is electrically connected to the semiconductor-based end 300.
Should be noted that in design of the present invention and scope thesubstrate 10 shown in Fig. 1 to Fig. 6 can be semiconductor or conductor, for example the polysilicon of Can Zaing.In addition,substrate 10 also can be monocrystal silicon substrate or silicon-on-insulator (silicon on insulator, SOI) substrate.
Fig. 7 is the structural analysis that illustrates the structure of utilizing the embodiment formation of discussing with reference to figure 4, and wherein,silicate boundary layer 120a can be HfSiO2, and the high-k dielectric layer can have molecular formula Hf0.67Al0.23O1.67
With reference to figure 7,1. symbol represents the concentration of Si, and 2. symbol represents the concentration of Hf, and 3. symbol represents the concentration of Al.Preferably, Hf and Al have uniform concentration on whole high-k dielectric layer 120b.Silicate boundary layer 120a can comprise from the aluminium atom of high-kdielectric layer 120b diffusion, and high-kdielectric layer 120b can comprise from the silicon atom ofsilicate boundary layer 120a diffusion.
In addition, insilicate boundary layer 120a, the concentration of Al reduces towards the upper surface of high-kdielectric layer 120b from the upper surface of silicate boundary layer 120a.And the concentration of Si reduces from the upper surface of thesilicate boundary layer 120a upper surface towards high-kdielectric layer 120b.
In addition, by molecular formula AyBI-yOzThe value of y can reduce by the upper surface from the interface between the basal surface ofsilicate boundary layer 120a and high-kdielectric layer 120b towards high-kdielectric layer 120b among the high-kdielectric layer 120b that expresses.The concentration of A has a gradient along the thickness direction of high-k dielectric layer 120b.In addition, the concentration of B can be inversely proportional to the concentration of A among high-k dielectric layer 120b.In other words, the value of y can change with the height of gate dielectric layer 120.If A is identical with the metal M ofsilicate boundary layer 120a, and B comprises the material that has chemical stability for the coated electrode structure such as gate electrode, control grid or electric capacity top electrode, then especially like this.Therefore, by means of these embodiment of the present invention, can form reliable semiconductor device structure.
According to a further aspect in the invention, 2. and 3. some functions of the height by depending on gate dielectric layer 120 can be divided into the concentration in the Q part stepped (can be stepped) or change.
At last, owing to adopted these embodiment of the present invention, dielectric layer structure with prior art, for example adopt the dielectric layer of silicon nitride or silicon oxynitride boundary layer or do not have the silicate body layer (a silicate bulk layer) of boundary layer, compare, interface performance can improve and can keep or reduce EOT.In other words, by with its dielectric constant greater than any onesilicate boundary layer 12 and high-k dielectric layer 14 combination in silica, silicon nitride or the silicon oxynitride, the low EOT that can realize having improved interface performance.
Below already with the formal description of a preferred embodiment of the present invention and illustrated principle of the present invention, obviously, the present invention can be improved on layout and details and can not be broken away from these principles.We are claimed to come from the design of appended claims and all improvement and the variation of scope.
Claims (60)
1. sandwich construction that is used for semiconductor device comprises:
One silicate boundary layer; With
One high-k dielectric layer is positioned on the described silicate boundary layer, and described high-k dielectric layer comprises metal alloy oxide.
2. sandwich construction according to claim 1, wherein said metal alloy oxide comprises the metallic element of at least two kinds of phase counterdiffusion.
3. sandwich construction according to claim 1, wherein said at least two kinds of metallic elements evenly mix with atomic level.
4. sandwich construction according to claim 1, wherein said metal alloy oxide comprises the mixture of at least two kinds of different metal oxides.
5. sandwich construction according to claim 4, the selected minimum clean fixed charge of wherein said metal oxide with described high-k dielectric layer.
6. sandwich construction according to claim 4, wherein said metal oxide comprises hafnium oxide, zirconia, tantalum oxide, aluminium oxide, titanium oxide, yittrium oxide, strontium oxide strontia, scandium oxide, lanthana or barium monoxide.
7. sandwich construction according to claim 1, wherein said metal alloy oxide comprise hafnium-oxidized aluminum alloy thing, zirconium-oxidized aluminum alloy thing, tantalum-oxidized aluminum alloy thing, Ti-Al alloy oxide, yttrium-oxidized aluminum alloy thing or hafnium-zirconium-oxidized aluminum alloy thing.
8. sandwich construction according to claim 1, wherein said high-k dielectric layer have a dielectric constant bigger than the dielectric constant of described silicate boundary layer.
9. sandwich construction according to claim 1, wherein said silicate boundary layer have any one the big dielectric constant of dielectric constant in a ratio silicon oxide, silicon nitride or the silicon oxynitride.
10. sandwich construction according to claim 1, wherein said silicate boundary layer has a thickness of about 5-50 dust.
11. sandwich construction according to claim 10, wherein said silicate boundary layer has a thickness of about 5-10 dust.
12. sandwich construction according to claim 1, wherein said silicate boundary layer is by chemical formula M1-XSixO2The metal metasilicate salt material of expression forms.
13. sandwich construction according to claim 12, wherein said metal " M " are selected from the group that is made of hafnium (Hf), zirconium (Zr), tantalum (Ta) titanium (Ti), yttrium (Y), lanthanum (La) and aluminium (Al).
14. sandwich construction according to claim 12, wherein 1-x is more than or equal to about 0.1.
15. sandwich construction according to claim 12, wherein 1-x is not more than about 0.5.
16. sandwich construction according to claim 12, wherein 1-x is about 0.2 to about 0.4.
17. sandwich construction according to claim 13, wherein said metal alloy oxide is by chemical formula AyB1-yOzExpression, and 0＜y＜1 wherein.
18. sandwich construction according to claim 17, wherein A is identical with M or come from identical periodic group.
19. sandwich construction according to claim 17, wherein A and M are IV family metals, and B is the III-th family metal.
20. sandwich construction according to claim 17, wherein A is zirconium or hafnium, and B is an aluminium.
21. sandwich construction according to claim 17, wherein y is about 0.5 to about 0.9.
22. sandwich construction according to claim 17, wherein the ratio of components of A and B is between about 1: 1 and about 5: 1.
23. sandwich construction according to claim 22, the ratio of components of wherein said A and B are about 2: 1.
24. sandwich construction according to claim 23, wherein A is hafnium or zirconium, and B is an aluminium.
25. sandwich construction according to claim 23, wherein said silicate boundary layer comprises the aluminium atom that diffuses out from described high-k dielectric layer.
26. sandwich construction according to claim 17, the upper surface of wherein said y value from the interface between the basal surface of described silicate boundary layer and described high-k dielectric layer towards described high-k dielectric layer reduces, and the concentration of wherein said A has along a gradient of the thickness direction of described high-k dielectric layer.
27. sandwich construction according to claim 17, wherein among described high-k dielectric layer, the concentration of described B and the concentration of described A are inversely proportional to.
28. sandwich construction according to claim 17, wherein said high-k dielectric layer comprises the silicon atom that diffuses out from described silicate boundary layer.
29. sandwich construction according to claim 1, wherein said high-k dielectric layer has amorphous substantially crystal structure.
30. sandwich construction according to claim 1, wherein said high-k dielectric layer forms the thickness of about 2-60 dust.
31. a method that is formed for the sandwich construction of semiconductor device may further comprise the steps:
Form a silicate boundary layer; And
Formation is positioned at the high-k dielectric layer on the described silicate boundary layer, and described high-k dielectric layer comprises metal alloy oxide.
32. method according to claim 31, the step of wherein said formation high-k dielectric layer comprises:
Form ground floor with first metallic element by the ALD method;
Have second metallic element, be positioned at the second layer on the described ground floor by the formation of ALD method; And
The structure that is produced is annealed under the temperature that allows the described first and second metallic element phase counterdiffusion.
33. method according to claim 32, wherein said annealing temperature is greater than about 900 ℃.
34. method according to claim 32, wherein said ground floor has first predetermined charge, and the described second layer has second predetermined charge opposite with the predetermined charge of described ground floor.
35. method according to claim 34, wherein said first predetermined charge is a positive fixed charge, and described second predetermined charge is a negative fixed charge.
36. method according to claim 32 wherein before described annealing, also comprises forming one or more additional first and second layers.
37. method according to claim 36, the wherein said the superiors comprise aluminium oxide.
38. method according to claim 32, the thickness of the wherein said second layer approximately are half of thickness of described ground floor.
39. according to the described method of claim 38, wherein said ground floor forms the thickness of about 10 dusts, and the described second layer forms the thickness of about 5 dusts.
40. method according to claim 32, wherein said ground floor is formed by hafnium oxide, zirconia, tantalum oxide, aluminium oxide, titanium oxide, yittrium oxide, strontium oxide strontia, scandium oxide, lanthana or barium monoxide, and the described second layer is formed by aluminium oxide.
41. method according to claim 31, wherein said silicate boundary layer is by chemical formula M1-XSixO2The metal metasilicate salt material of expression forms.
42. according to the described method of claim 41, wherein said 1-x is about 0.1 to about 0.5, and wherein said " M " is selected from the group that comprises hafnium (Hf), zirconium (Zr), tantalum (Ta) titanium (Ti), yttrium (Y), lanthanum (La) and aluminium (Al).
43. according to the described method of claim 42, wherein said 1-x is about 0.2 to 0.4.
44. method according to claim 31, the step of the described silicate boundary layer of wherein said formation is undertaken by ALD technology, MOCVD technology or reactive sputtering technology.
45. method according to claim 31, wherein said high-k dielectric layer has the metallic element of at least two kinds of phase counterdiffusion, the step of the described high-k dielectric layer of wherein said formation is undertaken by MOCVD technology or reactive sputtering technology, and wherein supply with described two kinds of metallic element sources simultaneously, to form described high-k dielectric layer.
46. method according to claim 31, wherein said metal alloy oxide comprise the different metal element of at least two kinds of phase counterdiffusion.
47. according to the described method of claim 46, the metallic element of wherein said at least two kinds of phase counterdiffusion evenly mixes with atomic level.
48. method according to claim 31, wherein said high-k dielectric layer has the dielectric constant bigger than the dielectric constant of described silicate boundary layer.
49. method according to claim 31, the thickness of wherein said high-k dielectric layer is in the scope of about 2-60 dust.
50. pass through a kind of semiconductor device that the method for claim 32 forms.
51. pass through a kind of semiconductor device that the method for claim 45 forms.
52. a semiconductor device comprises:
One substrate;
One silicate boundary layer is formed on the described substrate;
One high-k dielectric layer is formed on the described silicate boundary layer, and described high-k dielectric layer comprises metal alloy oxide;
One gate electrode; And
Source, contiguous described gate electrode forms.
53. according to the described semiconductor device of claim 52, wherein said high-k dielectric layer has the dielectric constant bigger than the dielectric constant of described silicate boundary layer.
54. according to the described semiconductor device of claim 53, wherein said gate electrode is formed by metal or polysilicon.
55. a nonvolatile memory comprises:
One substrate;
One gate insulator;
One floating grid is positioned in the described substrate;
One silicate boundary layer is formed on the described floating grid;
One high-k dielectric layer is formed on the described silicate boundary layer, and described high-k dielectric layer comprises metal alloy oxide; And
One control grid is positioned on the described high-k dielectric layer.
56. according to the described nonvolatile memory of claim 55, wherein said high-k dielectric layer has a dielectric constant bigger than the dielectric constant of described silicate boundary layer.
57. according to the described nonvolatile memory of claim 55, wherein said gate insulator comprises an additional silicon hydrochlorate boundary layer and is formed on the additional high-k dielectric layer of one on the described additional silicon hydrochlorate boundary layer that described high-k dielectric layer comprises metal alloy oxide.
58. a nonvolatile memory comprises:
One substrate;
One silicate boundary layer is formed on the described substrate;
One high-k dielectric layer is formed on the described silicate boundary layer, and described high-k dielectric layer comprises metal alloy oxide;
One floating grid is positioned in the described substrate;
One intergate dielectric layer; And
One control grid is positioned on the described intergate dielectric layer.
59. a capacitor that is used for semiconductor device comprises:
One bottom electrode;
One silicate boundary layer is formed on the described bottom electrode;
One high-k dielectric layer is formed on the described silicate boundary layer, and described high-k dielectric layer comprises metal alloy oxide; And
One top electrode.
60. according to the described capacitor of claim 59, wherein said high-k dielectric layer has the dielectric constant bigger than the dielectric constant of described silicate boundary layer.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR5817/2004 | 2004-01-29 | ||
| KR5817/04 | 2004-01-29 | ||
| KR1020040005817AKR100678626B1 (en) | 2004-01-29 | 2004-01-29 | Multilayer dielectric film of microelectronic device and manufacturing method thereof |
| US11/027,256 | 2004-12-30 | ||
| US11/027,256US7371633B2 (en) | 2001-02-02 | 2004-12-30 | Dielectric layer for semiconductor device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1655362Atrue CN1655362A (en) | 2005-08-17 |
| CN100474613C CN100474613C (en) | 2009-04-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100064112AExpired - LifetimeCN100474613C (en) | 2004-01-29 | 2005-01-31 | Dielectric layer for semiconductor device and method for manufacturing the same |
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| Country | Link |
|---|---|
| JP (1) | JP4722501B2 (en) |
| CN (1) | CN100474613C (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN100474613C (en) | 2009-04-01 |
| JP2005217409A (en) | 2005-08-11 |
| JP4722501B2 (en) | 2011-07-13 |
| TWI282128B (en) | 2007-06-01 |
| TW200537621A (en) | 2005-11-16 |
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