CN1536620A - Low-temperature polycrystalline silicon thin film transistor and manufacturing method of polycrystalline silicon layer thereof - Google Patents
Low-temperature polycrystalline silicon thin film transistor and manufacturing method of polycrystalline silicon layer thereofDownload PDFInfo
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- CN1536620A CN1536620ACNA031094856ACN03109485ACN1536620ACN 1536620 ACN1536620 ACN 1536620ACN A031094856 ACNA031094856 ACN A031094856ACN 03109485 ACN03109485 ACN 03109485ACN 1536620 ACN1536620 ACN 1536620A
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Abstract
Description
Technical field
The invention relates to a kind of low temperature polycrystalline silicon (low temperature poly-Si, be called for short LTPS) thin-film transistor (thin film transistor, be called for short TFT) manufacture method, and particularly about the manufacture method of polysilicon layer in a kind of low-temperature polysilicon film transistor.
Background technology
Along with high-tech development, video product, particularly digitized video or device for image become in general daily life common product.In these digitized videos or the device for image, display is a significant components, to show relevant information.The user can read information by display, or and then the running of control device.
And thin-film transistor (TFT) can be applicable to LCD (liquid crystal display, abbreviation LCD) driven unit, make this product become a main flow of last straight formula type flat-panel screens, become following dominance product in markets such as personal computer, game machine, monitors.At present, because of amorphous silicon (amorphous silicon claims a-Si again) thin-film transistor, can therefore be widely used in the low-temperature epitaxy of 200-300 degree Celsius.But (electron mobility) is low for the electron mobility of amorphous silicon, be no more than 1cm2/V.s, make amorphous silicon film transistor not apply present high-speed assembly demands of applications, and polysilicon (polycrystalline silicon, claiming ploy-Si again) thin-film transistor has higher mobility (approximately than the high 2-3 of an amorphous silicon order of magnitude) and low-temperature sensitive (low temperature sensitivity) compared to amorphous silicon film transistor, makes it more be applicable to high-speed assembly.Yet when the amorphous silicon of annealing in a conventional manner formed polysilicon, its formation temperature needed more than 600 degree Celsius, so general use quartzy (quartz) is as substrate.Because the quartz base plate cost is expensive more many than glass substrate, and under the restriction of substrate size, panel approximately only has at 2 to 3 o'clock, therefore can only develop small panel in the past.
Must use glass substrate in order to reduce cost at present, so the formation temperature of polysilicon is reduced to below 500 degree Celsius.Therefore, the method of the formation temperature of many reduction polysilicons is used one after another, wherein with quasi-molecule laser annealing technology (excimer laser annealing, be called for short ELA) and crystallization inducing metal technology (metal induced crystallization, be called for short MIC) attract attention, but because the equal polysilicon of growing high quality, pollution-free and fabricating low-defect-density (lowdefect density) of aforementioned technology, the polycrystalline SiTFT made from aforementioned low temperature process is called " low-temperature polysilicon film transistor " again.Moreover, because the electron mobility height of polysilicon itself, so common when carrying out the technology of thin-film transistor array, can make peripheral circuit in the periphery circuit region of periphery, viewing area in the lump.
And the crystallization mode of crystallization inducing metal technology is based on lateral growth (lateral growth), it is after amorphous silicon layer forms preceding or forms, and forms a metal level, in order to promote the crystallization of amorphous silicon layer, and after metal level forms, carry out low temperature annealing process, to form polysilicon.And the metal level that uses in the crystallization inducing metal technology not only can promote recrystallized amorphous silicon, the more important thing is in order to form metal silicide.And main mode is the relation between its horizontal growth direction of control and the source electrode-passage-drain electrode bearing of trend, if two directions vertically then are applicable to pixel region, if parallel peripheral circuit (peripheral circuit) district that then is applicable to of two directions.But, the shortcoming of crystallization inducing metal technology is that the polysilicon layer defective (defect) that is grown up to is too many, need add technology behind one high temperature again, as rapid hot technics (rapid thermal process) or laser annealing technique, so many at present based on quasi-molecule laser annealing technology.
But, be example with known active matrix liquid crystal display, the low-temperature polysilicon film transistor in its peripheral circuit need have the electric current (on-state current) of higher electron mobility and opening; Viewing area (pixel area) then must possess the requirement of low-leakage current; And can't meet this two requirement simultaneously with the formed polysilicon of quasi-molecule laser annealing technology at present.
Summary of the invention
Therefore, the purpose of this invention is to provide the manufacture method of a kind of low-temperature polysilicon film transistor and polysilicon layer thereof, to form little grained polysilicon layer simultaneously in periphery circuit region formation macromeritic polysilicon layer and in the viewing area.
According to above-mentioned and other purpose, the present invention proposes a kind of manufacture method of polysilicon layer, comprises that panel comprises a viewing area and a periphery circuit region prior to forming an amorphous silicon layer on the panel.Then, on the portion of amorphous silicon layer of periphery circuit region, form a metal level, carry out a crystallization processes again, so that the amorphous silicon layer of periphery circuit region becomes a polysilicon layer.Subsequently, carry out an excimer laser annealing process, so that the polysilicon layer of periphery circuit region becomes the polysilicon layer of big crystal grain and makes the amorphous silicon layer of viewing area become a polysilicon layer, wherein the crystal grain of the polysilicon layer of periphery circuit region is greater than the crystal grain of the polysilicon layer of viewing area.
The present invention proposes a kind of manufacture method of low-temperature polysilicon film transistor in addition, is suitable for being formed on the panel, and wherein this panel comprises a viewing area and a periphery circuit region, and its step is included in and forms an amorphous silicon layer on the panel earlier.Then, utilize a crystallization inducing metal technology,, again cover curtain layer is removed so that the amorphous silicon layer of periphery circuit region becomes a polysilicon layer.Afterwards, carry out an excimer laser annealing process, so that the polysilicon layer of periphery circuit region becomes the polysilicon layer with big crystal grain and makes the amorphous silicon layer of viewing area become polysilicon layer.Then, patterning macromeritic polysilicon layer to form several island polysilicon layers, forms a channel region more respectively and is positioned at the source electrode of channel region both sides in each island polysilicon layer, form a grid again on channel region.
Because the present invention makes the polysilicon that selective metal induced crystallization technology and back quasi-molecule laser annealing technology (post ELA) are applied to periphery circuit region, and back quasi-molecule laser annealing process application is made in the polysilicon of viewing area, so can form little grained polysilicon layer simultaneously in periphery circuit region formation macromeritic polysilicon layer and in the viewing area, and then obtain the good display floater of characteristic.
Description of drawings
Figure 1A to Fig. 1 D is the manufacturing process profile according to the polysilicon layer of the low-temperature polysilicon film transistor of a preferred embodiment of the present invention; And
Fig. 2 A to Fig. 2 H is a manufacturing process profile of making the low-temperature polysilicon film transistor of a preferred embodiment of the present invention in the periphery circuit region of Fig. 1 D.
10: periphery circuit region
12: the viewing area
100: panel
102: resilient coating
104: amorphous silicon layer
104a, 104b: polysilicon layer
106: cover curtain layer
108,230,236: opening
110: metal level
120: crystallization processes
200a, 200b: island polysilicon layer
202,208,216,222: doping process
204a, 204b: channel region
206,214,220: the patterning photoresist layer
210,224: source electrode
212: gate insulator
218: shallow doped-drain zone
226a, 226b: grid
228: interlayer dielectric layer
232: the source/drain contacting metal
234: protective layer
238: pixel electrode
Embodiment
The present invention can be applicable to low temperature polycrystalline silicon (low temperature poly-Si, be called for short LTPS) thin-film transistor (thin film transistor, be called for short TFT), please refer to Figure 1A to Fig. 1 D, it is according to the manufacturing process profile of the polysilicon layer of the low-temperature polysilicon film transistor of a preferred embodiment of the present invention.
Please refer to Figure 1A, on apanel 100, optionally form earlier a resilient coating (bufferlayer) 102, whereinresilient coating 102 for example is the stack layer that a silicon nitride layer and one silica layer are formed, its role is to promote the tack ofpanel 100 and the polysilicon layer of follow-up formation and when metal ion such as sodium is arranged in thepanel 100, in order to prevent the metal ion pollution polysilicon layer in the panel 100.Then, onresilient coating 102, form an amorphous silicon (amorphoussilicon claims a-Si again)layer 104, andpanel 100 comprises a periphery circuit region (peripheralcircuit region) 10 and one viewing area (display region) 12.Utilize crystallization inducing metal technology (metal-induced crystallization then, be called for short MIC), so that theamorphous silicon layer 104 ofperiphery circuit region 10 becomes a polysilicon (poly silicon, claim poly-Si again) layer, its detailed step for example is to form a cover curtain layer (mask layer) 106 earlier onamorphous silicon layer 104, it has an opening 108, to expose the portion ofamorphous silicon layer 104 of periphery circuit region 10.Then, form ametal level 110 on theamorphous silicon layer 104 that is exposed in opening 108, whereinmetal level 110 for example is a nickel dam.
Subsequently, please refer to Figure 1B, carry out acrystallization processes 120, so that theamorphous silicon layer 104 ofperiphery circuit region 10 becomes apolysilicon layer 104a, whereincrystallization processes 120 is solid-phase crystallization technology (solid phase crystallization) for example.And theamorphous silicon layer 104 ofperiphery circuit region 10 can begin crystallization from the part nearmetal level 110 and becomes docrystalline rete.
Then, please refer to Fig. 1 C, after theamorphous silicon layer 104 ofperiphery circuit region 10 becomespolysilicon layer 104a fully by the time, removecover curtain layer 106 again.Since theamorphous silicon layer 104 ofviewing area 12 when carrying out aforementioned metal induced crystallization technology without any metal as inducer, and havecover curtain layer 106 covering, so theamorphous silicon layer 104 ofviewing area 12 is still kept amorphous structure (amorphous structure).
Afterwards, please refer to Fig. 1 D, carry out an excimer laser annealing process (excimer laserannealing, be called for short ELA), so that thepolysilicon layer 104a ofperiphery circuit region 10 becomes the less polysilicon layer 104b of big crystal grain and defective and makes theamorphous silicon layer 104 ofviewing area 12 becomepolysilicon layer 104a, wherein the crystal grain of polysilicon layer 104b is big than the crystal grain of polysilicon layer 104a.And following Fig. 2 A to Fig. 2 H is illustrated in the subsequent technique of making low-temperature polysilicon film transistor in theperiphery circuit region 10 of Fig. 1 D.
Fig. 2 A to Fig. 2 H is a manufacturing process profile of making the low-temperature polysilicon film transistor of a preferred embodiment of the present invention in the periphery circuit region of Fig. 1 D.Please refer to Fig. 2 A, patterningmacromeritic polysilicon layer 104a (asking for an interview Fig. 1 D), to form severalisland polysilicon layers island polysilicon layer 200a for example is the some of the predetermined P of formation type thin-film transistor, andisland polysilicon layer 200b for example is the some of the predetermined N of formation type thin-film transistor, and in after description form the technology of P type and N type thin-film transistor simultaneously.But the present invention is not limited to make simultaneously the manufacturing process of P type and N type thin-film transistor, and only is when an example that explains feature of the present invention with present embodiment.
Afterwards, please refer to Fig. 2 B, carry out a passage doping process (channel doping) 202, in eachisland polysilicon layer
Then, please refer to Fig. 2 C, onpanel 100, form a patterning photoresist layer 206,, and exposeisland polysilicon layer 200b both sides upper surface with coveringisland polysilicon layer 200a and part island polysilicon layer 200b.Afterwards, carry out a n+Doping process 208 is to form thesource electrode 210 of N type thin-film transistor inisland polysilicon layer 200b both sides.
Then, please refer to Fig. 2 D, remove patterning photoresist layer 206, onisland polysilicon layer resilient coating 102, cover agate insulator 212 again.Then, ongate insulator 212, form another patterningphotoresist layer 214,, and expose the position that is close tosource electrode 210 among theisland polysilicon layer 200b with coveringisland polysilicon layer 200a and part island polysilicon layer 200b.Subsequently, carry out a n-Doping process 216 to form the shallow doped-drain zone 218 of N type thin-film transistor, defines the channel region 204b between shallow doped-drain zone 218 simultaneously.
Then, please refer to Fig. 2 E, remove patterningphotoresist layer 214, ongate insulator 212, form another patterning photoresist layer 220 again, coveringisland polysilicon layer 200b and partisland polysilicon layer 200a, and expose the position ofisland polysilicon layer 200b both sides upper surface.Subsequently, carry out a p+Doping process 222 to form the source electrode 224 of P type thin-film transistor, defines the channel region 204a between source electrode 224 simultaneously.
Afterwards, please refer to Fig. 2 F, remove patterning photoresist layer 220, go up formation grid 226a and 226b in channel region 204a and 204b again.Then, onpanel 100, form an interlayer dielectric layer (inter-layer dielectric is called for short ILD) 228, to coverisland polysilicon layer
Then, please refer to Fig. 2 G, in interlayerdielectric layer 228 andgate insulator 212, formseveral openings 230, to exposesource electrode 210 and 224, form several source/drain contacting metals 232 again, source/drain contacting metal 232 is to electrically connect withsource electrode 210 and 224 by opening 230.
Afterwards, please refer to Fig. 2 H, onpanel 100, form aprotective layer 234, inprotective layer 234, form anotheropening 236 again, to expose part source/drain contacting metal 232,protective layer 234 silicon nitride layer for example wherein.At last, form apixel electrode 238,pixel electrode 238 is electrical connected with part source/drain contacting metal 232 by opening 236, whereinpixel electrode 238 such as indium tin oxide (ITO).Because theisland polysilicon layer 200a of present embodiment and the polysilicon layer that 200b is big crystal grain are so can meet the requirement that the low-temperature polysilicon film transistor of periphery circuit region need have the electric current (on-state current) of higher electron mobility (electron mobility) and higher opening.
Characteristics of the present invention are selective metal induced crystallization technology and back quasi-molecule laser annealing technology (post ELA) are applied to the polysilicon making of periphery circuit region, and back quasi-molecule laser annealing process application is made in the polysilicon of viewing area, therefore the present invention can form the polysilicon layer of big crystal grain and the polysilicon layer that forms little crystal grain in the viewing area in periphery circuit region simultaneously, and then obtains the good display floater of characteristic.
Claims (27)
1. the manufacture method of a polysilicon layer is characterized in that, this method comprises:
Form an amorphous silicon layer on a panel, wherein this panel comprises a viewing area and a periphery circuit region;
On this amorphous silicon layer of part of this periphery circuit region, form a metal level;
Carry out a crystallization processes, so that this amorphous silicon layer of this periphery circuit region becomes one first polysilicon layer; And
Carry out an excimer laser annealing process, so that this of this periphery circuit region first polysilicon layer becomes one second polysilicon layer and make this amorphous silicon layer of this viewing area become one the 3rd polysilicon layer, wherein the crystal grain of this second polysilicon layer is greater than the crystal grain of this second polysilicon layer and the 3rd polysilicon layer.
2. the method for claim 1 is characterized in that, forms the step of this metal level on this amorphous silicon layer of part of this periphery circuit region, comprising:
Form a cover curtain layer on this amorphous silicon layer, this cover curtain layer has an opening, with this amorphous silicon layer of part that exposes this periphery circuit region; And
Form this metal level on this amorphous silicon layer that in this opening, is exposed.
3. method as claimed in claim 2 is characterized in that, carries out after this crystallization processes, more comprises removing this cover curtain layer.
4. method as claimed in claim 2 is characterized in that this cover curtain layer comprises silicon oxide layer.
5. the method for claim 1 is characterized in that, this metal level comprises nickel dam.
6. the method for claim 1 is characterized in that, this crystallization processes comprises solid-phase crystallization technology.
7. the method for claim 1 is characterized in that, before forming this amorphous silicon layer on this panel, more is included in and forms a resilient coating on this panel, and wherein this resilient coating comprises the stack layer that a silicon nitride layer and one silica layer are formed.
8. the manufacture method of a low-temperature polysilicon film transistor is characterized in that, this method comprises:
Form an amorphous silicon layer on a panel, wherein this panel comprises a viewing area and a periphery circuit region;
Utilize a crystallization inducing metal technology, so that this amorphous silicon layer of this periphery circuit region becomes one first polysilicon layer;
Carry out an excimer laser annealing process, so that this of this periphery circuit region first polysilicon layer becomes one second polysilicon layer and make this amorphous silicon layer of this viewing area become one the 3rd polysilicon layer, wherein the crystal grain of this second polysilicon layer is greater than the crystal grain of this second polysilicon layer and the 3rd polysilicon layer;
This second polysilicon layer of patterning is to form a plurality of island polysilicon layers;
In each those island polysilicon layer, form the source electrode that a channel region and is positioned at these channel region both sides respectively; And
On this channel region, form a grid.
9. method as claimed in claim 8 is characterized in that, utilizes the step of this crystallization inducing metal technology, comprising:
Form a cover curtain layer on this amorphous silicon layer, this cover curtain layer has an opening, with this amorphous silicon layer of part that exposes this periphery circuit region;
Form a metal level on this amorphous silicon layer that in this opening, is exposed; And
Carry out a crystallization processes.
10. method as claimed in claim 9 is characterized in that, carries out after this crystallization processes, more comprises removing this cover curtain layer.
11. method as claimed in claim 9 is characterized in that, this crystallization processes comprises solid-phase crystallization technology.
12. method as claimed in claim 9 is characterized in that, this cover curtain layer comprises silicon oxide layer.
13. method as claimed in claim 8 is characterized in that, this metal level comprises nickel dam.
14. method as claimed in claim 8 is characterized in that, before forming this amorphous silicon layer on this panel, more is included in and forms a resilient coating on this panel, wherein this resilient coating comprises the stack layer that a silicon nitride layer and one silica layer are formed.
15. method as claimed in claim 8 is characterized in that, after this second polysilicon layer of patterning, more comprises and carries out a doping process.
16. method as claimed in claim 11, it is characterized in that, carry out after this doping process and in each those island polysilicon layer, form respectively before this channel region is positioned at the source electrode of these channel region both sides with this, more be included in covering one gate insulator on those island polysilicon layers and this resilient coating.
17. method as claimed in claim 16 is characterized in that, forms this channel region respectively and this is positioned at the step of the source electrode of these channel region both sides in each those island polysilicon layer, comprising:
On this gate insulator, form one first patterning photoresist layer, to expose the position of each those island polysilicon layer both sides upper surface; And
Carry out a p+Doping process.
18. method as claimed in claim 17 is characterized in that, carries out this p+After the doping process, more comprise and remove this first patterning photoresist layer.
19. method as claimed in claim 8 is characterized in that, forms this channel region respectively and this is positioned at the step of the source electrode of these channel region both sides in each those island polysilicon layer, comprising:
On this panel, form one second patterning photoresist layer,, and expose each those island polysilicon layer both sides upper surface with each those island polysilicon layer of cover part; And
Carry out a n+Doping process.
20. method as claimed in claim 19 is characterized in that, carries out this n+After the doping process, more comprise and remove this second patterning photoresist layer.
21. method as claimed in claim 20, it is characterized in that, in each those island polysilicon layer, form respectively after this channel region and this be positioned at the source electrode of these channel region both sides, more be included in and cover a gate insulator on those island polysilicon layers and this resilient coating.
22. method as claimed in claim 21 is characterized in that, covers after this gate insulator on those island polysilicon layers, more comprises:
On this gate insulator, form one the 3rd patterning photoresist layer, to expose the position of contiguous those source electrode in each those island polysilicon layer; And
Carry out a n-Doping process.
23. method as claimed in claim 22 is characterized in that, carries out this n-After the doping process, more comprise and remove the 3rd patterning photoresist layer.
24. method as claimed in claim 8 is characterized in that, more comprises:
On this panel, form an interlayer dielectric layer;
In this interlayer dielectric layer and this gate insulator, form a plurality of first openings, to expose those source electrode; And
Form a plurality of source/drain contacting metals, those source/drain contacting metals are to be electrical connected with those source electrode by those first openings.
25. method as claimed in claim 24 is characterized in that, more comprises:
On this panel, form a protective layer; And
In this protective layer, form one second opening, to expose those source/drain contacting metals of part; And
Form a pixel electrode, this pixel electrode is to be electrical connected with those source/drain contacting metals of part by this second opening.
26. method as claimed in claim 25 is characterized in that, this pixel electrode comprises indium tin oxide.
27. method as claimed in claim 25 is characterized in that, this protective layer comprises silicon nitride layer.
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| CN 03109485CN1265430C (en) | 2003-04-09 | 2003-04-09 | Low-temperature polysilicon thin film transistor and method for manufacturing polysilicon layer thereof |
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| CN 03109485CN1265430C (en) | 2003-04-09 | 2003-04-09 | Low-temperature polysilicon thin film transistor and method for manufacturing polysilicon layer thereof |
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| CN1265430C CN1265430C (en) | 2006-07-19 |
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| US10084000B2 (en) | 2015-10-23 | 2018-09-25 | Boe Technology Group Co., Ltd. | Array substrate, manufacturing method therefor, display panel, and display apparatus |
| CN106601823A (en)* | 2016-12-29 | 2017-04-26 | 京东方科技集团股份有限公司 | Thin film transistor and manufacturing method thereof |
| CN106920773A (en)* | 2017-03-10 | 2017-07-04 | 京东方科技集团股份有限公司 | A kind of preparation method of display panel, display panel and display device |
| CN108220770A (en)* | 2017-12-15 | 2018-06-29 | 安泰科技股份有限公司 | One kind plus boron high-carbon clean steel vacuum induction furnace smelting preparation method |
| CN114220769A (en)* | 2021-12-17 | 2022-03-22 | 云谷（固安）科技有限公司 | Fabrication method of array substrate and display panel |
| CN114300487A (en)* | 2021-12-30 | 2022-04-08 | 广州华星光电半导体显示技术有限公司 | TFT substrate and preparation method thereof, display panel and display device |
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