CN1512373A

Movatterモバイル変換

Info

Publication number: CN1512373A
Application number: CNA021589100A
Authority: CN
Inventors: 朱克楚
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2002-12-26
Filing date: 2002-12-26
Publication date: 2004-07-14
Anticipated expiration: 2022-12-26
Also published as: CN1295633C

Abstract

本发明提供了一种多CPU通信的方法，该方法包括以下步骤：分别设置与CPU相连的可相互访问的外挂内存空间，将待发送的数据报文由发送方CPU写入与接收方CPU相连的内存空间，设置寄存器以产生中断信号给接收方CPU，接收方CPU收到中断信号后，进行数据报文接收；将待发送的控制报文由发送方CPU写入智能输入输出单元的缓冲区，产生智能输入输出单元的中断信号给接收方CPU，接收方CPU收到中断信号后，从智能输入输出单元的缓冲区中取得控制报文。应用本发明，采用不同的中断和传输通道进行数据传输，解决了重要数据的安全问题，提高了数据传输的速度。

The present invention provides a method for multi-CPU communication, the method comprising the following steps: respectively setting mutually accessible plug-in memory spaces connected to the CPUs, writing data messages to be sent by the sender CPU and connecting them to the receiver CPU memory space, set the register to generate an interrupt signal to the receiving CPU, and the receiving CPU will receive the data message after receiving the interrupt signal; write the control message to be sent into the buffer area of the intelligent input and output unit by the sending CPU , generating an interrupt signal of the intelligent input and output unit to the receiving CPU, and the receiving CPU obtains the control message from the buffer of the intelligent input and output unit after receiving the interrupt signal. By applying the present invention, different interrupts and transmission channels are used for data transmission, which solves the security problem of important data and improves the speed of data transmission.

Description

Translated fromChinese

一种多CPU通信的方法A Method for Multi-CPU Communication

技术领域technical field

本发明涉及通信技术领域，特别是指一种多CPU通信的方法。The invention relates to the technical field of communication, in particular to a multi-CPU communication method.

背景技术Background technique

随着计算机及通信技术的发展，单个CPU已经无法满足人们的需求，多CPU技术也就随之应运而生。With the development of computer and communication technology, a single CPU can no longer meet people's needs, and multi-CPU technology has emerged as the times require.

图1所示为主从式多CPU结构。将具有强大运算能力的通用处理器作为主CPU，将通信控制器或网络处理器等具有强大的通信控制功能和数据转发能力的CPU作为接口元件互连(PCI：Peripheral ComponentInterconnection)总线上的普通PCI设备，完成和外界通信或数据转发功能。这样，在一块单板上就同时拥有强大的运算能力和快速的数据转发能力，这种结构被称之为主从式多CPU结构。Figure 1 shows the master-slave multi-CPU structure. A general-purpose processor with powerful computing capabilities is used as the main CPU, and a CPU with powerful communication control functions and data forwarding capabilities such as a communication controller or network processor is used as an ordinary PCI on the interface component interconnection (PCI: Peripheral Component Interconnection) bus. The device completes the function of communication with the outside world or data forwarding. In this way, a single board has powerful computing capability and fast data forwarding capability at the same time. This structure is called a master-slave multi-CPU structure.

针对主从式多CPU结构，其CPU间的通信通常采用“共享内存+邮箱协议”的方案。图2所示为共享内存式通信队列。在每个CPU都能访问到的空间中建立两个队列，采用接收指针(Precv)和发送指针(Psend)两个指针来对队列进行管理，Precv指向当前正在读取的缓冲区地址，Psend指向存放下一个待发送数据的缓冲区地址。每个队列由32或64个大小为2KB的缓冲区组成，每个缓冲区存放一个需要传输的数据包。队列0中存放主CPU发给从CPU的数据，从CPU定时来读取，队列1中存放从CPU发给主CPU的数据，而主CPU也是定时来读取。For the master-slave multi-CPU structure, the communication between the CPUs usually adopts the scheme of "shared memory + mailbox protocol". Figure 2 shows the shared memory communication queue. Two queues are established in the space that each CPU can access, and the queues are managed by using two pointers, the receiving pointer (Precv) and the sending pointer (Psend). Precv points to the buffer address currently being read, and Psend points to Store the buffer address of the next data to be sent. Each queue consists of 32 or 64 buffers with a size of 2KB, and each buffer stores a data packet that needs to be transmitted. Queue 0 stores the data sent from the master CPU to the slave CPU, and the slave CPU reads it regularly. Queue 1 stores the data sent from the slave CPU to the master CPU, and the master CPU also reads it regularly.

主从CPU间数据发送的方式是完全相同，下面以主CPU向从CPU发送数据包为例来说明数据传输过程。The way of data transmission between the master and slave CPUs is exactly the same. The data transmission process will be described below by taking the master CPU to send data packets to the slave CPU as an example.

主CPU随机地向队列0中写入数据，为防止每个缓冲区中的数据包在没有被取走前，被新的数据改写，设置每个缓冲区的第一个长字为控制位。当有数据需要写入缓冲区时，首先判断缓冲区的第一个长字的内容，若缓冲区的第一个长字为0x5555aaaa，则表示当前缓冲区内的数据包有效，还没有被取走，不能写入新数据；若缓冲区的第一个长字为0xaaaa5555，则表示当前缓冲区内的数据包已经被取走，可以写入新的数据。如果整个队列的每个缓冲区中的数据包全部有效，新来的数据将被丢弃。The main CPU randomly writes data into the queue 0. In order to prevent the data packets in each buffer from being rewritten by new data before being taken away, the first long word of each buffer is set as the control bit. When there is data to be written into the buffer, first judge the content of the first long word of the buffer, if the first long word of the buffer is 0x5555aaaa, it means that the data packet in the current buffer is valid and has not been retrieved Go, new data cannot be written; if the first long word of the buffer is 0xaaaa5555, it means that the data packet in the current buffer has been taken away and new data can be written. If all packets in each buffer of the entire queue are valid, new incoming data will be discarded.

从CPU定时地读取队列0中的数据。Precv从队列的头部遍历到队列的尾部，一旦发现某个缓冲区的第一个长字内容为0x5555aaaa，就把该缓冲区的数据读取出来，同时把该缓冲区的第一个长字修改为0xaaaa5555。从CPU读取数据所需时间的设置原则是：假如从CPU把队列0中所有数据包读取完毕需要的时间为T，为防止从CPU一次读取时有数据包被遗漏，则设置从CPU读取所有数据包的时间为1.5T～2T。The data in queue 0 is read periodically from the CPU. Precv traverses from the head of the queue to the tail of the queue. Once it finds that the first long word content of a certain buffer is 0x5555aaaa, it reads the data of the buffer and at the same time reads the first long word of the buffer Modified to 0xaaaa5555. The setting principle of the time required to read data from the CPU is: if the time required to read all the data packets in queue 0 from the CPU is T, in order to prevent data packets from being missed when reading from the CPU once, set the slave CPU The time to read all data packets is 1.5T~2T.

为了解决访问冲突问题和防止在数据接收的同时新来的数据被丢弃，在取出队列0头部第一个缓冲区的数据包后，立刻修改指针Psend的指向，使它指到队列0的头部，新来的数据就存放在队列0的头部。并且在所有数据包全部取出后，修改指针Precv的指向，使它指向队列0的头部，以保证从CPU每次都是从缓冲区队列的头部开始读取数据。In order to solve the access conflict problem and prevent new data from being discarded while the data is being received, after taking out the data packet in the first buffer at the head of queue 0, immediately modify the pointing of the pointer Psend so that it points to the head of queue 0 The new data is stored at the head of queue 0. And after all data packets are taken out, modify the pointing of pointer Precv to make it point to the head of queue 0, so as to ensure that the data is read from the head of the buffer queue every time from the CPU.

从上述实现方式中可以看出，此方法存在以下缺点：As can be seen from the above implementation, this method has the following disadvantages:

由于传输带宽与传输每个数据包的延迟时间相互矛盾，即传输每个数据包的延迟时间越长，传输带宽也就相对越小，所以，一旦队列长度和读取所有数据包所需的时间确定，传输带宽和传输每个数据包的延迟时间也就随之确定，为保证每次能把数据包全部取走避免遗漏，每次读取所有数据所需的时间应该足够长，而该时间增大就意味着传输每个数据包的延迟时间增大，这对于实时性很强的业务来说是不能允许的。Since the transmission bandwidth and the delay time of transmitting each data packet are contradictory, that is, the longer the delay time of transmitting each data packet, the smaller the transmission bandwidth is. Therefore, once the queue length and the time required to read all data packets Determined, the transmission bandwidth and the delay time of transmitting each data packet will be determined accordingly. In order to ensure that all data packets can be taken away each time to avoid omissions, the time required to read all data each time should be long enough, and the time The increase means that the delay time of transmitting each data packet increases, which is not allowed for the business with strong real-time nature.

CPU间传输的数据很多，各种数据的优先级和重要程度都不同，有的数据包允许被丢弃，而有的数据包一旦被丢弃，将造成系统工作异常。在上述现有技术方案中，无论是普通的数据报文还是重要的控制报文，所有的数据包都是通过同一个通道同一方式进行传输，无法保证重要数据的可靠性。There are a lot of data transmitted between CPUs, and the priority and importance of various data are different. Some data packets are allowed to be discarded, but once some data packets are discarded, the system will work abnormally. In the above prior art solution, no matter it is a common data message or an important control message, all data packets are transmitted through the same channel and in the same way, and the reliability of important data cannot be guaranteed.

对于每个队列来说，数据的写入是随机的，而数据的读取是定时的，访问冲突的问题很难彻底避免和解决。For each queue, the writing of data is random, while the reading of data is timed, and the problem of access conflict is difficult to completely avoid and solve.

由于依靠接收指针和发送指针来对队列进行管理，且主从CPU都有一套维护指针的软件代码，增加了软件设计的复杂度。Because the queue is managed by receiving pointers and sending pointers, and the master and slave CPUs have a set of software codes for maintaining pointers, the complexity of software design is increased.

发明内容Contents of the invention

有鉴于此，本发明提供了一种多CPU通信的方法，在增加传输带宽的同时大大减少传输每个数据包的延迟时间，降低系统的丢包率；同时，彻底解决重要数据的可靠性问题；并且可以完全避免访问冲突，防止由于访问冲突而引起的数据异常。In view of this, the present invention provides a method for multi-CPU communication, which greatly reduces the delay time of transmitting each data packet while increasing the transmission bandwidth, and reduces the packet loss rate of the system; at the same time, it completely solves the reliability problem of important data ; And access conflicts can be completely avoided and data exceptions caused by access conflicts can be prevented.

为达到上述目的，本发明的技术方案是这样实现的：In order to achieve the above object, technical solution of the present invention is achieved in that way:

一种多CPU通信的方法，该方法包括以下步骤：A method for multi-CPU communication, the method comprises the following steps:

分别设置与CPU相连的可相互访问的外挂内存空间，将待发送的数据报文由发送方CPU写入与接收方CPU相连的内存空间，设置寄存器以产生中断信号给接收方CPU，接收方CPU收到中断信号后，进行数据报文接收；Set the mutually accessible plug-in memory space connected to the CPU respectively, write the data message to be sent from the sender CPU to the memory space connected to the receiver CPU, set the register to generate an interrupt signal to the receiver CPU, and the receiver CPU After receiving the interrupt signal, receive the data message;

将待发送的控制报文由发送方CPU写入智能输入输出单元的缓冲区，产生智能输入输出单元的中断信号给接收方CPU，接收方CPU收到中断信号后，从智能输入输出单元的缓冲区中取得控制报文。Write the control message to be sent into the buffer of the intelligent input and output unit by the sender CPU, generate an interrupt signal of the intelligent input and output unit to the receiver CPU, and after receiving the interrupt signal, the receiver CPU Get control packets in the zone.

较佳地，所述设置外挂内存空间步骤进一步包括：在与CPU各自相连的外挂内存空间内，各建立一固定大小的缓冲区，作为接收对方数据报文的目的地址，并在每一个缓冲区增设控制该缓冲区是否可写入消息的控制位；Preferably, the step of setting the external memory space further includes: in each external memory space connected to the CPU, each establishes a buffer with a fixed size as the destination address for receiving the other party's data message, and in each buffer Add a control bit to control whether the buffer can write messages;

较佳地，数据报文的传输过程进一步包括：Preferably, the transmission process of the data message further includes:

发送方CPU判断本方控制位是否为可写入消息状态，如果是就申请本方缓冲区的动态空间并存放待发送的数据报文，否则等待一定时间后，强制把该控制位设置为可写入消息状态，再申请本方缓冲区的动态空间并存放待发送的数据报文；The sender’s CPU judges whether the control bit of its own side is in the state of writing a message. If it is, it applies for the dynamic space of the buffer of its own side and stores the data message to be sent. Otherwise, after waiting for a certain period of time, the control bit is forced to be set to Write the message status, and then apply for the dynamic space of the local buffer and store the data messages to be sent;

发送方CPU将本方缓冲区动态空间中的数据报文写入接收方缓冲区的目的地址后，将本方控制位设置为禁止写入消息状态；After the sender CPU writes the data message in the dynamic space of the buffer of the receiver to the destination address of the buffer of the receiver, the control bit of the sender is set to the state of prohibiting writing messages;

接收方CPU处理完收到的数据报文后，将发送方的控制位修改为可写入消息状态。After the CPU of the receiver finishes processing the received data message, it modifies the control bit of the sender to the status of writing the message.

较佳地，将一个控制报文分为若干个控制帧，其传输过程进一步包括：Preferably, a control message is divided into several control frames, and the transmission process further includes:

a、发送方CPU根据智能输入输出单元中的缓冲区尾指针得到空闲消息帧头指针的地址，然后向该指针所指的缓冲区中写入待传送的控制帧，尾指针指向该缓冲区的下一个空闲消息帧；a. The sender CPU obtains the address of the idle message frame head pointer according to the buffer tail pointer in the intelligent input and output unit, and then writes the control frame to be transmitted in the buffer pointed to by the pointer, and the tail pointer points to the buffer of the buffer next idle message frame;

b、将该缓冲区计数器的值加一，发送方CPU产生智能输入输出单元中断，上报给接收方CPU；b. Add one to the value of the buffer counter, and the CPU of the sending side generates an interrupt of the intelligent input and output unit, and reports it to the CPU of the receiving side;

c、接收方CPU接到中断后，在智能输入输出单元的寄存器中，得到发送方CPU发来的控制报帧所在地址的指针，然后从该指针指向的缓冲区空间处取得待传送的控制报文；c. After receiving the interrupt, the receiver CPU obtains the pointer of the address of the control message frame sent by the sender CPU in the register of the intelligent input and output unit, and then obtains the control message to be transmitted from the buffer space pointed to by the pointer arts;

d、缓冲区头指针指向该缓冲区中的下一个消息帧所在的地址，取完所有控制帧后，缓冲区计数器的值减一。d. The buffer head pointer points to the address where the next message frame in the buffer is located. After all the control frames are fetched, the value of the buffer counter is decremented by one.

较佳地，发送方为从CPU，接收方为主CPU，其中从CPU包括内核和微引擎两部分，数据报文的传输过程进一步包括：Preferably, the sender is a slave CPU, and the receiver is a master CPU, wherein the slave CPU includes two parts, a kernel and a microengine, and the transmission process of the data message further includes:

从CPU将其缓冲区中的待发送的数据报文以直接存取控制方式写入与主CPU相连的缓冲区的目的地址后，主CPU返回硬件信号通知从CPU的微引擎；After the CPU writes the data message to be sent in its buffer to the destination address of the buffer connected to the master CPU in a direct access control mode, the master CPU returns a hardware signal to notify the microengine from the CPU;

从CPU的微引擎将本方的控制位设置为禁止写入消息状态后，产生中断通知从CPU的内核；After the micro-engine of the slave CPU sets its own control bit to the state of prohibiting writing messages, an interrupt is generated to notify the core of the slave CPU;

从CPU的内核控制门铃寄存器发中断给主CPU；From the core of the CPU to control the doorbell register to send an interrupt to the main CPU;

主CPU收到中断后，读取本方缓冲区中的数据，将其封装并发送给上层软件，并将从CPU的控制位设置为可写入消息状态。After the master CPU receives the interrupt, it reads the data in the local buffer, encapsulates it and sends it to the upper layer software, and sets the control bit of the slave CPU to the state of writing the message.

较佳地，发送方为主CPU，接收方为从CPU，其中主CPU包括内核和微引擎两部分，数据报文的传输过程进一步包括：Preferably, the sender is the main CPU, and the receiver is the slave CPU, wherein the main CPU includes two parts, the kernel and the microengine, and the transmission process of the data message further includes:

主CPU将其缓冲区中的待发送的数据报文以字节拷贝方式或直接存取控制方式写入与从CPU相连的缓冲区后，将本方的控制位设置为禁止写入消息状态，并设置从CPU的门铃寄存器发中断给从CPU的内核；After the master CPU writes the data message to be sent in its buffer into the buffer connected to the slave CPU in byte copy mode or direct access control mode, the control bit of the local side is set to prohibit writing the message state, And set the doorbell register from the CPU to send an interrupt to the core of the CPU;

从CPU的内核设置本方的内部线程中断寄存器，使从CPU的微引擎产生中断，转发本方缓冲区中的数据报文；Set the internal thread interrupt register of this party from the core of the CPU, so that the micro-engine of the CPU generates an interrupt and forwards the data message in the buffer of the party;

从CPU的微引擎将主CPU的控制位设置为可写入消息状态。The microengine of the slave CPU sets the control bit of the master CPU to write a message state.

较佳地，所述的固定大小的缓冲区中，只存放一个包括报头和报文的数据报文。Preferably, only one data message including a header and a message is stored in the fixed-size buffer.

较佳地，发送方为从CPU，接收方为主CPU，其中从CPU包括内核和微引擎两部分，控制报文的传输过程进一步包括：Preferably, the sender is a slave CPU, and the receiver is a master CPU, wherein the slave CPU includes two parts, a kernel and a microengine, and the transmission process of the control message further includes:

所述步骤a进一步包括：从CPU根据本方智能输入输出单元中的发送缓冲区尾指针得到指向发送缓冲区的空闲消息帧头指针的地址，然后向该指针所指的缓冲区处写入待传送的控制帧，发送缓冲区尾指针指向发送缓冲区的下一个空闲消息帧；Said step a further comprises: obtain the address of the free message frame head pointer pointing to the sending buffer from the CPU according to the sending buffer tail pointer in the intelligent input and output unit of the own party, and then write the address to be sent to the buffer place indicated by the pointer. For the transmitted control frame, the tail pointer of the sending buffer points to the next free message frame in the sending buffer;

所述步骤c进一步包括：主CPU接到中断后，在从CPU的发送缓冲区中的先进先出寄存器中得到从CPU发来的控制报文的数据指针所在的地址，然后从该指针指向的缓冲区空间处取得待传送的控制报文。Said step c further comprises: after the master CPU receives the interrupt, obtain the address at the data pointer location of the control message sent from the CPU in the first-in-first-out register in the sending buffer of the slave CPU, and then from the address pointed to by the pointer Obtain the control message to be transmitted from the buffer space.

较佳地，发送方为主CPU，接收方为从CPU，其中主CPU包括内核和微引擎两部分，控制报文的传输过程进一步包括：Preferably, the sender is the main CPU, and the receiver is the slave CPU, wherein the main CPU includes two parts, the kernel and the microengine, and the transmission process of the control message further includes:

所述步骤a进一步包括：主CPU读取从CPU的智能输入输出单元中的接收缓冲区中的先进先出寄存器，从该寄存器中得到接收缓冲区尾指针，并根据该尾指针得到从CPU接收缓冲区的空闲消息帧的头指针地址，向该指针所指的缓冲区处写入待传送的控制帧，接收缓冲区尾指针指向接收缓冲区的下一个空闲消息帧；Described step a further comprises: main CPU reads from the first-in-first-out register in the receiving buffer in the intelligent input and output unit of CPU, obtains receiving buffer tail pointer from this register, and obtains from CPU according to this tail pointer The head pointer address of the idle message frame in the buffer, write the control frame to be transmitted to the buffer pointed by the pointer, and the tail pointer of the receiving buffer points to the next idle message frame in the receiving buffer;

所述步骤c进一步包括：从CPU接到中断后，根据本方接收缓冲区头指针处得到主CPU发送来的控制报文的数据指针所在的地址，并从该指针指向的缓冲区处取得待传送的控制报文。Said step c further comprises: after receiving the interrupt from the CPU, obtain the address where the data pointer of the control message sent by the main CPU is obtained according to the head pointer of the receiving buffer of this party, and obtain the address to be received from the buffer pointed to by the pointer. The control message sent.

应用本发明，利用中断来进行数据传输，在增加传输带宽的同时大大减少了每个数据包的延迟时间，降低了系统的丢包率；并依靠中断解决了访问冲突，从而防止了由于访问冲突引起的数据异常。在传输普通的数据报文和重要的控制报文时，分别采用不同的中断和传输通道，避免了数据报文和控制报文在同一通道内相互干扰的问题，彻底解决了重要数据的安全性问题，在数据传输的效率，可靠性和传输带宽等方面有很大的提高，同时，充分利用芯片本身的功能，避免了复杂的软件设计，大大减少了软件设计、维护的工作量。By applying the present invention, the interruption is used for data transmission, the delay time of each data packet is greatly reduced while the transmission bandwidth is increased, and the packet loss rate of the system is reduced; and the access conflict is solved by relying on the interruption, thereby preventing data exceptions. When transmitting ordinary data messages and important control messages, different interrupt and transmission channels are used respectively, which avoids the problem of mutual interference between data messages and control messages in the same channel, and completely solves the security of important data The problem is that the efficiency, reliability and transmission bandwidth of data transmission have been greatly improved. At the same time, the functions of the chip itself are fully utilized to avoid complicated software design and greatly reduce the workload of software design and maintenance.

附图说明Description of drawings

图1为现有技术的主从式多CPU结构图；Fig. 1 is the master-slave type multi-CPU structural diagram of prior art;

图2为现有技术的共享内存式通信队列；Fig. 2 is the shared memory type communication queue of prior art;

图3为主从式CPU的系统结构图；Fig. 3 is a system structure diagram of a master-slave CPU;

图4为数据报文传输模型；Fig. 4 is a data packet transmission model;

图5为IXP1200向MPC750发送控制报文的图解；Figure 5 is an illustration of IXP1200 sending control messages to MPC750;

图6为MPC750向IXP1200发送控制报文的图解。Figure 6 is an illustration of MPC750 sending control messages to IXP1200.

具体实施方式Detailed ways

为使本发明的目的、技术方案及优点更加清楚明白，以下参照附图并举实施例，对本发明做进一步详细说明。In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below with reference to the accompanying drawings and examples.

在本实施例中，以MPC750(Motorola公司PPC系列的通用处理器)和IXP1200(Intel公司的Strong ARM系列的网络处理器)为例，针对主从式多CPU结构详细说明本发明的技术方案。In the present embodiment, taking MPC750 (the general-purpose processor of Motorola's PPC series) and IXP1200 (the network processor of Intel's Strong ARM series) as examples, describe the technical scheme of the present invention in detail for the master-slave multi-CPU structure.

图3所示为主从式CPU的系统结构图。MPC750具有强大的运算能力，在此作为主CPU使用；IXP1200具有强大的数据转发能力，它包括内核(CORE)和微引擎(uE)两部分，CORE是一个精简指令集计算机(RISC：Reduced Instruction System Computer)结构的通用处理器，uE的作用是进行数据的处理和转发，这两部分共同集成在一个芯片中，在此作为从CPU使用。设置两个外挂的内存(SDRAM)分别与MPC750和IXP1200相连，而且MPC750和IXP1200可以相互访问对方的SDRAM空间。Figure 3 shows the system structure diagram of the master-slave CPU. MPC750 has powerful computing power and is used here as the main CPU; IXP1200 has powerful data forwarding capability, which includes two parts: core (CORE) and microengine (uE). CORE is a reduced instruction set computer (RISC: Reduced Instruction System A general-purpose processor with a Computer) structure, and the function of uE is to process and forward data. These two parts are integrated in one chip and used here as a slave CPU. Set two external memories (SDRAM) to connect with MPC750 and IXP1200 respectively, and MPC750 and IXP1200 can visit each other's SDRAM space.

数据报文的流量一般较大，其主要是指IXP1200的uE将自身无法处理的数据报文上报给MPC750进行处理和MPC750将处理后的数据信息下发给IXP1200的uE，在进行数据报文的传输时，是通过主从CPU各自外挂的SDRAM空间来完成的，并且通过中断方式通知对方接收；而控制报文是指MPC750下发给IXP1200的各种控制命令和IXP1200上报给MPC750的状态信息，在进行控制报文的传输时，是通过IXP1200自带的I2O(Intelligent Inputand Output)单元来完成的，并且控制报文的数据传输也采用中断方式通知对方接收，但该中断和数据报文所使用的中断不是同一个中断。这就使数据报文和控制报文分别采用了不同的传输通道，因而避免了数据报文和控制报文采用同一通道相互干扰的问题。MPC750内部也有I2O单元，可以用来作为控制报文的传输通道，在本实施例中，控制报文的传输只使用IXP1200的I2O单元。The flow of data packets is generally large, which mainly means that the uE of the IXP1200 reports the data packets that cannot be processed by itself to the MPC750 for processing, and the MPC750 sends the processed data information to the uE of the IXP1200. The transmission is completed through the external SDRAM space of the master and slave CPUs, and the other party is notified to receive it through an interrupt; the control message refers to the various control commands issued by the MPC750 to the IXP1200 and the status information reported by the IXP1200 to the MPC750. When the control message is transmitted, it is completed through the I2O (Intelligent Input and Output) unit that comes with IXP1200, and the data transmission of the control message also uses the interrupt method to notify the other party to receive it, but the interrupt and the data message used The interrupts are not the same interrupt. This makes the data message and the control message use different transmission channels respectively, thereby avoiding the problem that the data message and the control message use the same channel to interfere with each other. There is also an I2O unit inside the MPC750, which can be used as a transmission channel for control messages. In this embodiment, only the I2O unit of IXP1200 is used for the transmission of control messages.

图4所示为数据报文传输模型。数据报文传输机制的实现过程如下：Figure 4 shows the datagram transmission model. The implementation process of the data message transmission mechanism is as follows:

1、在IXP1200和MPC750的SDRAM内各建立一个2KB的固定缓冲区，作为双方向对方传输数据的目的地址，这样每次数据传输的源地址是动态申请的，而目的地址是固定的；1. Establish a 2KB fixed buffer in the SDRAM of IXP1200 and MPC750 respectively, as the destination address of data transmission to each other, so that the source address of each data transmission is dynamically applied, while the destination address is fixed;

2、为了简化设计，2KB的缓冲区中只存放一个数据报文，它既包括数据报文的报头也包括数据报文的具体数据内容，每次只传输一个数据报文，等对方接收完该报文后，再传输下一个；2. In order to simplify the design, only one data message is stored in the 2KB buffer, which includes both the header of the data message and the specific data content of the data message. After the message, transmit the next one;

3、传输的数据报文长度在40～1500字节之间，而且以60字节长度为主，由于MPC750的直接存取控制器(DMA：Direct Memory Access)在处理较大的数据报文或者DMA链表时，其性能比较明显，而在处理较小的数据报文时，其性能不能很好的体现出来，所以为了简化设计，本实施例采用的方案是：MPC750发给IXP1200的数据报文用字节拷贝(bcopy)方式处理，而IXP1200发给MPC750的数据报文用DMA方式处理；3. The length of the transmitted data message is between 40 and 1500 bytes, and the length is mainly 60 bytes. Since the direct access controller (DMA: Direct Memory Access) of MPC750 is processing larger data messages or When DMA linked list, its performance is relatively obvious, but when processing smaller data packets, its performance can not be well reflected, so in order to simplify the design, the solution adopted in this embodiment is: the data packet sent by MPC750 to IXP1200 It is processed by byte copy (bcopy), and the data message sent by IXP1200 to MPC750 is processed by DMA;

4、为了防止缓冲区内的数据报文来不及取走就被下一个数据报文刷新，另外增加控制位来表示哪个CPU控制当前的数据报文，在2KB的缓冲区旁设置8字节控制位，初始化时把缓冲区内的控制位都设置为1。发送前发现本方的控制位为1时才能发送，否则等待，如果等待很长时间控制位还是0，就把该控制位强制设为1。例如：如IXP1200要向MPC750发送一个数据报文，发送前发现本方SDRAM中的控制位为1，就用DMA方式将要发送的数据报文写到MPC750的SDRAM里，随后uE把本方的控制位置为0，当MPC750在中断服务程序里把该数据报文从MPC750的SDRAM缓冲区读出来后，再把IXP1200的控制位修改为1，这样当IXP1200发现本方的控制位为1时，就可以发送下一个数据报文。MPC750向IXP1200发送数据报文的原理相同。4. In order to prevent the data message in the buffer from being refreshed by the next data message before it is taken away, a control bit is added to indicate which CPU controls the current data message, and an 8-byte control bit is set next to the 2KB buffer , set the control bits in the buffer to 1 during initialization. Before sending, it is found that the control bit of the party is 1 before sending, otherwise wait, if the control bit is still 0 after waiting for a long time, the control bit is forced to be 1. For example: If IXP1200 wants to send a data message to MPC750, and finds that the control bit in its own SDRAM is 1 before sending, it uses DMA to write the data message to be sent into SDRAM of MPC750, and then uE transfers the control bit of its own The position is 0, when the MPC750 reads the data message from the SDRAM buffer of the MPC750 in the interrupt service program, then modify the control bit of the IXP1200 to 1, so that when the IXP1200 finds that the control bit of the local side is 1, it will The next datagram can be sent. The principle of sending data packets from MPC750 to IXP1200 is the same.

5、利用每个设备的PCI配置空间内的门铃(DoorBell)寄存器，实现PCI总线上的主从CPU之间中断方式的通信。如果IXP1200作为PCI总线的目标(Target)设备设置该寄存器，就产生一个中断送给MPC750，如果MPC750作为PCI总线的主机(HOST)处理器设置该寄存器，就产生一个中断送给IXP1200。5. Utilize the doorbell (DoorBell) register in the PCI configuration space of each device to realize the interrupt mode communication between the master and slave CPUs on the PCI bus. If IXP1200 sets this register as the target (Target) device of the PCI bus, an interrupt will be generated and sent to MPC750. If MPC750 is set as the host processor (HOST) of the PCI bus, an interrupt will be sent to IXP1200.

下面具体说明主从CPU之间数据报文的传输过程。The following describes the transmission process of data packets between the master and slave CPUs in detail.

IXP1200发送数据报文给MPC750：IXP1200 sends data packets to MPC750:

1、初始化时IXP1200和MPC750各自把本方的控制位写为1，当IXP1200有数据报文要发送时，先读取本方缓冲区的控制位，如果控制位为1就可以继续执行发送数据报文的操作，否则就等待，直至等待的时间大于发送一个数据报文所需时间的20倍，就强制把该控制位设置为1；1. During initialization, IXP1200 and MPC750 respectively write the control bit of their own side as 1. When IXP1200 has a data message to send, it first reads the control bit of the local buffer. If the control bit is 1, it can continue to send data The operation of the message, or wait until the waiting time is greater than 20 times the time required to send a data message, and the control bit is forced to be set to 1;

2、如果控制位为1，uE申请本方SDRAM中的动态空间存放待发送的数据报文；2. If the control bit is 1, the uE applies for the dynamic space in its own SDRAM to store the data message to be sent;

3、通过uE的PCI_DMA指令，uE用DMA方式把该待发送的数据报文写入MPC750的SDRAM内；3. Through the PCI_DMA command of uE, uE uses DMA to write the data message to be sent into the SDRAM of MPC750;

4、MPC750收到该数据后，返回一个硬件信号通知uE，uE此时先把本方的控制位写为0，然后产生一个中断信号通知CORE，CORE再执行相应中断服务程序，在此中断服务程序中只需设置本方的Doorbell寄存器发外部中断给MPC750，CORE执行完此操作后退出该中断服务程序；4. After MPC750 receives the data, it returns a hardware signal to notify uE. At this time, uE first writes its own control bit as 0, and then generates an interrupt signal to notify CORE, and CORE executes the corresponding interrupt service program. Here, the interrupt service In the program, it is only necessary to set the Doorbell register of the local party to send an external interrupt to the MPC750, and the CORE exits the interrupt service program after executing this operation;

5、MPC750收到该中断后，从缓冲区中读取IXP1200发送来的数据报文，并将之封装完毕后送给上层软件处理，并把IXP1200的控制位写为1。5. After receiving the interrupt, MPC750 reads the data message sent by IXP1200 from the buffer, encapsulates it and sends it to the upper layer software for processing, and writes the control bit of IXP1200 as 1.

MPC750发送数据报文给IXP1200：MPC750 sends data packets to IXP1200:

1、初始化时IXP1200和MPC750各自把本方的控制位写为1，当MPC750有数据报文要发送时，先读取本方缓冲区的控制位，如果控制位为1就可以继续执行发送数据报文的操作，否则就等待，直至等待的时间大于发送一个数据报文所需时间的20倍，就强制把该控制位设置为1；1. During initialization, IXP1200 and MPC750 each write their own control bit as 1. When MPC750 has a data message to send, it first reads the control bit of its own buffer. If the control bit is 1, it can continue to send data The operation of the message, or wait until the waiting time is greater than 20 times the time required to send a data message, and the control bit is forced to be set to 1;

2、如果控制位为1，MPC750先申请本方SDRAM中的动态空间存放待发送的数据报文，再用bcopy的方式把数据报文写入到IXP1200的SDRAM内，写入完成后把本方的控制位写为0；2. If the control bit is 1, the MPC750 first applies for the dynamic space in the local SDRAM to store the data message to be sent, and then writes the data message into the SDRAM of the IXP1200 by means of bcopy. The control bit is written as 0;

3、MPC750设置IXP1200的Doorbell寄存器以产生相应中断信号给IXP1200的CORE，CORE再执行相应中断服务程序，在此中断服务程序中，只需要设置IXP1200中CORE上的内部线程中断(INTER_THD_SIG)寄存器，使uE产生中断并转发MPC750发送来的数据报文，CORE执行完此操作后退出该服务程序；3. The MPC750 sets the Doorbell register of the IXP1200 to generate a corresponding interrupt signal to the CORE of the IXP1200, and the CORE executes the corresponding interrupt service program. uE generates an interrupt and forwards the data message sent by MPC750, and CORE exits the service program after executing this operation;

4、uE收到中断后将MPC750的控制位改为1。4. After receiving the interrupt, uE changes the control bit of MPC750 to 1.

控制报文传输机制的实现过程：The implementation process of the control message transmission mechanism:

相对于数据报文，控制报文的流量较少，但是它要求的传输可靠性很高，数据报文在流量过大时允许丢包，但是控制报文要尽量避免这种情况。为了满足这种高可靠性的需求，将一个控制报文分为若干个控制帧，并采用I2O单元来实现控制报文的传输，I2O为挂在PCI总线上的设备之间进行通信提供了一个标准、可靠的消息传递机制，它包含了四个位于本地SDRAM中的先进先出缓冲区(FIFOs)：即Compared with data packets, the traffic of control packets is less, but it requires high transmission reliability. Data packets are allowed to lose packets when the traffic is too large, but control packets should try to avoid this situation. In order to meet this high reliability requirement, a control message is divided into several control frames, and the I2O unit is used to realize the transmission of the control message. I2O provides a communication between devices connected to the PCI bus. A standard, reliable messaging mechanism consisting of four first-in-first-out buffers (FIFOs) located in local SDRAM: the

Inbound free list FIFO：接收缓冲区中的空闲队列；Inbound free list FIFO: the free queue in the receive buffer;

Inbound post list FIFO：接收缓冲区中已经被占用的队列；Inbound post list FIFO: queues already occupied in the receive buffer;

Outbound free list FIFO：发送缓冲区中的空闲队列；Outbound free list FIFO: the free queue in the send buffer;

Outbound post list FIFO：发送缓冲区中已经被占用的队列。Outbound post list FIFO: The queue that has been occupied in the send buffer.

MPC750和IXP1200各有一个I2O单元，可以使用各自的I2O单元实现两者间的通信，为了更好的支持多CPU的结构，在本实施例中只使用IXP1200的接收缓冲区和发送缓冲区，即只使用IXP1200提供的I2O单元，不使用MPC750的该单元。MPC750 and IXP1200 each have an I2O unit, and can use their respective I2O units to realize the communication between the two. In order to better support the multi-CPU structure, only the receive buffer and send buffer of IXP1200 are used in this embodiment, namely Only use the I2O unit provided by IXP1200, do not use this unit of MPC750.

IXP1200发送控制报文给MPC750：IXP1200 sends control message to MPC750:

为了程序设计的方便，使用OUT_MFA_HEAD_PTR和out_mfa_tail_ptr分别表示发送缓冲区中已被占用队列的头指针和尾指针，由于该队列和空闲队列共用一段连续的内存的空间，所以发送缓冲区的空闲队列的头指针和尾指针也可以知道，即发送缓冲区中已被占用队列的头指针和尾指针就是发送缓冲区的空闲队列的尾指针和头指针。同时，用发送缓冲区计数器(OUT_BOUND_CNT)记录发送缓冲区中需要发送的数据报文的个数。For the convenience of program design, use OUT_MFA_HEAD_PTR and out_mfa_tail_ptr to indicate the head pointer and tail pointer of the occupied queue in the sending buffer respectively. Since the queue and the free queue share a continuous memory space, the head of the free queue in the sending buffer The pointer and the tail pointer can also be known, that is, the head pointer and the tail pointer of the occupied queue in the sending buffer are the tail pointer and the head pointer of the idle queue of the sending buffer. At the same time, use the sending buffer counter (OUT_BOUND_CNT) to record the number of data packets that need to be sent in the sending buffer.

图5所示为IXP1200向MPC750发送控制报文的图解。首先IXP1200根据out_mfa_tail_ptr得到指向发送缓冲区的空闲消息帧的头指针的地址，然后向该指针所指的内存处依次写入待发送的控制帧，每写一帧，out_mfa_tail_ptr就下移一帧，直到所有控制帧写完后，out_mfa_tail_ptr指向发送缓冲区的下一个空闲消息帧，以便下次发送控制报文使用，OUT BOUND CNT的值加一。只要OUT BOUND CNT的值不等于0，IXP1200就会产生PCI中断，上报给MPC750。Figure 5 shows the illustration of IXP1200 sending control messages to MPC750. First, the IXP1200 obtains the address of the head pointer pointing to the idle message frame of the sending buffer according to out_mfa_tail_ptr, and then writes the control frame to be sent to the memory pointed to by the pointer in sequence. Every time a frame is written, out_mfa_tail_ptr moves down by one frame until After all the control frames are written, out_mfa_tail_ptr points to the next idle message frame in the send buffer for the next time the control message is sent, and the value of OUT BOUND CNT is increased by one. As long as the value of OUT BOUND CNT is not equal to 0, IXP1200 will generate a PCI interrupt and report it to MPC750.

MPC750收到中断后，从IXP1200的发送缓冲区先进先出寄存器(OUTBOUND_FIFO)中得到IXP1200发来的控制帧所在地址的指针，然后从该指针所指地址的内存空间处取得待传送的控制帧，每取一帧，OUT_MFA_HEAD_PTR就指向发送缓冲区的下一个控制帧所在的地址，待所有控制帧取完后，OUT_BOUND_CNT的值减一。After the MPC750 receives the interrupt, it obtains the pointer of the address of the control frame sent by the IXP1200 from the first-in-first-out register (OUTBOUND_FIFO) of the sending buffer of the IXP1200, and then obtains the control frame to be transmitted from the memory space of the address pointed to by the pointer. Every time a frame is fetched, OUT_MFA_HEAD_PTR points to the address of the next control frame in the sending buffer, and after all the control frames are fetched, the value of OUT_BOUND_CNT is reduced by one.

MPC750发送控制报文给IXP1200：MPC750 sends a control message to IXP1200:

为了程序设计的方便，使用IN_MFA_TAIL_PTR和in_mfa_head_ptr分别表示接收缓冲区中已被占用队列的尾指针和头指针，由于该队列和空闲队列共用一段连续的内存的空间，所以接收缓冲区的空闲队列的头指针和尾指针也可以知道，即接收缓冲区中已被占用队列的尾指针和头指针就是接收缓冲区的空闲队列的头指针和尾指针。同时，用接收缓冲区计数器(IN_BOUND_CNT)记录接收缓冲区中已经接收的数据报文的个数。For the convenience of program design, use IN_MFA_TAIL_PTR and in_mfa_head_ptr to represent the tail pointer and head pointer of the occupied queue in the receiving buffer respectively. Since the queue and the free queue share a continuous memory space, the head of the free queue in the receiving buffer The pointer and the tail pointer can also be known, that is, the tail pointer and the head pointer of the occupied queue in the receiving buffer are the head pointer and the tail pointer of the free queue of the receiving buffer. At the same time, use the receiving buffer counter (IN_BOUND_CNT) to record the number of received data packets in the receiving buffer.

图6所示为MPC750向IXP1200发送控制报文的图解。MPC750向IXP1200发送控制报文时，MPC750先读IXP1200的接收缓冲区先进先出寄存器(INBOUND_FIFO)，根据IN_MFA_TAIL_PTR得到IXP1200接收缓冲区的空闲消息帧的头指针的地址，然后向该指针所指的内存处依次写入待发送的控制帧，每写一帧，IN_MFA_TAIL_PTR就下移一帧，直到所有控制帧写完后，IN_MFA_TAIL_PTR指针指向接收缓冲区的下一个空闲消息帧，以便下次发送控制报文使用，IN_BOUND_CNT的值加一。只要IN_BOUND_CNT的值不等于0，MPC750就会产生I2O中断上报给IXP1200。Figure 6 shows the illustration of MPC750 sending control messages to IXP1200. When the MPC750 sends a control message to the IXP1200, the MPC750 first reads the first-in-first-out register (INBOUND_FIFO) of the receiving buffer of the IXP1200, obtains the address of the head pointer of the idle message frame of the receiving buffer of the IXP1200 according to IN_MFA_TAIL_PTR, and then transfers to the memory pointed to by the pointer Each time a frame is written, the IN_MFA_TAIL_PTR will move down one frame until all the control frames are written, and the IN_MFA_TAIL_PTR pointer points to the next idle message frame in the receiving buffer, so that the control message can be sent next time Use, add one to the value of IN_BOUND_CNT. As long as the value of IN_BOUND_CNT is not equal to 0, MPC750 will generate an I2O interrupt and report it to IXP1200.

IXP1200接到I2O中断后，在in_mfa_head_ptr处得到MPC750发来的控制帧所在地址的指针，再从该指针所指地址的内存处取得待传送的控制帧，每取一帧，in_mfa_head_ptr就指向接收缓冲区的下一个控制帧所在地址，待所有控制帧取完后，IN_BOUND_CNT的值减一。After IXP1200 receives the I2O interrupt, it gets the pointer of the address of the control frame sent by MPC750 at in_mfa_head_ptr, and then gets the control frame to be transmitted from the memory at the address pointed to by the pointer. Every time a frame is taken, in_mfa_head_ptr points to the receiving buffer The address of the next control frame, after all the control frames are fetched, the value of IN_BOUND_CNT will be reduced by one.

在本实施例中，MPC750和IXP1200进行数据传输时，MPC750是采用bcopy方式把数据发送给IXP1200的，如果数据量很大，MPC750也可以采用DMA的方式把数据发送给IXP1200，数据传输速度会更快，而且CPU的占用率也会降低。In this embodiment, when MPC750 and IXP1200 perform data transmission, MPC750 uses the bcopy method to send the data to IXP1200. If the amount of data is large, MPC750 can also use DMA to send the data to IXP1200, and the data transmission speed will be faster. Faster, and the CPU usage will be reduced.

以上实施例只介绍了主CPU和一个从CPU的通信情况，该通信方法同样适用于主CPU和两个或两个以上从CPU同时通信的情况。同时，对于其它系列有类似结构的CPU，该通信方法同样适用。The above embodiments only introduce the communication between the master CPU and one slave CPU, and this communication method is also applicable to the situation where the master CPU communicates with two or more slave CPUs simultaneously. At the same time, this communication method is also applicable to other series of CPUs with similar structures.

以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the scope of the present invention. within the scope of protection.

Claims

Translated fromChinese

1、一种多CPU通信的方法，其特征在于，该方法包括以下步骤：1. A method for multi-CPU communication, characterized in that the method may further comprise the steps:

2、根据权利要求1所述的多CPU通信的方法，其特征在于，所述设置外挂内存空间步骤进一步包括：2. The method for multi-CPU communication according to claim 1, wherein the step of setting the external memory space further comprises:

在与CPU各自相连的外挂内存空间内，各建立一固定大小的缓冲区，作为接收对方数据报文的目的地址，并在每一个缓冲区增设控制该缓冲区是否可写入消息的控制位；In the plug-in memory spaces connected to the CPU respectively, a fixed-size buffer is established as the destination address for receiving the other party's data message, and a control bit for controlling whether the buffer can be written into a message is added to each buffer;

3、根据权利要求2所述的多CPU通信的方法，其特征在于，数据报文的传输过程进一步包括：3. The method for multi-CPU communication according to claim 2, wherein the transmission process of the data message further comprises:

4、根据权利要求1所述的多CPU通信的方法，其特征在于，将一个控制报文分为若干个控制帧，其传输过程进一步包括：4. The method for multi-CPU communication according to claim 1, wherein a control message is divided into several control frames, and its transmission process further comprises:

5、根据权利要求3所述的多CPU通信的方法，其特征在于，发送方为从CPU，接收方为主CPU，其中从CPU包括内核和微引擎两部分，数据报文的传输过程进一步包括：5. The method for multi-CPU communication according to claim 3, wherein the sender is a slave CPU, and the receiver is a master CPU, wherein the slave CPU includes two parts, a kernel and a microengine, and the transmission process of the data message further includes :

6、根据权利要求3所述的多CPU通信的方法，其特征在于发送方为主CPU，接收方为从CPU，其中主CPU包括内核和微引擎两部分，数据报文的传输过程进一步包括：6. The method for multi-CPU communication according to claim 3, wherein the sender is the main CPU, and the receiver is the slave CPU, wherein the main CPU includes two parts, the kernel and the microengine, and the transmission process of the data message further includes:

7、根据权利要求2或5或6所述的多CPU通信的方法，其特征在于：所述的固定大小的缓冲区中，只存放一个包括报头和报文的数据报文。7. The multi-CPU communication method according to claim 2, 5 or 6, characterized in that only one data message including a header and a message is stored in the fixed-size buffer.

8、根据权利要求4所述的多CPU通信的方法，其特征在于发送方为从CPU，接收方为主CPU，其中从CPU包括内核和微引擎两部分，控制报文的传输过程进一步包括：8. The method for multi-CPU communication according to claim 4, wherein the sender is a slave CPU, and the receiver is a master CPU, wherein the slave CPU includes two parts, a kernel and a microengine, and the transmission process of the control message further includes:

9、根据权利要求4所述的多CPU通信的方法，其特征在于发送方为主CPU，接收方为从CPU，其中主CPU包括内核和微引擎两部分，控制报文的传输过程进一步包括：9. The method for multi-CPU communication according to claim 4, characterized in that the sender is the main CPU, and the receiver is the slave CPU, wherein the main CPU includes two parts, the kernel and the microengine, and the transmission process of the control message further includes: