CN1466177A

Movatterモバイル変換

Info

Publication number: CN1466177A
Application number: CNA021401381A
Authority: CN
Inventors: 何濂泽
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2002-07-03
Filing date: 2002-07-03
Publication date: 2004-01-07
Anticipated expiration: 2022-07-03
Also published as: CN1208817C

Abstract

本发明揭露一种金氧半导体(MOS)晶体管的制造方法。此方法系于源极/漏极区域形成前，先于硅基板表面沉积一遮蔽层。此遮蔽层以均一的厚度覆盖基板上的栅极电极及场氧化层或浅隔离沟渠。接着，对硅基板进行高浓度的离子植入，并控制其能量使离子无法穿透栅极电极侧壁的遮蔽层。而在去除此遮蔽层之后，再对此硅基板进行低浓度的离子掺杂。依此方式，将可利用较少的工艺步骤形成具有LDD的MOS晶体管。

The present invention discloses a method for manufacturing a metal oxide semiconductor (MOS) transistor. This method is to deposit a shielding layer on the surface of a silicon substrate before forming the source/drain region. This shielding layer covers the gate electrode and the field oxide layer or shallow isolation trench on the substrate with a uniform thickness. Then, high-concentration ion implantation is performed on the silicon substrate, and its energy is controlled so that the ions cannot penetrate the shielding layer on the side wall of the gate electrode. After removing this shielding layer, low-concentration ion doping is performed on the silicon substrate. In this way, a MOS transistor with LDD can be formed using fewer process steps.

Description

The manufacture method of MOS (metal-oxide-semiconductor) transistor

Technical field

The present invention relates to a kind of manufacture method of MOS transistor, particularly a kind of in order to reduce the method that LDD forms step.

Background technology

In a MOS transistor, channel length is the distance between source electrode and drain electrode.For size of components is dwindled, must shorten the length of raceway groove.Yet well-known, the too short performance that can produce thermoelectronic effect (Hot Electron Effects) and influence MOS transistor of MOS raceway groove.For solving this problem, can be in source electrode and the place of drain electrode near raceway groove, form light dope drain electrode (Lightly Doped Drain, LDD).

Fig. 1 (a) shows the formation method of a kind of LDD of existing MOS transistor to Fig. 1 (g).

At first, according to existing semiconductor technology, on a Ptype silicon substrate 100, form gridoxic horizon 101,gate electrode 102 andfield oxide 103, shown in Fig. 1 (a).Secondly, coating one deck photoresistance on this substrate.Then, utilize one first light shield (not icon) that this layer photoresistance exposed.After developing, can on this substrate, form one first photoresist layer 105.Afterwards, utilize this first photoresist layer 105, Ptype silicon substrate 100 surfaces are carried out the phosphonium ion of low concentration and implant 104 (N as shielding^-Mix N^-Doped), shown in Fig. 1 (b).This step can formlight dope zone 106 on P type silicon substrate 100.Afterwards, again first photoresist layer 105 is removed, shown in Fig. 1 (c).

Then, utilize low-pressure chemical vapor deposition method (Low Pressure Chemical VaporDeposition), deposition one silicon dioxide layer 107 on this P type silicon substrate is shown in Fig. 1 (d).Utilize the anisotropic etching technology again, this silicon dioxide layer 107 is carried out etching.Shown in Fig. 1 (e), can form grid gap wall (Spacer) 117 ingate electrode 102 sidewalls after the etching.

With reference to Fig. 1 (f), on this P type silicon substrate, be coated with one deck photoresistance once more.Utilize one second light shield that this layer photoresistance exposed, and in the back of developing form be covered infield oxide 103 on second photoresist layer 115.Then, utilize this secondphotoresist layer 115 and the 117 conduct shieldings of gate pole clearance wall, these Ptype silicon substrate 100 surfaces are carried out the arsenic ion of high concentration and implant 114 (N⁺Mix N⁺Doped).This step can form highly doped regional 116 on Ptype silicon substrate 100, afterwards, remove this second photoresist layer again, shown in Fig. 1 (g).This highly doped regional 116 andlight dope zone 106 promptly as the source electrode and the drain electrode of this MOS transistor.

Mode can form the MOS transistor with LDD design according to this.

Yet this existing technology is used two road light shields (annotating: first light shield and second light shield) with needs.That is, when forming the light dope zone, must pass through photoresistance coating, exposure, development and the etched process of photoresistance respectively with highly doped zone.In addition, form the step of grid gap wall, also comprise deposition and etching step.Therefore, for formation has the MOS transistor of this LDD, it is quite complicated that its processing step can become.

Summary of the invention

Therefore, the purpose of this invention is to provide the manufacture method that a kind of LDD of being reduced forms the MOS transistor of step.

According to preferred embodiment of the present invention, the manufacture method of this MOS transistor comprises the following step:

On a substrate, form a grid oxic horizon, a gate electrode and a field oxide;

Deposition one deck shielding layer on this substrate, this shielding layer is with a homogeneous thickness cover gate electrode, field oxide and substrate surface, and wherein, this shielding layer can form sidewall areas in gate electrode side, and the shielding layer thickness of this sidewall areas can be greater than this homogeneous thickness;

On this substrate, form a resistance agent pattern, to cover field oxide;

This substrate is carried out ion implant to form a highly doped zone, wherein, the energy that ion is implanted is controlled at and makes ion can't penetrate the shielding layer of sidewall areas;

Remove not by the shielding layer of this resistance agent pattern covers;

This substrate is carried out ion to be implanted to form a light dope zone; And

Remove this resistance agent pattern and this residual shielding layer.

According to another aspect of the present invention, also can shallow trench isolation replace field oxide, with the usefulness of isolating as assembly.

Advantage of the present invention is: form in the step at LDD, only need to use one light shield.Simultaneously, also can save the step that forms grid gap wall.

Purpose of the present invention, feature and advantage, after the explanation of reference accompanying drawing and following routine embodiment, can be clearer.

Description of drawings

Fig. 1 (a) shows that to 1 (g) prior art is in order to make the method for MOS transistor; And

Fig. 2 (a) shows the manufacture method of the MOS transistor of the embodiment of the invention to 2 (f).

Fig. 3 shows the existing transistor of isolating as assembly with shallow trench isolation.[symbol descriptions] 100: substrate 101: grid oxic horizon 102: gate electrode 103: field oxide 104: 105: the firstphotoresist layers 106 of the implanted ions of low concentration: light dope zone 107: silicon dioxide layer 114: 115: the secondphotoresist layers 116 of the implanted ions of high concentration: highly doped regional 117: grid gap wall (Spacer) 200: silicon substrate 201: grid oxic horizon 202: gate electrode 203: field oxide 204: silicon substrate surface 220: shielding layer 221: theshielding layer 222 on silicon substrate surface: sidewall areas 230: photoresist layer 240: highly doped regional 241: light dope zone 300: substrate 301: grid oxic horizon 302: gate electrode 303: shallow trench 306: light dope zone 316: highly doped zone

Embodiment

Fig. 2 (a) shows the manufacture method of the MOS transistor of preferred embodiment of the present invention to 2 (f).

Referring to Fig. 2 (a), utilized prior art to make a gridoxic horizon 201, agate electrode 202 andfield oxide 203 on the P type silicon substrate 200.Wherein, the exposed surface 204 of thissilicon substrate 200 will be in order to make the source electrode and the drain electrode of MOS transistor.In the present embodiment,gate electrode 202 is made of polysilicon, andfield oxide 203 is the silicon dioxide layer for utilizing wet oxidation process to grow up then.

In the present embodiment, before regions and source formed, deposition oneshielding layer 220 was on this substrate surface, shown in Fig. 2 (b) earlier.Thisshielding layer 220 is made of the material with good step covering power, for example BARC (bottom anti-reflective coating material, BottomAnti-Reflective Coating).The material of this shielding layer can be made of organic material; Perhaps constitute, for example amorphous phase carbon film (amorphous carbon), silicon nitride (SiN), silicon oxynitride (SiO by inorganic material_xN_y, silicon oxynitride) and titanium oxide (TiO) etc.

Because the ladder coverage property of thisshielding layer 220 is good, it will be covered ongate electrode 202,field oxide 203 andsilicon substrate 200 surfaces with a homogeneous thickness.In addition, be adjacent to the shielding layer thickness of thesidewall areas 222 ofgate electrode 202, will be thick more a lot of than silicon substrate surface 204.As shown in the figure, the thickness of supposing this shielding layer is X, and then then for the height H of gate electrode adds its thickness X, that is its thickness equals H+X to thisshielding layer 220 in the thickness ofgate electrode 202 sidewalls.The present invention utilizes this feature, forms LDD, and is as described below.

For carrying out the action that ion is implanted, at first on thissubstrate 200, be coated with one deck photoresistance 230.This photoresistance can be positive photoresistance.Then, utilize a little shadow technology and a light shield, make thisphotoresist layer 230 patternings.Utilize thisphotoresist layer 230 andshielding layer 220 as shielding again, the ion that this substrate is carried out high concentration is implanted to form highly doped regional 240, shown in Fig. 2 (c).In the present embodiment, this high-concentration dopant ion can be N type admixture (N-type dopant), for example arsenic ion.

The front mentions, and thisshielding layer 220 is positioned at the thickness ofsidewall areas 222 can be thick more a lot of than silicon substrate surface 204.Therefore, the energy that our may command ion is implanted makes its shielding layer that can'tpenetrate sidewall areas 222 220, and only penetrates theshielding layer 221 on silicon substrate surface 204, to form highly doped regional 240.In other words, belowsidewall areas 222, will can not form the ion doping zone.

Then, referring to Fig. 2 (d), utilize thisphotoresistance 230 equally as shielding, thisshielding layer 220 of etching.

Afterwards, referring to Fig. 2 (e), thissilicon substrate 200 is carried out the low concentration ion doping.As shown in the figure, remove after theshielding layer 220, thesidewall areas 222 ofgate electrode 202 has not had and has covered, so its below can form light dope zone 241.In this embodiment, the light dope ion is N type admixture (N-type dopant), for example phosphonium ion.

At last,photoresistance 230 andresidual shielding layer 220 are removed, shown in Fig. 2 (f).Mode just can form the MOS transistor with LDD design according to this.Wherein, one group is positioned at gate electrode other highly doped regional 240 andlight dope zone 241 promptly as the source electrode of this MOS transistor, and the doped region that is positioned at the gate electrode another side is then as the drain electrode of this MOS transistor.

Can find clearly to 2 (f) that by Fig. 2 (a) the present invention in the process that forms LDD, only uses light shield in order to form the method for MOS transistor one.Therefore, the method according to this invention can reduce technologies such as the coating of another time photoresistance, exposure, development and etching.In addition, the present invention also saves the step that forms grid gap wall.So the method according to this invention can effectively reduce processing step and and then improves production capacity, reduces cost.

In addition, though the present invention uses a P type silicon substrate, the ion implantation step uses N type admixture, yet the present invention also can use a N type silicon substrate, and uses P type admixture to carry out ion and implant.Simultaneously, though the present invention utilizes field oxide as the assembly area of isolation, yet as shown in Figure 3, those skilled in the art should also can utilizeshallow trench isolation 303 as the assembly area of isolation as can be known.

Though preferred embodiment of the present invention illustrated as before, it only is the usefulness of explanation.What need understand is that in not deviating from the present invention's spirit and scope, it still can do various modification and variation herein.