


发明领域field of invention
本发明总的来说涉及微电子结构和器件及其制造方法,更具体地说,涉及薄膜金属氧化物结构和器件,并且涉及薄膜金属氧化物结构和器件的制造及使用。The present invention relates generally to microelectronic structures and devices and methods of fabrication thereof, and more particularly to thin film metal oxide structures and devices, and to the manufacture and use of thin film metal oxide structures and devices.
发明背景Background of the invention
多种金属氧化物都表现出希望的特性,例如压电、铁电、铁磁、大磁阻和超导性能。在采用这些特性优点的有关的微电子器件中可以包含或者使用这些氧化物。例如,可以使用金属氧化物来形成铁电存储器件等。A variety of metal oxides exhibit desirable properties such as piezoelectricity, ferroelectricity, ferromagnetism, large magnetoresistance, and superconductivity. These oxides may be included or used in related microelectronic devices that take advantage of these properties. For example, metal oxides can be used to form ferroelectric memory devices and the like.
通常,金属氧化物膜的希望特性随着氧化物膜结晶度的增加而增加。例如,当材料处于单晶形式时,超导材料表现出最高的导电率。此外,还希望这些氧化物与半导体元件一体化以便形成器件例如存储器件。据此,人们渴望得到在半导体衬底上生长薄膜单晶金属氧化物的方法和装置。In general, desirable properties of metal oxide films increase as the crystallinity of the oxide film increases. For example, superconducting materials exhibit the highest electrical conductivity when the material is in a single crystal form. In addition, it is also desirable that these oxides are integrated with semiconductor elements to form devices such as memory devices. Accordingly, people are eager to obtain methods and devices for growing thin film single crystal metal oxides on semiconductor substrates.
由于各种金属氧化物材料的希望的特性,并且由于它们目前通常的高成本和块状时(in bulk form)低的实用性,许多年来一直试图在外来衬底上生长希望的金属氧化物材料薄膜。然而,为了实现金属氧化物材料的最佳特性,希望得到高结晶质量的单晶膜。例如,已经试图在衬底例如硅上生长单晶金属氧化物材料层。通常这些努力没有获得成功,因为基质晶体(host crystal)和生长的晶体之间晶格的不匹配已经使得到的金属氧化物材料薄膜具有低的结晶质量。已经在氧化物衬底上例如块状钛酸锶生长更高质量的金属氧化物。生长在氧化物衬底上的金属氧化物经常是昂贵的,一部分是因为氧化物衬底小且昂贵。Due to the desirable properties of various metal oxide materials, and due to their current generally high cost and low availability in bulk form, attempts have been made for many years to grow desirable metal oxide materials on exotic substrates. film. However, to achieve optimal properties of metal oxide materials, single crystal films of high crystalline quality are desired. For example, attempts have been made to grow layers of single crystal metal oxide materials on substrates such as silicon. Often these efforts have not been successful because the lattice mismatch between the host crystal and the growing crystal has resulted in low crystalline quality of the resulting thin films of metal oxide materials. Higher quality metal oxides have been grown on oxide substrates such as bulk strontium titanate. Metal oxides grown on oxide substrates are often expensive, in part because oxide substrates are small and expensive.
如果大面积的高质量单晶金属氧化物材料薄膜可以便宜地得到,那末与在金属氧化物材料的块状晶片上或者在氧化物材料的块状晶片上这种材料的外延膜中制造半导体器件的成本相比,可以利用该膜有利地制造各种便宜的半导体器件。此外,如果在块状晶片例如硅晶片上可以得到高质量单晶金属氧化物材料的薄膜,那末可以得到集成的半导体结构,该结构利用硅和金属氧化物材料两者的最好性能。If large-area, high-quality thin films of single-crystal metal-oxide materials are inexpensively available, there is no comparison between fabricating semiconductor devices on bulk wafers of metal-oxide materials or in epitaxial films of such materials on bulk wafers of oxide materials. Compared with the cost of , various inexpensive semiconductor devices can be advantageously manufactured using this film. Furthermore, if thin films of high quality single crystal metal oxide materials are available on bulk wafers such as silicon wafers, integrated semiconductor structures can be obtained which utilize the best properties of both silicon and metal oxide materials.
据此,需要一种微电子结构和用于制造该结构的方法,该结构提供了在另一种单晶材料之上的高质量单晶金属氧化物膜。Accordingly, there is a need for a microelectronic structure and method for fabricating the structure that provides a high quality single crystal metal oxide film on another single crystal material.
附图的简要描述Brief description of the drawings
下面以例子方式参照附图而不是限制来说明本发明,其中相同的参考标号表示类似的部件,其中:The present invention is illustrated below by way of example and not limitation with reference to the accompanying drawings, in which like reference numerals indicate similar parts, in which:
图1-3示意性地示出了根据本发明各个实施例的器件结构的截面;1-3 schematically illustrate cross-sections of device structures according to various embodiments of the present invention;
图4示出了可得到的最大膜厚与基质晶体和生长的晶体覆盖层(overlayer)之间的晶格错配之间的关系曲线图。Figure 4 shows a graph of the maximum achievable film thickness versus the lattice mismatch between the host crystal and the growing crystal overlayer.
技术人员应理解,为了简化和清楚,图中示出的部件没有必要按比例绘制。例如,图中的一些部件可以相对于其它的部件放大,以便帮助理解本发明的实施例。The skilled artisan will appreciate that for simplicity and clarity, components shown in the figures have not necessarily been drawn to scale. For example, some of the elements in the figures may be exaggerated relative to other elements to help to understand the embodiments of the present invention.
附图的详细描述Detailed description of the drawings
图1示意性地示出了根据本发明实施例的微电子结构20的部分截面。微电子结构20包含单晶衬底22、包括单晶材料的调节(accommodating)缓冲层24和单晶金属氧化物材料层26。在上下文中,术语“单晶”应具有半导体工业内通用的含义。该术语指的应是半导体工业中经常使用的单晶材料或者基本上是单晶的材料,并且应包含具有相对少量的缺陷例如位错等的材料,这些缺陷在硅或锗或硅和锗的混合物的衬底以及这些材料的外延层中是常见的。FIG. 1 schematically shows a partial cross-section of a
根据本发明的一个实施例,结构20还包含位于衬底22和调节缓冲层24之间的非晶中间层28。结构20还包含调节缓冲层和单晶氧化物层26之间的模板30。如下面将更全面地说明的,模板帮助开始调节缓冲层上金属氧化物层的生长。非晶中间层帮助缓解调节缓冲层中的应变,借此,帮助高质量的调节缓冲层的生长。According to an embodiment of the present invention, the
根据本发明的实施例,衬底22是单晶半导体晶片,大直径较好。该晶片可以是元素周期表中的IV族材料,优选IVA族材料。IV族半导体材料的例子包含硅;锗;混合的硅和锗;混合的硅和碳;混合的硅、锗和碳等。衬底22还可以是化合物半导体材料。根据具体的半导体结构的需要,衬底22的化合物半导体材料选自下面的任何一种:IIIA和VA族元素(III-V半导体化合物);混合的III-V化合物、II族(A或者B)和VIA元素(II-VI半导体化合物)以及混合的II-VI化合物。例子包含砷化镓(GaAs)、砷化铟镓(GaInAs)、砷化铝镓(GaAlAs)、磷化铟(InP)、硫化镉(CdS)、碲化汞镉(CdHgTe)、硒化锌(ZnSe)、硒化硫锌(ZnSSe)等。According to an embodiment of the invention,
较好的是,衬底22是包含硅或者锗的晶片,最好是用在半导体工业中的高质量单晶硅晶片。调节缓冲层24是外延生长在下伏衬底上的单晶氧化物或者氮化物材料较好。根据本发明的一个实施例,在层24生长过程中,通过衬底22的氧化,非晶中间层28生长在衬底22上衬底22和生长的调节缓冲层之间的界面处。非晶中间层起到缓解应变的作用,否则该应变会由于衬底和缓冲层的晶格常数不同而出现在单晶调节缓冲层中。这里所使用的晶格常数指的是在表面的平面中测得的晶胞的原子之间的距离。如果这种应变不通过非晶中间层缓解,该应变会引起调节缓冲层的晶体结构缺陷。结果,调节缓冲层的晶体结构缺陷将使其难以在单晶金属氧化物层26中得到高质量的晶体结构。Preferably,
调节缓冲层24是根据其与下伏的衬底和上覆的金属氧化物材料的晶体兼容性而选择的单晶氧化物或者氮化物材料较好。例如,该材料可以是具有与衬底和后来形成的金属氧化物材料匹配的晶格结构的氧化物或者氮化物。适用于调节缓冲层的材料包含:金属氧化物,例如碱土金属钛酸盐、碱土金属锆酸盐、碱土金属铪酸盐、碱土金属钽酸盐、碱土金属钌酸盐、碱土金属铌酸盐、碱土金属钒酸盐;钙钛矿氧化物,例如碱土金属锡基钙钛矿、铝酸镧、镧钪氧化物和氧化钆。此外,各种氮化物也可以用于调节缓冲层,例如氮化镓、氮化铝和氮化硼。尽管例如钌酸锶是导体,但这些材料中的大部分是绝缘体。通常,这些材料是金属氧化物或者金属氮化物,更具体地说,这些金属氧化物或者氮化物一般包含至少两种不同的金属元素。在一些具体的应用中,该金属氧化物或者氮化物可以包含三种或者更多中不同的金属元素。
非晶界面层28最好是由衬底22的表面氧化形成的氧化物构成,由氧化硅构成更好。层28的厚度足以缓解由于衬底22和调节缓冲层24的晶格常数之间的不匹配造成的应变。通常,层28的厚度为约0.5-5纳米。The
根据具体结构或者应用的需要,可以选择层26的金属氧化物材料。例如,层26可以包含具有希望特性的金属氧化物材料,例如显示压电、热电、铁磁、巨磁阻或者超导特性的材料。这种材料包含单斜的、四方的、立方的或者钙钛矿的金属氧化物结构,具有化学通式:ABO3,其中A选自由铅、镧、铌、钪及其组合构成的组,B选自由锆、钛、及其组合构成的组:(Pb,La,Na,Sc)(Zr,Ti)O3,例如,PbZrTiO3、PbNbZrTiO3、PbScZrTiO3、PbSrNbZrTiO3、PbLiZrTiO3、PbTiO3;ABO3,其中A选自由锶、钡、钙及其组合构成的组,B选自由锆、铪、钛及其组合构成的组:(Sr,Ba,Ca)(Zr,Hf,Ti)O3,例如,SrTiO3、BaTiO3、BaSrTiO3、CaTiO3、BaZrO3;ACoO3,其中A选自镧、锶、钡、锆及其组合:(La,Sr,Ba,Zr)CoO3,例如,LaSrCoO3、LaZrCoO3;ABMnO3,其中A是稀土元素(例如镧),B是碱土金属元素(例如钙、钡或锶):(La,Sr,Ba,Ca)MnO3,例如LaSrMnO3、LaCaMnO3;ABa2Cu3On,其中A选自钇、镨及其组合,n是7或8:(Y,Pr)Ba2Cu3O7-8,例如YBa2Cu3O、YPrBa2Cu3O;ARuO3,其中A选自锶、钡及其组合:(Sr,Ba)RuO3;PbAO3,其中A选自镁、铌及其组合:Pb(Mg,Nb)O3;GdFeO3;YAlO3;LaAlO3;SrVO3;SrCrO3;BaAO3,其中A选自铅、铋及其组合:Ba(Pb,Bi)O3;LaCoO3;KNbO3;NaWO3;Bi4Ti3O12;YMnO3;和LaAO3,其中A选自铝、钪及其组合:La(Al,Sc)O3。The metal oxide material of
在选择的位置,适当的模板材料化学结合到调节缓冲层24表面,为接续的金属氧化物层26的外延生长提供晶核形成的位置。当使用时,模板层30具有大约1-10个单层的厚度。At selected locations, an appropriate template material chemically binds to the surface of
图2显示了根据本发明更进一步的实施例的微电子结构40的部分截面图。结构40与前面描述的结构20类似,除了使附加的缓冲层32位于调节缓冲层24和单晶金属氧化物材料层26之间。具体地说,附加的缓冲层位于可选择的模板30(如果没有模板,那末就是层24)和单晶金属氧化物材料覆盖层之间。当调节缓冲层的晶格常数与覆盖的金属氧化物材料层不能适当地匹配时,由单晶氧化物材料形成的附加缓冲层起到提供晶格补偿的作用。FIG. 2 shows a partial cross-sectional view of a
图3示意性地显示了根据本发明另一个仿效实施例的微电子结构34的部分截面图。结构34与结构20类似,除了结构34包含非晶层36和附加的金属氧化物层38,而不包含调节缓冲层24和非晶界面层28。FIG. 3 schematically shows a partial cross-sectional view of a microelectronic structure 34 according to another exemplary embodiment of the present invention. Structure 34 is similar to structure 20 except that structure 34 includes amorphous layer 36 and additional metal oxide layer 38 instead of tuning
如下面更详细描述的,按照与上述方式类似的方式可以通过首先形成调节缓冲层和非晶界面形成非晶层36。然后(通过外延生长)形成单晶金属氧化物层38,覆盖单晶调节缓冲层。然后将调节缓冲层暴露于退火工艺,以便将单晶调节缓冲层转变为非晶层。按该方式形成的非晶层36包括来自调节缓冲层和界面层的材料,该非晶层可以合并(amalgamate)或者可以不合并。这样,层36可以包括一个或者两个非晶层。在衬底22和金属氧化物层38(层38的形成后)之间非晶层36的形成缓解了层22和38之间的应力,为后续的工艺例如金属氧化物层26的形成提供了真正适用的衬底。As described in more detail below, the amorphous layer 36 may be formed by first forming the adjustment buffer layer and the amorphous interface in a manner similar to that described above. A single crystal metal oxide layer 38 is then formed (by epitaxial growth) overlying the single crystal conditioning buffer layer. The conditioning buffer layer is then exposed to an annealing process to convert the single crystal conditioning buffer layer into an amorphous layer. The amorphous layer 36 formed in this manner includes material from the conditioning buffer layer and the interfacial layer, which may or may not be amalgamate. Thus, layer 36 may comprise one or two amorphous layers. The formation of the amorphous layer 36 between the
上面结合图1和2描述的工艺适于在单晶衬底上生长单晶金属氧化物层。然而,包含将单晶调节缓冲层转换为非晶氧化物层、结合图3描述的工艺对于生长单晶金属氧化物层来说可能更好,因为它允许在形成层26之前缓解了层38中任何应变。The process described above in connection with Figures 1 and 2 is suitable for growing a single crystal metal oxide layer on a single crystal substrate. However, the process described in conjunction with FIG. 3 , which includes converting the single-crystal conditioning buffer layer to an amorphous oxide layer, may be better for growing a single-crystal metal oxide layer because it allows for the relaxation of the crystalline layer in layer 38 prior to forming
金属氧化物层38可以包含在本申请中结合金属氧化物层26或者附加的缓冲层32描述的任何材料。例如,层38可以包含上面列出的适用于层26的钙钛矿金属氧化物。Metal oxide layer 38 may comprise any of the materials described herein in connection with
根据本发明的一个实施例,层38作为层36形成过程中的退火盖层(anneal cap)和用于后续的金属氧化物层26形成的模板。据此,层38最好足够厚,以便提供适合层26生长的模板(至少一个单层),并且足够薄,以便允许层38形成为基本上没有缺陷的单晶金属氧化物(经常少于大约10个单层)。According to one embodiment of the present invention, layer 38 acts as an anneal cap during the formation of layer 36 and as a template for the subsequent formation of
根据本发明的另一个实施例,单晶金属氧化物层38包括金属氧化物材料(例如上面结合层26讨论的材料),该层足够厚以便使用用于希望的微电子器件的膜。在这种情况下,根据本发明的微电子结构不包含层26。换句话说,根据该实施例的微电子结构仅包含设置在非晶氧化物层36上的一个金属氧化物层。According to another embodiment of the present invention, single crystal metal oxide layer 38 comprises a metal oxide material (such as the material discussed above in connection with layer 26) that is thick enough to use the film for the desired microelectronic device. In this case, the microelectronic structure according to the invention does not contain
下面非限定的、说明性的例子说明了根据本发明的各个可选择的实施例、可用于结构20、40和34的材料的各种组合。这些例子仅是说明性的,本发明不仅限于这些说明性的例子。The following non-limiting, illustrative examples illustrate various combinations of materials that may be used for
例1example 1
根据本发明的一个实施例,单晶衬底22是在(100)方向上定向的硅衬底。该硅衬底例如可以是通常用来制造大约200-300mm直径的互补金属氧化物半导体(CMOS)集成电路的硅衬底。根据本发明的该实施例,调节缓冲层24是SrzBa1-zTiO3的单晶层,其中z从0-1,非晶中间层是形成在硅衬底和调节缓冲层之间的界面处的氧化硅(SiOx)层。选择z的值以便得到与接着形成的层26的晶格常数紧密配合的一个或者多个晶格常数。调节缓冲层可以具有大约2-100纳米(nm)的厚度,最好具有大约10nm的厚度。总之,希望调节缓冲层足够厚以便隔离金属氧化物层和衬底,得到希望的特性。比100nm厚的层通常几乎不能提供附加的好处,同时增加了不必要的成本。然而,如果需要可以制造更厚的层。氧化硅的非晶中间层可以具有大约0.5-5nm的厚度,最好具有大约1.5-2.5nm的厚度。According to one embodiment of the present invention,
根据本发明的该实施例,金属氧化物材料层26是钌酸锶(SrRuO3)层,具有大约5-500nm的厚度,最好具有大约10-100nm的厚度。该厚度通常根据该层准备作何用而定。According to this embodiment of the invention, the metal
例2Example 2
根据本发明的另一个实施例,提供一种结构,该结构适于覆盖硅衬底的外延膜(Pb,La,Nb,Sc)(Zr,Ti)O3膜的生长。该衬底最好是如上所述的硅晶片。适合的调节缓冲层材料是SrxBa1-xTiO3,其中x从0-1,具有大约2-100nm的厚度,最好具有大约5-15nm的厚度。金属氧化物材料例如可以是PbZrTiO3,具有大约50-500nm的厚度。According to another embodiment of the present invention, there is provided a structure suitable for the growth of an epitaxial (Pb, La, Nb, Sc) (Zr, Ti) O3 film covering a silicon substrate. The substrate is preferably a silicon wafer as described above. A suitable adjustment buffer layer material is Srx Ba1-x TiO3 , where x ranges from 0-1, with a thickness of about 2-100 nm, preferably about 5-15 nm. The metal oxide material may be, for example, PbZrTiO3 , with a thickness of about 50-500 nm.
再参考图1-3,衬底22是单晶衬底,例如单晶硅或者砷化镓衬底。单晶衬底的晶体结构由晶格常数和晶格定向来表征。同样,调节缓冲层24也是单晶材料,该单晶材料的晶格由晶格常数和晶体定向表征。调节缓冲层和单晶衬底的晶格常数必须紧密配合,或者必须使当一个晶体定向相对于另一个晶体定向旋转时实现晶格常数基本匹配。在该文中“基本相等”和“基本匹配”的含义是晶格常数之间充分类似,以便允许在底层上生长高质量的晶体层。Referring again to FIGS. 1-3 , the
图4绘出了可以得到的高结晶质量的晶体生长层的膜厚作为基质晶体和生长晶体的晶格常数之间的失配的函数关系曲线图。曲线42说明了高结晶质量材料的边界。曲线42的右侧区域代表趋向多晶的层。没有晶格不匹配,理论上能够在基质晶体上生长无限厚、高质量的外延层。随着晶格常数不匹配的增加,可以得到的、高质量结晶层的厚度迅速减小。作为参考点,例如,如果基质晶体和生长层之间的晶格常数失配大于约2%,那末不能得到超过大约20nm的单晶外延层。Figure 4 plots the film thickness of achievable crystal growth layers of high crystalline quality as a function of the mismatch between the lattice constants of the host crystal and the growing crystal.
根据本发明的一个实施例,衬底22是(100)或者(111)定向的单晶硅晶片,调节缓冲层24是钛酸锶钡层。通过将钛酸盐材料的晶体取向相对于硅衬底晶片的晶体取向旋转45°实现这两个材料之间晶格常数的基本匹配。如果足够厚,包含在所述结构中的非晶界面层28(在该例中是氧化硅层)起到减小钛酸盐单晶层中的应变的作用,该应变可能是由于基质硅晶片和生长的钛酸盐层的晶格常数的任何不匹配造成的。结果,根据本发明的一个实施例,可以得到高质量的、厚的、单晶钛酸盐层。According to an embodiment of the present invention, the
仍然参考图1-3,层26是外延生长的金属氧化物材料层,并且结晶材料也由晶体的晶格常数和晶体定向表征。根据本发明的一个实施例,层26的晶格常数不同于衬底22的晶格常数。为了在该外延生长的单晶层中得到高的结晶质量,调节缓冲层必须具有高的结晶质量。此外,为了在层26中实现高的结晶质量,希望在基质晶体(此时为单晶调节缓冲层)和生长的晶体之间的晶格常数之间基本匹配。通过适当选择材料,作为生长晶体的晶体取向相对于基质晶体的取向旋转的结果,实现了晶格常数的基本匹配。在有些情况下,可以使用基质氧化物和生长的金属氧化物层之间的结晶缓冲层来减小生长的单晶金属氧化物层中由晶格常数的微小不同而导致的应变。从而可以在生长的单晶金属氧化物层中得到更好的结晶质量。Still referring to FIGS. 1-3 ,
下面的例子说明了根据本发明一个实施例的方法,该方法用于制造如图1-3所描述微电子结构。该方法由提供包括硅或者锗的单晶半导体衬底开始。根据本发明的最佳实施例,半导体衬底是具有(100)取向的硅晶片。该衬底最好定向在轴上,或者至多偏移轴大约0.5°。尽管如下所述半导体衬底的其它部分可以包括其它结构,但至少半导体衬底的一部分具有裸露的表面。在上下文中术语“裸露”指的是已经清洁了衬底的一部分表面以便除去任何氧化物、污染物或者其它外来材料。众所周知,裸露的硅是易反应的并且容易形成本身的氧化物。术语“裸露”意指包括这种本身氧化物。薄的氧化硅还可以故意生长在半导体衬底上,尽管这种生长的氧化物不是根据本发明的工艺必须的。为了外延生长覆盖单晶衬底的单晶氧化物层,必须首先除去本身的氧化物层以便露出下方衬底的晶体结构。尽管根据本发明可以使用其它的外延工艺,但最好通过分子束外延生长(MBE)进行下面的工艺。首先可以通过在MBE装置中热淀积锶、钡、锶和钡的组合、其它碱土金属或碱土金属的组合的薄层除去该本身氧化物。在使用锶的情况下,然后将衬底加热到大约750℃的温度,以便使锶和本身的氧化硅层反应。锶起到减少氧化硅以便留下没有氧化硅的表面。所得到的表面表现为有序的2×1结构,该表面包含锶、氧和硅。有序的2×1结构形成了用于单晶氧化物的覆盖层有序生长的模板。该模板提供需要的化学和物理特性,以便成为覆盖层的结晶生长的核。The following example illustrates a method according to one embodiment of the present invention for fabricating microelectronic structures as depicted in FIGS. 1-3. The method begins by providing a single crystal semiconductor substrate comprising silicon or germanium. According to a preferred embodiment of the invention, the semiconductor substrate is a silicon wafer having a (100) orientation. The substrate is preferably oriented on-axis, or at most about 0.5° off-axis. At least a portion of the semiconductor substrate has an exposed surface, although other portions of the semiconductor substrate may include other structures as described below. The term "bare" in this context means that a portion of the surface of the substrate has been cleaned to remove any oxides, contaminants or other foreign material. It is well known that bare silicon is reactive and readily forms its own oxide. The term "bare" is meant to include such native oxides. Thin silicon oxide can also be deliberately grown on the semiconductor substrate, although such a grown oxide is not necessary for the process according to the invention. In order to epitaxially grow a single crystal oxide layer covering a single crystal substrate, the oxide layer itself must first be removed in order to expose the crystalline structure of the underlying substrate. Although other epitaxial processes may be used in accordance with the present invention, the following processes are preferably performed by molecular beam epitaxy (MBE). The native oxide can first be removed by thermally depositing a thin layer of strontium, barium, a combination of strontium and barium, other alkaline earth metals or a combination of alkaline earth metals in an MBE apparatus. In the case of strontium, the substrate is then heated to a temperature of about 750° C. in order to react the strontium with the native silicon oxide layer. Strontium acts to reduce the silicon oxide to leave a silicon oxide free surface. The resulting surface exhibits an ordered 2×1 structure comprising strontium, oxygen and silicon. The ordered 2 × 1 structure forms a template for the ordered growth of capping layers of single-crystal oxides. This template provides the required chemical and physical properties in order to be the nucleus for the crystalline growth of the capping layer.
根据本发明的另一个实施例,可以使本身的氧化硅转变,并且可以在低温利用MBE将碱土金属氧化物例如氧化锶、氧化锶钡或氧化钡淀积到衬底表面上、接着将该结构加热到大约750℃的温度,制备用于单晶氧化物层生长的衬底表面。在该温度,在氧化锶和该本身的氧化硅之间发生固态反应,引起该本身的氧化硅减少,留下有序的2×1结构,锶、氧和硅留在衬底的表面上。这样也形成了用于有序的单晶氧化物层后续生长的模板。According to another embodiment of the present invention, the native silicon oxide can be transformed and an alkaline earth metal oxide such as strontium oxide, strontium barium oxide or barium oxide can be deposited on the substrate surface at low temperature using MBE, followed by the structure Heating to a temperature of approximately 750°C prepares the substrate surface for growth of a single crystal oxide layer. At this temperature, a solid state reaction occurs between the strontium oxide and the native silicon oxide, causing the native silicon oxide to decrease, leaving an ordered 2x1 structure with strontium, oxygen and silicon remaining on the surface of the substrate. This also forms a template for the subsequent growth of the ordered single crystal oxide layer.
根据本发明的一个实施例,从衬底表面上除去氧化硅之后,将衬底冷却到大约200-800℃的温度,利用分子束外延生长在模板上生长钛酸锶层。通过打开MBE装置中的窗板(shutters)以便露出锶、钛和氧源启动MBE工艺。锶和钛的比大约为1∶1。氧的分压最初设定在最小值,以便在大约0.3-0.5nm每分钟的生长速度下生长化学计量比的钛酸锶。钛酸锶的最初生长之后,将氧分压增加到高于最初的最小值。氧的过压导致在下方衬底和正在生长的钛酸锶层之间的界面处生长非晶氧化硅层。氧化硅层的生长来源于氧扩散通过正在生长的钛酸锶层到达下方衬底表面处的界面,在该界面氧与硅反应。钛酸锶生长为有序的单晶,结晶取向相对于下方衬底的有序2×1晶体结构旋转45°。在非晶氧化硅中间层中,缓解了由于硅衬底和正在生长的晶体之间晶格常数的微小不匹配而可能存在于钛酸锶层中应变。According to one embodiment of the present invention, after silicon oxide is removed from the substrate surface, the substrate is cooled to a temperature of about 200-800° C., and a strontium titanate layer is grown on the template by molecular beam epitaxy. The MBE process was started by opening the shutters in the MBE apparatus to expose the strontium, titanium and oxygen sources. The ratio of strontium to titanium is approximately 1:1. The partial pressure of oxygen was initially set at a minimum value to grow stoichiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After the initial growth of strontium titanate, the oxygen partial pressure was increased above the initial minimum. The overpressure of oxygen causes the growth of an amorphous silicon oxide layer at the interface between the underlying substrate and the growing strontium titanate layer. The growth of the silicon oxide layer results from the diffusion of oxygen through the growing strontium titanate layer to the interface at the underlying substrate surface where the oxygen reacts with the silicon. Strontium titanate grows as an ordered single crystal with a crystallographic orientation rotated by 45° relative to the ordered 2×1 crystal structure of the underlying substrate. In the amorphous silicon oxide interlayer, the strain that may exist in the strontium titanate layer due to the slight mismatch in lattice constant between the silicon substrate and the growing crystal is relieved.
钛酸锶层已经生长到希望的厚度之后,可以利用模板覆盖单晶钛酸锶层,这有益于希望的金属氧化物材料外延层的后续生长。例如,可以通过使具有钛的1-2单层、钛-氧的1-2单层或者锶-氧的1-2单层终结所述生长盖住钛酸锶单晶层的MBE生长。模板形成之后(如果形成了一个),利用MBE或者其它适当的技术生长金属氧化物材料。After the strontium titanate layer has grown to the desired thickness, the single crystal strontium titanate layer can be covered with a template, which facilitates the subsequent growth of the desired epitaxial layer of metal oxide material. For example, MBE growth of a strontium titanate single crystal layer can be capped by terminating the growth with a 1-2 monolayer of titanium, a 1-2 monolayer of titanium-oxygen, or a 1-2 monolayer of strontium-oxygen. After the template is formed (if one is formed), the metal oxide material is grown using MBE or other suitable technique.
可以通过上面讨论的方法形成图2所示的结构,添加附加的缓冲层淀积步骤。在淀积单晶金属氧化物层之前形成缓冲层,覆盖模板或者调节缓冲层。如果缓冲层是氧化物超晶格,例如,可以利用MBE在上述模板上淀积这种超晶格。The structure shown in Figure 2 can be formed by the methods discussed above, adding an additional buffer layer deposition step. A buffer layer is formed before depositing the single crystal metal oxide layer, covering the template or adjusting the buffer layer. If the buffer layer is an oxide superlattice, such a superlattice can be deposited on the above-mentioned template using MBE, for example.
可以如上所述通过生长调节缓冲层在衬底22上形成非晶氧化物层和通过在调节缓冲层上生长金属氧化物层38形成如图3所示的结构34。然后将调节缓冲层和非晶氧化物层暴露于退火工序,该退火工序足以将调节缓冲层的晶体结构从单晶变为非晶,从而形成非晶层,使得非晶氧化物层和新的非晶调节缓冲层的组合形成单一的非晶氧化物层36。然后在层38上生长层26。或者可以在层26生长之后进行退火工序。Forming the amorphous oxide layer on the
根据该实施例的一个方面,通过将衬底22、调节缓冲层、非晶氧化物层和层38暴露于快速热退火工艺形成层36,所述快速热退火工艺具有大约700-1000℃的峰值温度和大约10秒至10分钟的处理时间。然而,可以采用其它适当的退火工艺以便根据本发明将调节缓冲层转变为非晶层。例如,可以采用激光退火或者“常规”热退火工艺(在适当的环境中)以便形成层36。当采用常规的热退火以便形成层36时,可能需要层30的一个或者多个成份的过压,以便防止在退火工艺过程中层38的退化。According to one aspect of this embodiment, layer 36 is formed by exposing
如上所述,结构34的层38可以包含适用于层32或者26的任何材料。据此,可以采用与层32或26有关的任何淀积或生长方法,以便淀积层38。As noted above, layer 38 of structure 34 may comprise any material suitable for
上述方法说明了用于通过分子束外延工艺形成半导体结构的方法,所述半导体结构包含硅衬底、覆盖氧化物层和单晶金属氧化物层。该方法还可以通过下列工艺进行:化学汽相淀积(CVD)、金属有机化学汽相淀积(MOCVD)、迁移增强外延(MEE)、原子层外延(ALE)、物理汽相淀积(PVD)、化学溶液淀积(CSD)、脉冲激光淀积(PLD)等。此外,通过类似的工艺,还可以生长其它单晶调节缓冲层例如碱土金属钛酸盐、锆酸盐、铪酸盐、钽酸盐、钒酸盐、钌酸盐和铌酸盐;钙钛矿氧化物例如碱土金属锡基钙钛矿、铝酸镧、氧化镧钪和氧化钆。此外,通过类似的工艺例如MBE,可以淀积其它的金属氧化物层,覆盖单晶氧化物调节缓冲层。例如,可以通过用准分子激光烧蚀希望材料的靶并加热衬底到大约300-500℃的温度下,通过PLD生长金属氧化物。The methods described above illustrate methods for forming a semiconductor structure comprising a silicon substrate, a capping oxide layer, and a single crystal metal oxide layer by a molecular beam epitaxy process. The method can also be carried out by the following processes: Chemical Vapor Deposition (CVD), Metal Organic Chemical Vapor Deposition (MOCVD), Migration Enhanced Epitaxy (MEE), Atomic Layer Epitaxy (ALE), Physical Vapor Deposition (PVD) ), chemical solution deposition (CSD), pulsed laser deposition (PLD), etc. In addition, other single-crystal regulatory buffer layers such as alkaline earth metal titanates, zirconates, hafnates, tantalates, vanadates, ruthenates, and niobates can be grown by similar processes; perovskite Oxides such as alkaline earth tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. In addition, other metal oxide layers can be deposited by a similar process such as MBE, covering the single crystal oxide conditioning buffer layer. For example, metal oxides can be grown by PLD by ablating a target of the desired material with an excimer laser and heating the substrate to a temperature of about 300-500°C.
金属氧化物材料和单晶氧化物调节缓冲层的每种变化可以使用适当的用于启动各个层生长的模板。在这种情况下,可以根据上面联系生长层26所描述方法生长适当的模板材料。Each variation of metal oxide material and single crystal oxide conditioning buffer layer can use an appropriate template for initiating the growth of the respective layer. In this case, a suitable template material can be grown according to the method described above in connection with
在前面的说明中,已经参考具体实施例描述了本发明。然而,本领域技术人员应理解,如在下面权利要求中提出的,在不离开本发明的范围的情况下可以作出各种修改和变化。据此,应将说明书和附图看作是说明性的而不是限定性的。所有的这些修改都应包含在本发明的范围内。In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive. All such modifications are intended to be included within the scope of this invention.
上面已经根据具体实施例描述了利益、其它优点和问题的解决方案。然而,利益、优点、解决问题的技术方案以及将出现或变得更显著的任何会带来任何利益、优点或技术方案的要素(element)都不应解释为任何或所有权利要求的临界的、需要的或必要的技术特征或要素。这里所使用的术语“包括”或其任何其它变化都应指的是非排外的包含,使得包括要素清单的工艺、方法、制品或装置不仅包含这些要素,而且可以包含没有列出清单的或者这些工艺、方法、制品或装置固有的其它要素。Benefits, other advantages, and solutions to problems have been described above in terms of specific embodiments. However, benefits, advantages, technical solutions to problems and any elements (elements) that will appear or become more significant that will bring any benefits, advantages or technical solutions should not be interpreted as critical, A desired or necessary technical feature or element. As used herein, the term "comprises" or any other variation thereof shall mean a non-exclusive inclusion such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also non-listed or such processes. , method, article or other element inherent in the device.
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| JP2004505444A (en) | 2004-02-19 |
| WO2002009159A3 (en) | 2002-04-25 |
| AU2001276989A1 (en) | 2002-02-05 |
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| Date | Code | Title | Description |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |