CN1442891A - Soft package structure and manufacturing method thereof - Google Patents

Abstract

The invention relates to a soft package structure and a manufacturing method thereof, in particular to a soft package structure which can simultaneously complete the manufacturing of a soft chip package substrate and the automatic bonding of inner pins and a manufacturing method thereof, mainly comprising the following steps: providing a substrate, forming a patterned circuit preset with inner pins, outer pins, test circuits or test terminals on the surface of the substrate in an electroplating way, covering a polyimide protective film or soft solder resist protective paint on the upper part of the patterned circuit except the inner pins, then carrying out relative hot-pressing combination on bumps on an IC wafer which is subjected to bumping operation and the inner pins of the patterned circuit, finally removing the substrate, and covering the polyimide protective film or the soft solder resist protective paint outside the outer pin area below the patterned circuit. The structure and the method can reduce the manufacturing cost, simplify the process and improve the product percent of pass.

Description

Translated fromChinese

软式封装构造及其制作方法Soft package structure and manufacturing method thereof

技术领域technical field

本发明系有关于一种软式封装构造及制作方法，尤指一种可同时完成软式晶片封装基板制作与内引脚自动接合的软式封装构造及制作方法。The present invention relates to a flexible packaging structure and manufacturing method, especially to a flexible packaging structure and manufacturing method that can simultaneously complete the manufacturing of the flexible chip packaging substrate and the automatic bonding of inner pins.

背景技术Background technique

随着集成电路(IC)制造技术的不断精进，在相同面积下的存储器容量系以几何级数态样增加，以力求符合产品轻、薄、短、小、功能强的设计理念。如今，0.18微米线宽的半导体元件已进入批量生产阶段，相对地，为防止外力环境因素损害或影响微小脆弱的IC元件，各种高密度的封装(Packaging)结构也因应而生，例如晶片尺寸构装技术(Chip ScalePackage CSP)。而IC元件必须与构装结构的电路连接才能发挥其既有的设计功能，因此在半导体封装结构中，其电性连接的技术好坏将可直接影响到IC元件的设计优劣。With the continuous improvement of integrated circuit (IC) manufacturing technology, the memory capacity under the same area is increasing geometrically, in order to meet the design concept of light, thin, short, small, and powerful products. Today, semiconductor components with a line width of 0.18 microns have entered the stage of mass production. Correspondingly, in order to prevent external forces and environmental factors from damaging or affecting tiny and fragile IC components, various high-density packaging (Packaging) structures have also emerged accordingly, such as chip size Construction technology (Chip ScalePackage CSP). However, IC components must be connected to the circuit of the structural structure to exert their existing design functions. Therefore, in the semiconductor package structure, the technical quality of its electrical connection will directly affect the design of the IC component.

而在各种IC元件电性连接技术中，软式卷带自动接合技术(TapeAutomated Bonding；TAB)技术由于具备有可提供高连线密度(引脚间距相对细微)、自动化的接合、组装前电性测试、及低制造成本的优点，因此普遍被使用于超大型集成电路、高速电子元件构装、航太、医学、及各种消费性电子产品中。Among various IC component electrical connection technologies, flexible tape automatic bonding technology (TapeAutomated Bonding; TAB) technology has the advantages of providing high connection density (relatively small pin pitch), automatic bonding, and electrical connection before assembly. Due to the advantages of permanent testing and low manufacturing cost, it is widely used in VLSI, high-speed electronic component assembly, aerospace, medical, and various consumer electronic products.

软式卷带自动接合技术(TAB)的制作流程主要是包括有：(1)制作一引脚化软式卷带，首先系于一聚亚醯胺(polyimide；PI)卷带上形成铜薄膜，并于铜薄膜上进行光阻及蚀刻等过程而于聚亚醯胺上形成传动孔(sprocket)、元件孔(devicehole)、及金属引脚图案；(2)完成一IC元件(晶片)的金属凸块化步骤(bumping process)；(3)将已个别完成的引脚化卷带及凸块化IC晶片连接，以完成内引脚接合步骤(InnerLead Bonding；ILB)；(4)进行封胶、电气特性测试；(5)将外引脚搭载到所欲驱动的元件上，以进行外引脚接合步骤(Outer Lead Bonding；OLB)；及(6)最后再进行元件的整合测试工作。The production process of flexible tape automatic bonding technology (TAB) mainly includes: (1) To make a pin-shaped flexible tape, first tie it to a polyimide (PI) tape to form a copper film , and carry out photoresist and etching processes on the copper film to form transmission holes (sprocket), component holes (devicehole), and metal pin patterns on the polyimide; (2) complete the design of an IC component (chip) Metal bumping process (bumping process); (3) Connect the pinned tapes and bumped IC chips that have been individually completed to complete the inner lead bonding step (InnerLead Bonding; ILB); (4) Packaging Glue and electrical characteristic test; (5) Mount the external lead on the component to be driven to perform the outer lead bonding step (Outer Lead Bonding; OLB); and (6) finally perform the integration test of the component.

而在上述制作流程中，由于内引脚接合步骤事关IC晶片是否可正常工作的重要关键，且引脚间的间距十分微细，制作上存在有相当的困难度，因此，如何改良内引脚的接合技术与结构也因此成为TAB可否被大量应用及批量生产的重要课题。In the above-mentioned manufacturing process, since the inner pin bonding step is an important key to whether the IC chip can work normally, and the spacing between the pins is very fine, there are considerable difficulties in manufacturing. Therefore, how to improve the inner pin Therefore, the bonding technology and structure of TAB has become an important issue whether TAB can be applied in large quantities and mass produced.

参阅图1A及图1B，系分别为一习用软式卷带自动接合技术(TAB)中内引脚接合制程的剖面示意图；如图所示，首先系提供一软式卷带(tapecarrier)15，软式卷带15主要是包括有复数个金属引脚153(trace)及一具绝缘功效的聚亚醯胺卷带层155，引脚153的一部分系经由蚀刻技术而形成于卷带层155的表面，而其另一部分则可裸露于卷带层155外。另外，再提供一IC晶片11，IC晶片11的上表面铺设有一钝态保护层(PassivationLayer)115，而在IC晶片11上表面表层设有复数个电极接垫(die pad)113，每一电极接垫113皆藉由一可穿透保护层115的金属凸块(bump)13而保持与外界电性连接。Referring to FIG. 1A and FIG. 1B , they are respectively schematic cross-sectional views of the internal pin bonding process in a conventional flexible tape automatic bonding technology (TAB); as shown in the figure, a flexible tape carrier (tapecarrier) 15 is first provided, Theflexible tape 15 mainly includes a plurality of metal pins 153 (trace) and apolyimide tape layer 155 with insulation function. A part of thepins 153 is formed on thetape layer 155 by etching technology. surface, while the other part may be exposed outside thetape layer 155 . In addition, anIC chip 11 is provided again, a passivation layer (PassivationLayer) 115 is laid on the upper surface of theIC chip 11, and a plurality of electrode pads (die pad) 113 are arranged on the upper surface layer of theIC chip 11, each electrode The pads 113 are electrically connected to the outside through ametal bump 13 that can penetrate theprotection layer 115 .

之后，分别将每一引脚153对准相对应的凸块13，利用一接合工具(热压头)17分别对凸块13及引脚153均匀加热及加压作动，致使每一凸块13可与相对应的引脚153接合，也因此IC晶片11内的电极接垫113将通过凸块13而与引脚153电性连接，以完成内引脚的接合步骤(ILB)，如图1B所示。After that, eachpin 153 is aligned with thecorresponding bump 13, and a bonding tool (thermal head) 17 is used to uniformly heat and press thebump 13 and thepin 153, so that eachbump 13 can be bonded to thecorresponding pin 153, and therefore the electrode pad 113 in theIC chip 11 will be electrically connected to thepin 153 through thebump 13 to complete the inner pin bonding step (ILB), as shown in the figure 1B.

惟，在上述习用TAB的内引脚制程中，由于每一引脚153的宽度极为细微，使得引脚153极易受到外力的影响而扭曲，徒增引脚153与相对应凸块13的对准压合困难度；另外，每一凸块13的高度亦或有不同，需将凸块13的高度控制在极小的误差内，否则引脚153与凸块13的接合信赖度将降低，对产品品保上有其一定的麻烦；又，还必须精准地均匀加热及加压于凸块13及引脚153上，才能确保两者间的接合品质；又，凸块13与引脚153上的焊料清洁度也是影响接合效果良好与否的重要因素。However, in the conventional TAB internal pin manufacturing process, since the width of eachpin 153 is extremely small, thepin 153 is easily distorted by external force, which increases the relative distance between thepin 153 and thecorresponding bump 13. Difficulty of quasi-pressing; in addition, the height of eachbump 13 may also be different, and the height of thebump 13 must be controlled within a very small error, otherwise the bonding reliability between thepin 153 and thebump 13 will be reduced. There is a certain amount of trouble for product quality assurance; in addition, it is necessary to precisely and evenly heat and pressurize thebump 13 and thepin 153 to ensure the bonding quality between the two; and, thebump 13 and thepin 153 The cleanliness of the solder on the surface is also an important factor affecting whether the bonding effect is good or not.

针对上述习用TAB内引脚制程的种种缺憾，业界又发展出软式晶片模组技术(chip on film；COF)，COF技术具有比TAB技术更轻、更薄、引脚间距更细微的特征，因此近年来在半导体封装技术领域中备受关注。In response to the various shortcomings of the conventional TAB internal pin manufacturing process, the industry has developed chip on film (COF) technology. COF technology has the characteristics of being lighter, thinner, and finer pin spacing than TAB technology. Therefore, it has attracted much attention in the field of semiconductor packaging technology in recent years.

参阅图2A及图2B，系分别为一习用软式晶片模组技术(COF)中内引脚接合制程的剖面示意图；如图所示，首先系提供一软式基板(film)25，该软式基板25主要系包括有复数个金属引脚253及一具有绝缘效果由聚亚醯胺材质制成的卷带255，其中弓脚253系贴附于卷带255的下表面上。另外，再提供一IC晶片21，IC晶片21的上表面铺设有一钝态保护层215，而在IC晶片21的上表面表层设有复数个电极接垫213，每一电极接垫213皆藉由一可穿透保护层215的金属凸块23而保持与外界电性连接。Referring to FIG. 2A and FIG. 2B , they are schematic cross-sectional views of the internal pin bonding process in a conventional chip-on-chip (COF) technology; Thetype substrate 25 mainly includes a plurality ofmetal pins 253 and areel 255 made of polyimide material with insulating effect, wherein thebow 253 is attached to the lower surface of thereel 255 . In addition, anIC chip 21 is provided again, apassivation protection layer 215 is laid on the upper surface of theIC chip 21, and a plurality ofelectrode pads 213 are arranged on the upper surface of theIC chip 21, and eachelectrode pad 213 is connected byA metal bump 23 penetrating theprotection layer 215 maintains electrical connection with the outside.

再者，于金属引脚253的下表面贴附一异方性导电膜(Anti-isotropicConductive Film；ACF)或异方性导电胶(Anti-isotropic ConductivePaste；ACP)的导电层257，接续再分别将每一引脚253对准相对应的凸块23，利用一接合工具(热压头)27分别对凸块23及引脚253均匀加热及加压作动，致使每一凸块23可与相对应的引脚253接合，也因此IC晶片21内的电极接垫213将通过凸块23及导电层257而与引脚253电性连接，以完成内引脚的接合步骤(ILB)，如图2B所示。Furthermore, aconductive layer 257 of an anisotropic conductive film (Anti-isotropic Conductive Film; ACF) or an anisotropic conductive paste (Anti-isotropic Conductive Paste; ACP) is pasted on the lower surface of themetal pin 253, and then respectively Eachpin 253 is aligned with thecorresponding bump 23, and a bonding tool (thermal head) 27 is used to uniformly heat and press thebump 23 and thepin 253 respectively, so that eachbump 23 can be connected with the corresponding bump. Thecorresponding pins 253 are bonded, and therefore theelectrode pads 213 in theIC chip 21 will be electrically connected to thepins 253 through thebumps 23 and theconductive layer 257, so as to complete the bonding step (ILB) of the inner pins, as shown in the figure 2B.

在上述的习用软式晶片模组(COF)制程中，最关键的技术还是在于引脚253与凸块23的接合技术。由于每一引脚253的宽度极为细微，且卷带255的厚度远比TAB技术的卷带155低，因此引脚253受到热应力影响而位移的情况更为严重，致使每一引脚253与相对应凸块23对准压合更加不易；又，每一凸块23的高度、IC晶片21与凸块23的均匀加压加热、凸块23与引脚253上的焊料清洁度等影响因素还是如同TAB技术一般存在。再者，软式基板25的制造成本亦比软式卷带15高，且产品合格率相对偏低，因此直至现今COF技术并无法广泛且应用于批量生产中。In the above-mentioned conventional chip-on-flex (COF) process, the most critical technology lies in the bonding technology of thepins 253 and thebumps 23 . Since the width of eachpin 253 is extremely small, and the thickness of thetape 255 is much lower than that of thetape 155 of TAB technology, the displacement of thepin 253 is more serious due to the influence of thermal stress, causing eachpin 253 and It is more difficult to align and press thecorresponding bumps 23; and the height of eachbump 23, the uniform pressure and heating of theIC chip 21 and thebumps 23, the cleanliness of the solder on thebumps 23 and thepins 253, etc. It still exists like TAB technology. Furthermore, the manufacturing cost of theflexible substrate 25 is also higher than that of theflexible tape 15 , and the product yield is relatively low, so until now the COF technology cannot be widely used in mass production.

另外，不管是TAB技术中所使用的软式卷带或COF技术中所应用的软式基板皆为可弯折的软性材质所制成，所以在进行内引脚接合过程时需要很高的元件对准度，相对也就无形增加其制作时的困难度及成本支出。In addition, both the flexible tape used in the TAB technology and the flexible substrate used in the COF technology are made of bendable soft materials, so a high level of labor is required for the inner lead bonding process. The degree of component alignment relatively invisibly increases the difficulty and cost of its production.

发明内容Contents of the invention

有鉴于此，本发明提供一种可大幅降低制造成本、简化制作流程及提高产品合格率的软式封装结构及其制作方法。In view of this, the present invention provides a flexible packaging structure and a manufacturing method thereof that can greatly reduce manufacturing costs, simplify manufacturing processes, and improve product yield.

一种软式封装构造，其主要系包括有：一至少包括有内引脚的图案化线路；于该图案化线路的一表面上设有一保护膜；及于该图案化线路的另一表面部分区域设有一防焊保护漆。A flexible packaging structure, which mainly includes: a patterned circuit including at least inner leads; a protective film is provided on one surface of the patterned circuit; and the other surface part of the patterned circuit The area is provided with a solder resist protective paint.

一种软式封装构造的制作方法，其主要步骤系包括有：提供一基底；于该基底的部分上表面形成预设的图案化线路；提供一已完成凸块化的IC晶片，并将该IC晶片的凸块对准与其相对应的图案化线路，且致使凸块与相对应的图案化线路接合；及移除该基底，并形成一保护膜于图案化线路的其中一表面上。A method for manufacturing a flexible packaging structure, the main steps of which include: providing a base; forming a predetermined patterned circuit on a part of the upper surface of the base; providing a bumped IC chip, and placing the The bumps of the IC chip are aligned with the corresponding patterned lines, and the bumps are bonded with the corresponding patterned lines; and the substrate is removed, and a protective film is formed on one surface of the patterned lines.

上述制作方法，尚可包括有下列步骤：于图案化线路的表面形成一导电层，且藉由该导电层以致使IC晶片上的凸块与图案化线路电性连接。其中该导电层系可选择异方性导电膜(ACF)、异方性导电胶(ACP)及其组合式的其中之一所制成。The above manufacturing method may further include the following steps: forming a conductive layer on the surface of the patterned circuit, and using the conductive layer to electrically connect the bumps on the IC chip to the patterned circuit. The conductive layer can be made of one of anisotropic conductive film (ACF), anisotropic conductive glue (ACP) and their combination.

一种软式封装构造的制作方法，其主要步骤系包括有：提供一基底；于该基底的部分上表面形成预设的图案化线路；于图案化线路的其中一表面上形成一保护膜；及移除该基底，并于该图案化线路的另一表面部分区域上形成一防焊保护漆。A method for manufacturing a flexible packaging structure, the main steps of which include: providing a substrate; forming a predetermined patterned circuit on a part of the upper surface of the substrate; forming a protective film on one of the surfaces of the patterned circuit; and removing the base, and forming a solder resist protection paint on another surface portion of the patterned circuit.

所述图案化线路的形成方法系包括有：于未被定义为图案化线路的基底其它部分表面形成一光阻；以电镀方式在基底上表面形成至少一金属层，以成为该图案化线路；其中该图案化线路系可包括有内引脚、脚肩、外引脚、被动元件电极接垫、测试线路、测试端子及其组合式的其中之一者。其中该图案化线路系可选择由金、镍、铜、钯、铂、钨、镍-金、钯-镍、钛-钯-金、钛-铂-金、铬-镍-金、钛-钨-金及其组合式的其中之一所制成者。The method for forming the patterned circuit includes: forming a photoresist on the surface of other parts of the substrate that are not defined as the patterned circuit; forming at least one metal layer on the upper surface of the substrate by electroplating to become the patterned circuit; The patterned circuit system may include one of inner pins, shoulders, outer pins, electrode pads of passive components, test lines, test terminals and combinations thereof. The patterned line can be selected from gold, nickel, copper, palladium, platinum, tungsten, nickel-gold, palladium-nickel, titanium-palladium-gold, titanium-platinum-gold, chromium-nickel-gold, titanium-tungsten - Made of one of gold and its combinations.

其中该保护膜系可选择聚亚醯胺、聚乙胺、环氧树脂、聚脂材料、压克力树脂及其组合式等高分子胶膜材料的其中之一所制成者；Among them, the protective film can be made of one of polymer film materials such as polyimide, polyethylene amine, epoxy resin, polyester material, acrylic resin and its combination;

上述制作方法尚可包括有下列步骤：提供一基底，且于该基底的下表面形成一暂覆层；于图案化线路形成后，移除该暂覆层。The above manufacturing method may further include the following steps: providing a substrate, and forming a temporary covering layer on the lower surface of the substrate; removing the temporary covering layer after the patterned circuit is formed.

其中所述基底系可选择铜、铝、铁、镍、锌、钢、不锈钢及其组合式的其中之一所制成者。Wherein the substrate can be made of one of copper, aluminum, iron, nickel, zinc, steel, stainless steel and combinations thereof.

本发明的这种软式封装构造及其制作方法，可同时进行软式基板的制作与内引脚接合制程，以简化制程步骤及节省制作成本。且以电镀形成方式取代传统的蚀刻方式制作图案化线路，故可大幅提高软式晶片封装基板或软式卷带的微细线路制作能力，有助于软式晶片模组技术COF或软式卷带自动接合技术TAB的配线密度。由于其内引脚与IC晶片的自动接合与软式晶片封装基板的制作皆在一硬度较高的基底支撑下进行，不但可有效提高内引脚与IC晶片在接合时的定位对准能力，亦可相对降低接合制程上的困难度及增加产品合格率。且其内引脚与IC晶片的接合制程可藉由现有的覆晶接合技术机台进行接合，不但可提高产品产量及产品合格率，且可相对降低制作成本。The flexible packaging structure and its manufacturing method of the present invention can simultaneously perform the manufacturing of the flexible substrate and the bonding process of inner pins, so as to simplify the manufacturing process steps and save the manufacturing cost. In addition, electroplating is used to replace the traditional etching method to produce patterned circuits, so it can greatly improve the production capacity of the micro-circuits of flexible chip packaging substrates or flexible tapes, and contribute to the flexible chip module technology COF or flexible tapes Wiring density of automated bonding technology TAB. Since the automatic bonding of the inner pins and the IC chip and the production of the flexible chip packaging substrate are carried out under the support of a higher hardness substrate, it can not only effectively improve the positioning and alignment ability of the inner pins and the IC chip when bonding, It can also relatively reduce the difficulty of the bonding process and increase the yield of products. And the bonding process of the internal pins and the IC chip can be bonded by the existing flip-chip bonding technology machine, which can not only increase the product yield and product qualification rate, but also relatively reduce the production cost.

附图说明Description of drawings

图1A及图1B：系分别为一习用软式卷带自动接合技术(TAB)中内引脚接合制程的剖面示意图；FIG. 1A and FIG. 1B are respectively schematic cross-sectional views of the internal pin bonding process in a conventional flexible tape automated bonding technology (TAB);

图2A及图2B：系分别为一习用软式晶片模组技术(COF)中内引脚接合制程的剖面示意图；FIG. 2A and FIG. 2B are schematic cross-sectional views of the internal pin bonding process in a conventional chip-on-chip (COF) technology;

图3A至图3E：系分别为本发明可同时达成软式封装构造的基板制作与内引脚接合制程的一较佳实施例各步骤构造剖示图；3A to FIG. 3E : are the cross-sectional views of each step of a preferred embodiment of the substrate manufacturing and inner pin bonding process that can simultaneously achieve the flexible packaging structure of the present invention;

图4：系为本发明的又一实施例构造剖示图；Fig. 4: is the structural sectional view of another embodiment of the present invention;

图5A至图5D：系为本发明在制作软式卷带的各步骤构造剖示图。Fig. 5A to Fig. 5D: are the cross-sectional views of the structure of each step of making the flexible tape according to the present invention.

具体实施方式Detailed ways

请参阅图3A至图3E，系分别为本发明可同时达成软式封装构造的基板制作与内引脚接合制程的一较佳实施例各步骤装置剖示图；如图所示，本发明的主要步骤系包括有：Please refer to FIG. 3A to FIG. 3E , which are cross-sectional views of each step of the device in a preferred embodiment of the substrate manufacturing and inner pin bonding process that can simultaneously achieve the flexible packaging structure of the present invention; as shown in the figure, the present invention The main steps include:

首先，提供一可由铜、铝、铁、镍、锌、钢、不锈钢或上述材质组合物所制成的基底31，于基底31的部分上表面依设计可规划定义出一包括有内引脚、脚肩、外引脚、被动元件电极接垫、测试线路或测试端子的图案化线路位置333，而未被规划为图案化线路位置333的基底31其它部分表面则藉由一可选择干膜或液态光阻材质所制成的光阻315予以覆盖，且于基底31的下表面形成一可隔绝后续电镀材质依附的暂覆层35，如图3A所示；Firstly, asubstrate 31 is provided which can be made of copper, aluminum, iron, nickel, zinc, steel, stainless steel or a combination of the above materials, and a part of the upper surface of thesubstrate 31 can be defined according to the design including inner pins, The patternedcircuit position 333 of the shoulder, the outer pin, the electrode pad of the passive component, the test circuit or the test terminal, and the other part of the surface of thesubstrate 31 that is not planned as the patternedcircuit position 333 is covered by an optional dry film or Thephotoresist 315 made of liquid photoresist material is covered, and atemporary coating layer 35 is formed on the lower surface of thesubstrate 31, which can isolate the subsequent electroplating material from adhering, as shown in FIG. 3A;

再者，藉由电镀或蚀刻等方式在基底31的上表面形成至少一金属层，而位于预设图案化线路位置333的金属层即成为可包括有内引脚、脚肩、外引脚、被动元件电极接垫、测试线路或测试端子的图案化线路(circuit)33，之后再移除光阻315及暂覆层35，如图3B所示。该图案化线路33所选用的材质必须与IC晶片所形成的凸块具有良好的接合性，且于后续将基底31剥除时，不会被一起剥除的特性，故可选择由金、镍、铜、钯、铂、钨、镍-金、钯-镍、钛-钯-金、钛-铂-金、铬-镍-金、钛-钨-金或上述材质组合物所组成的多层或单层结构；Moreover, at least one metal layer is formed on the upper surface of thesubstrate 31 by means of electroplating or etching, and the metal layer at the predetermined patternedcircuit position 333 can include inner leads, shoulders, outer leads, The patternedcircuit 33 of the electrode pad of the passive device, the test line or the test terminal is removed, and then thephotoresist 315 and thetemporary covering layer 35 are removed, as shown in FIG. 3B . The selected material of the patternedcircuit 33 must have good bondability with the formed bump of the IC chip, and when thesubstrate 31 is peeled off later, it will not be stripped together, so it can be selected from gold and nickel. , copper, palladium, platinum, tungsten, nickel-gold, palladium-nickel, titanium-palladium-gold, titanium-platinum-gold, chromium-nickel-gold, titanium-tungsten-gold or a combination of the above materials or a single-layer structure;

接续，将已预留晶片孔的保护膜37贴附于内引脚33上表面，保护膜37可选择为聚亚醯胺、聚乙胺、环氧树脂、聚脂材料、或压克力树脂等高分子胶膜材料所制成；而在此步骤中，内引脚33的部分将裸露于保护膜37外以利后续晶片的组装作业，如图3C所示；Next, attach theprotective film 37 with reserved wafer holes on the upper surface of theinner pin 33. Theprotective film 37 can be selected from polyimide, polyethyleneamine, epoxy resin, polyester material, or acrylic resin and other polymer film materials; and in this step, the part of theinner pin 33 will be exposed outside theprotective film 37 to facilitate subsequent chip assembly operations, as shown in Figure 3C;

又，于内引脚33的表面贴附一异方性导电膜(ACF)或异方性导电胶(ACP)的导电层39；并将一已经完成金属凸块化IC晶片41或被动元件翻转，致使其金属凸块43与相对应的内引脚33对位，再经一加温及加压过程进行两者接合，并接着进行烘烤(post-cure)及封胶(potting)等步骤以完成金属凸块43与内引脚33间的永久连接，而IC晶片(或被动元件)41将可通过电极接垫413、凸块43、及导电层39而与内引脚33电性连接，且藉此可提高产品的信赖度，如图3D所示；Also, aconductive layer 39 of an anisotropic conductive film (ACF) or anisotropic conductive glue (ACP) is pasted on the surface of theinner pin 33; and a completed metalbump IC chip 41 or passive element is turned over , so that themetal bump 43 is aligned with the correspondinginner pin 33, and then the two are bonded through a heating and pressing process, and then baked (post-cure) and sealing (potting) and other steps To complete the permanent connection between themetal bump 43 and theinner pin 33, the IC chip (or passive element) 41 will be electrically connected to theinner pin 33 through theelectrode pad 413, thebump 43, and theconductive layer 39 , and thereby the reliability of the product can be improved, as shown in Figure 3D;

最后，利用湿式或干式蚀刻方式将基底31剥除，再将一由感光型或热烘型的软性环氧树脂、压克力树脂所制成的软性防焊保护漆45(或保护膜)以湿式涂布或干式贴合方式设于内引脚33下表面，以保护该内引脚33，如图3E所示。当然，在此防焊保护漆45形成步骤中，会针对外引脚、测试线路或测试端子空间区域予以保留，或是依产品需求施以镀锡、镍或金处理，以利后续对外引脚、测试线路或测试端子的接合作业，如此即可同时达成软式晶片封装基板的制作与内引脚接合制程的目的，如图3E所示。Finally, thesubstrate 31 is peeled off by wet or dry etching, and then a soft solder resist protective paint 45 (or protective paint 45) made of photosensitive or thermally baked soft epoxy resin and acrylic resin is applied. Film) is provided on the lower surface of theinner pin 33 by wet coating or dry lamination to protect theinner pin 33, as shown in FIG. 3E. Of course, in the step of forming the solder resistprotective paint 45, the external pins, test lines or test terminal space areas will be reserved, or tin, nickel or gold treatment will be applied according to product requirements, so as to facilitate the subsequent external pins. , test circuit or test terminal bonding operation, so that the purpose of manufacturing the flexible chip packaging substrate and the inner pin bonding process can be achieved at the same time, as shown in FIG. 3E .

由于在此实施例中图案化线路的制作与内引脚接合制程都在一硬度较高的基底上进行及完成，因此在与IC晶片接合时的定位、对准(Alignment)上难度不高，且可籍由现有进行覆晶接合技术的机台进行接合制程，不但可降低内引脚接合制程的困难度，亦可降低制程的成本。另外，线路的制作以电镀方式取代传统的蚀刻方式，可大幅提高软式晶片封装基板的微细线路制作能力及软式晶片模组COF的配线密度。Since the fabrication of the patterned circuit and the bonding process of the internal pins in this embodiment are all carried out and completed on a substrate with high hardness, the positioning and alignment (Alignment) are not difficult when bonding with the IC chip. Moreover, the bonding process can be performed by the existing machine for flip-chip bonding technology, which not only reduces the difficulty of the inner pin bonding process, but also reduces the cost of the process. In addition, the electroplating method is used to replace the traditional etching method in the production of circuits, which can greatly improve the production capacity of fine circuits on the flexible chip packaging substrate and the wiring density of the flexible chip module COF.

当然，本发明的内引脚33与凸块43的接合制程系可选用热压接合(thermo-compression bonding)、超音波接合(ultra-sonic bonding)、热超音波接合(thermo-sonic bonding)、雷射接合(laser bonding)、焊锡回流(solder refolw)等方式完成。Certainly, the bonding process of theinner pin 33 and thebump 43 of the present invention can be selected from thermo-compression bonding (thermo-compression bonding), ultrasonic bonding (ultra-sonic bonding), thermo-sonic bonding (thermo-sonic bonding), Laser bonding (laser bonding), solder reflow (solder refolw) and other methods to complete.

另外，请参阅图4，系为本发明又一实施例的构造剖示图；本发明所揭露技术亦可应用于如软式卷带自动接合技术(TAB)中，只要在步骤3D时无需在金属引脚33周边添设导电层39的情况下直接将已经完成金属凸块化的IC晶片41翻转，致使其金属凸块43与相对应的内引脚33对位，再经加温、加压、烘烤及封胶等后续步骤即可。In addition, please refer to FIG. 4 , which is a structural sectional view of another embodiment of the present invention; the technology disclosed in the present invention can also be applied to such as in the flexible tape automatic bonding technology (TAB), as long as there is no need to be in the step 3D When theconductive layer 39 is added around the metal pins 33, theIC chip 41 that has completed the metal bumping process is directly turned over, so that the metal bumps 43 are aligned with the correspondinginner pins 33, and then heated and heated. Subsequent steps such as pressing, baking and sealing can be completed.

又，上述实施例的保护膜37可选择一由感光型或热烘型的软性环氧树脂、压克力树脂所制成的软性防焊保护漆以湿式涂布或干式贴合方式设于内引脚33上表面；而上述实施例。软性防焊保护漆亦可由以聚亚醯胺、聚乙胺、环氧树脂、聚脂材料、或压克力树脂等高分子胶膜材料所制成且已预留晶片孔的保护膜来设于金属电极33的下表面来保护内引脚33。In addition, theprotective film 37 of the above-mentioned embodiment can be selected from a soft solder resist protective paint made of photosensitive or heat-drying soft epoxy resin and acrylic resin in a wet coating or dry laminating method. Set on the upper surface of theinner pin 33; and the above-mentioned embodiment. The soft solder resist protective paint can also be made of a protective film made of polymer film materials such as polyimide, polyethyleneamine, epoxy resin, polyester material, or acrylic resin, and has reserved chip holes. It is provided on the lower surface of themetal electrode 33 to protect theinner pin 33 .

而在此实施例中，由于同样是在一基底上完成图案化线路的制作与内引脚的接合制程，因此不但可降低内引脚接合制程的困难度、降低制程的成本、及大幅提高软式晶片封装基板的微细线路制作能力及软式晶片模组COF的配线密度。In this embodiment, since the fabrication of the patterned circuit and the bonding process of the inner pins are also completed on a substrate, it can not only reduce the difficulty of the inner pin bonding process, reduce the cost of the manufacturing process, and greatly improve the software. The micro-circuit manufacturing capability of the chip packaging substrate and the wiring density of the flexible chip module COF.

另外，请参阅图5A至图5D，系为本发明在制作软式卷带的一实施例各步骤构造剖示图；如图所示，本发明所揭露的主要技术同样可以应用于TAB技术中的软式卷带制作上，其主要步骤系包括有：In addition, please refer to Fig. 5A to Fig. 5D, which are cross-sectional diagrams of each step of the present invention in the production of a flexible tape; as shown in the figure, the main technology disclosed by the present invention can also be applied to the TAB technology In the production of soft tape, the main steps include:

首先，同样提供一基底31，于基底31的部分上表面依设计规划定义出一图案化线路位置333，而未被规划为图案化线路位置333的基底31其它部分表面则籍由一光阻315予以覆盖，且于基底31的下表面形成一可阻隔后续电镀材质依附的暂覆层35，如图5A所示；First, asubstrate 31 is also provided, and a patternedcircuit position 333 is defined on a part of the upper surface of thesubstrate 31 according to the design plan, while other parts of the surface of thesubstrate 31 that are not planned as the patternedcircuit position 333 are covered by aphotoresist 315 be covered, and form atemporary coating layer 35 on the lower surface of thesubstrate 31 that can block the adhesion of subsequent electroplating materials, as shown in FIG. 5A;

再者，藉由电镀或蚀刻等方式在基底31的上表面形成至少一金属层，而位于预设图案化线路位置333的金属层即成为可包括有内引脚、脚肩、外引脚、测试线路或测试端子的图案化线路33，之后再移除光阻315及暂覆层35，如图5B所示；接续，于图案化线路33上方藉由涂布或压合方式施以保护膜57，以保护电镀形成的图案化线路33，如图5C所示；及Moreover, at least one metal layer is formed on the upper surface of thesubstrate 31 by means of electroplating or etching, and the metal layer at the predetermined patternedcircuit position 333 can include inner leads, shoulders, outer leads, Test the patternedcircuit 33 of the circuit or test terminal, and then remove thephotoresist 315 and thetemporary covering layer 35, as shown in FIG. 5B; then, apply a protective film on the patternedcircuit 33 by coating or pressing 57, to protect the patternedcircuit 33 formed by electroplating, as shown in Figure 5C; and

最后，以湿式或干式蚀刻方式将基底31移除，并将软性防焊保护漆36利用湿式涂布或干式贴合方式保护图案化线路33，且预留外引脚区域以利后续外引脚接合作业(未显示)，如此即可完成达成软式卷带的制作。而内、外引脚区域的表面处理可依产品需求施以镀锡、镍或金处理，以利后续内、外引脚接合作业，如图5D所示。Finally, thesubstrate 31 is removed by wet or dry etching, and the soft solder resistvarnish 36 is wet-coated or dry-bonded to protect the patternedcircuit 33, and the outer lead area is reserved for subsequent The outer pins are bonded (not shown), so that the flexible tape can be completed. The surface treatment of the inner and outer lead areas can be treated with tin, nickel or gold according to product requirements, so as to facilitate the subsequent inner and outer lead bonding operations, as shown in FIG. 5D .

在此实施例中，由于图案化线路33的制作都在一硬度较高的基底上进行及完成，且线路的制作以电镀方式取代传统的蚀刻方式，因此可大幅提高软式卷带的微细线路制作能力、配线密度、及降低其制作成本。In this embodiment, since the fabrication of the patternedcircuit 33 is carried out and completed on a substrate with high hardness, and the fabrication of the circuit is replaced by the traditional etching method by electroplating, the fine circuit of the flexible tape can be greatly improved. production capacity, wiring density, and lower production costs.

惟以上所述，仅为本发明的一较佳实施例而已，并非用来限定本发明实施的范围，举凡依本发明对所述的形状、构造、特征及精神所为的均等变化与修饰，均应包括于本发明的权利要求范围内。However, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. For example, all equal changes and modifications made to the described shape, structure, characteristics and spirit according to the present invention, All should be included in the scope of the claims of the present invention.

Claims (24)

1. the manufacture method of a soft type encapsulating structure, its key step system includes:

One substrate is provided;

Part upper surface in this substrate forms default patterned circuit;

The one IC wafer of having finished projectionization is provided, and the projection of this IC wafer is aimed at patterned circuit corresponding with it, and cause projection to engage with corresponding patterned circuit; And

Remove this substrate, and form a diaphragm on a wherein surface of patterned circuit.

2. the manufacture method of soft type encapsulating structure as claimed in claim 1 is characterized in that: still can include the following step:

Form a conductive layer in the surface of patterned circuit, and electrically connect to cause projection and patterned circuit on the IC wafer by this conductive layer.

3. the manufacture method of soft type encapsulating structure as claimed in claim 2 is characterized in that: these conduction series of strata are optional selects anisotropy conducting film (ACF), anisotropic conductive (ACP) and knockdown one of them is made.

4. the manufacture method of soft type encapsulating structure as claimed in claim 1 is characterized in that: the formation method system of this patterned circuit includes:

Form a photoresistance in the substrate other parts surface that is not defined as patterned circuit; Form at least one metal level with plating mode at upper surface of substrate, to become this patterned circuit; And

Remove this photoresistance.

5. the manufacture method of soft type encapsulating structure as claimed in claim 1 is characterized in that: this patterned circuit system can include interior pin, pin shoulder, outer pin, passive device electrode connection pad, measurement circuit, calibrating terminal and knockdown one of them person thereof.

6. the manufacture method of soft type encapsulating structure as claimed in claim 1 is characterized in that: this patterned circuit system can select by gold, nickel, copper, palladium, platinum, tungsten, nickel-Jin, palladium-nickel, titanium-palladium-Jin, titanium-platinum-Jin, chromium-nickel-Jin, titanium-tungsten-Jin and knockdown one of them made person thereof.

7. the manufacture method of soft type encapsulating structure as claimed in claim 1 is characterized in that: still can include the following step:

Another surface portion zone in patterned circuit forms a diaphragm.

8. the manufacture method of soft type encapsulating structure as claimed in claim 7 is characterized in that: one of them made person of macromolecule glue membrane materials such as Polyimide, poly-ethamine, epoxy resin, polyester material, acryl resin and composite type thereof can select in this diaphragm system.

9. the manufacture method of soft type encapsulating structure as claimed in claim 1 is characterized in that: still can include the following step:

Another surface portion zone in patterned circuit forms a soft anti-welding protective paint.

10. the manufacture method of soft type encapsulating structure as claimed in claim 9 is characterized in that: one of them made person of soft epoxy resin and acryl resin can select in this soft anti-welding protective paint system.

11. the manufacture method of soft type encapsulating structure as claimed in claim 1 is characterized in that: after removing this substrate, also can form a soft anti-welding protective paint on the lower surface of patterned circuit.

12. the manufacture method of soft type encapsulating structure as claimed in claim 1 is characterized in that: still can include the following step:

One substrate is provided, and forms a temporary coating in the lower surface of this substrate; And

After patterned circuit forms, remove this temporary coating.

13. the manufacture method of soft type encapsulating structure as claimed in claim 1 is characterized in that: copper, aluminium, iron, nickel, zinc, steel, stainless steel and knockdown one of them made person thereof can select in this substrate system.

14. the manufacture method of a soft type encapsulating structure, its key step system includes:

One substrate is provided;

Part upper surface in this substrate forms default patterned circuit; Formation one diaphragm is gone up on a wherein surface in patterned circuit; And

Remove this substrate, and on another surface portion zone of this patterned circuit, form an anti-welding protective paint.

15. the manufacture method of soft type encapsulating structure as claimed in claim 14 is characterized in that: the formation method system of this patterned circuit includes:

Form a photoresistance in the substrate other parts surface that is not defined as patterned circuit;

Form at least one metal level with plating mode at upper surface of substrate, to become this patterned circuit;

Remove this photoresistance.

16. the manufacture method of soft type encapsulating structure as claimed in claim 14 is characterized in that: this patterned circuit system can include interior pin, pin shoulder, outer pin, passive device electrode connection pad, measurement circuit, calibrating terminal and knockdown one of them person thereof.

17. the manufacture method of soft type encapsulating structure as claimed in claim 14 is characterized in that: this patterned circuit system can select by gold, nickel, copper, palladium, platinum, tungsten, nickel-Jin, palladium-nickel, titanium-palladium-Jin, titanium-platinum-Jin, chromium-nickel-Jin, titanium-tungsten-Jin and knockdown one of them made person thereof.

18. the manufacture method of soft type encapsulating structure as claimed in claim 14 is characterized in that: one of them made person of macromolecule glue membrane materials such as Polyimide, poly-ethamine, epoxy resin, polyester material, acryl resin and composite type thereof can select in this diaphragm and anti-welding protective paint system.

19. the manufacture method of soft type encapsulating structure as claimed in claim 14 is characterized in that: still can include the following step:

One substrate is provided, and forms a temporary coating in the lower surface of this substrate; And

After patterned circuit forms, remove this temporary coating.

20. the manufacture method of soft type encapsulating structure as claimed in claim 14 is characterized in that: copper, aluminium, iron, nickel, zinc, steel, stainless steel and knockdown one of them made person thereof can select in this substrate system.

21. a soft type encapsulating structure is characterized in that: it mainly is to include:

One includes the patterned circuit of interior pin at least;

Surface in this patterned circuit is provided with a diaphragm; And

Another surface portion zone in this patterned circuit is provided with an anti-welding protective paint.

22. soft type encapsulating structure as claimed in claim 21 is characterized in that: this patterned circuit still can include outer pin, pin shoulder, passive device electrode connection pad, measurement circuit, calibrating terminal and knockdown one of them person thereof.

23. soft type encapsulating structure as claimed in claim 21 is characterized in that: this patterned circuit system can select by gold, nickel, copper, palladium, platinum, tungsten, nickel-Jin, palladium-nickel, titanium-palladium-Jin, titanium-platinum-Jin, chromium-nickel-Jin, titanium-tungsten-Jin and knockdown one of them made person thereof.

24. soft type encapsulating structure as claimed in claim 21 is characterized in that: one of them made person of macromolecule glue membrane materials such as Polyimide, poly-ethamine, epoxy resin, polyester material, acryl resin and composite type thereof can select in this diaphragm and anti-welding protective paint system.

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