CN1438651A - 1-T memory structure with concealed renewing memory function and its operation method - Google Patents

Abstract

The storage structure comprises the multiple memory arrays, multiple sensing amplifiers, a selector, a shared type data latch. The method for operating the storage structure includes following steps. The addresses, where the conflicts of accessing and updating requirements happen, are compared to determine whether the addresses are in the same memory array. If yes, then the present working mode is decided. If it is in the data accessing cycle mode, then data signals are updated through the sensing amplifier at same time and data signals are accessed through the shared data latch; if it is in the data updating cycle mode, then the data signal needed to update are stored in the shared type data latch, and the updated data are stored back to the original memory array by using the stealing technique after the operation of accessing data is completed.

Description

1-T internal storage structure and method of operating thereof with concealed updating memory function

Technical field

The present invention relates to a kind of 1-T internal storage structure and method of operating thereof with concealed updating memory function, it utilizes a data latches and adopts the design of parallel electrical path, solves effectively that access traditionally clashes with new element more and the problem that causes data to be lost.

Background technology

Fig. 1 is the synoptic diagram of a cell unit (aunit of cell) circuit in the typical 1-transistor internal memory (1-Tansistor memory).In Fig. 1, has monocrystal pipe closer (1-Transistorgate) G_1TAn assembly and a capacitor Cap.As shown in Figure 1, when lock control signal WL makes described TFT assembly conducting, select signal wire BL to deliver to capacitor Cap by the power supply meeting of data driver (not shown) via the position, and make capacitor Cap charge to saturated (saturation).Yet, passage in time, stored data-signal can disappear in time in this kind 1-T internal memory, and just the electric charge that stores in the capacitor can die down, and therefore is necessary this kind internal memory is done the action that data are upgraded (data refresh).For 1-T DRAM (Dynamic Random Access Memory) (DRAM), per 64 milliseconds (ms) make once more new element, new element time-consuming about 80 nanoseconds (ns) more at every turn, and for 1-T static random access memory (SRAM), per 2 milliseconds (ms) make once more new element, at every turn new element time-consuming about 80 nanoseconds (ns) more.Above-mentioned so frequent more new element can significantly increase in the storage operation access action and produce the possibility of (collision) of conflicting with new element more, and then significantly increases the complexity in the storage operation, otherwise, just be easy to generate the problem of data loss.

Summary of the invention

The object of the present invention is to provide a kind of 1-T internal storage structure and method of operating thereof with concealed updating memory function, its utilize data latches solve access action and more new element produce the data losing issue that is caused when conflict (collision), and the complexity and the required area of layout of reduction configuration (layout).

Another object of the present invention provides a kind of 1-T internal storage structure and method of operating thereof with concealed updating memory function, it uses the design of a parallel electrical path, cooperate shirtsleeve operation rule of logic (algorithm) to reduce operational complexity, and reach the problem that the institute that manages conflict causes the data loss.

The object of the present invention is achieved like this:

The invention provides a kind of 1-T internal storage structure and method of operating thereof with concealed updating memory function, it utilizes the sharing type data latches and adopts the design of parallel electrical path to come the configuration data latch, solves effectively that access traditionally clashes with new element more and the problem that causes data to be lost.Described 1-T internal storage structure with concealed updating memory function comprises: a plurality of memory arrays (memory array) are used for the storage data signal; A plurality of sensing amplifiers (senseamplifier) are used for amplifying respectively and the data-signal of temporary pairing memory array (memory array); One selector switch, be used for according to one-period indicator signal send the data-signal that in described sensing amplifier, amplifies via a bus; And a sharing type data latches, receive and store the data-signal of sending from described selector switch.Described method of operating with 1-T internal storage structure of concealed updating memory function comprises the following steps: relatively to take place the address of access and more new demand conflict whether in same memory array; If described conflict is to occur in the same memory array, then determine present mode of operation; If in the data access cyclic pattern, then simultaneously through sensing amplifier renewal data-signal and through a sharing type data latches access desired data signal; If in the Data Update cyclic pattern, then storing earlier needs the data updated signal in described sharing type data latches, and utilizes and steal technology (cycle-stealing technique) and will upgrade data-signal and deposit back in the former memory array finishing data access action back.

Specifically, the invention provides a kind of 1-T internal storage structure, comprising with concealed updating memory function:

A plurality of memory arrays are used for the storage data signal;

A plurality of sensing amplifiers storehouse is used for amplifying respectively and the data-signal of temporary pairing memory array;

One selector switch, be used for according to one-period indicator signal send the data-signal that in described sensing amplifier, amplifies via a bus; And

One sharing type data latches receives and stores the data-signal of sending from described selector switch.

Described cycle indicator signal be a store access cycle signal or a Data Update periodic signal one of them.

Described bus is that a long bit line is right.

The present invention also provides a kind of 1-T internal storage structure with concealed updating memory function, comprising:

One column address latch, memory array (MAT) address that is used to receive the column address data signal of outside input and exports place, described outer array address;

One present address timer is used to export the clock signal of a control present address;

One present address counter is used for exporting according to described clock signal memory array (MAT) address at described present column address place;

One address comparator is used for memory array (MAT) address at place, more described outer array address and memory array (MAT) address at described present column address place;

One instruction control unit is used for exporting a working period signal according to the comparative result of described address comparator;

One multiplexer is used for receiving respectively the column address from described column address latch and address counter;

One column address decoder is used to decipher the column address from described multiplexer;

One memory array is used for exporting corresponding data-signal according to the column address of described decoding;

One sensing amplifier is used for amplifying and temporary described outputting data signals;

One selector switch is used for sending the data-signal that amplifies via a bus according to described working period signal in described sensing amplifier; And

One sharing type data latches receives and stores the data-signal of sending from described selector switch.

Described working period signal is a update cycle signal.

Described working period signal is a store access cycle signal.

Described bus is that a long bit line is right.

The present invention also provides a kind of method of operating with 1-T internal storage structure of concealed updating memory function, comprises the following steps:

Whether the address that access and more new demand conflict relatively take place is in same memory array;

If described conflict is to occur in the same memory array, then determine present work period pattern;

If in the data access cyclic pattern, then simultaneously through sensing amplifier renewal data-signal and through a sharing type data latches access desired data signal; And

If in the Data Update cyclic pattern, then storing earlier needs the data updated signal in described sharing type data latches, and utilizes the technology of stealing will upgrade data-signal to return and deposit to former memory array finishing described data access action back.

In the step of described store access cycle pattern, also comprise using a bus to be sent to described sharing type data latches the described access data signal and using corresponding zone to export to go into bus and make access action into bus and main output.

Described bus uses a long bit line right.

In the step of described update cycle pattern, described renewal data-signal uses a bus to be sent to the sharing type data latches.

Described bus uses a long bit line right.

The described technology of stealing uses the switch operating cycle of Data Update periodic signal to return the action of deposit data.

Description of drawings

Fig. 1 is the synoptic diagram of a cell element circuit in the typical 1-T internal memory;

Fig. 2 is the synoptic diagram of 1-T internal storage structure of the present invention;

Fig. 3 is the synoptic diagram of the hiding refresh circuit part among Fig. 2;

Fig. 4 is operating structure figure of the present invention; And

Fig. 5 is an operational flowchart of the present invention.Wherein:

41--instruction control unit 42--timer (timer) 43--column address latch

44--address counter 45--MAT address comparator 46--multiplexer

47--column address decoder 48--row address decoder 49--memory array block

Embodiment

For allow above-mentioned and other purpose of the present invention, feature, can be more apparent with advantage, a preferred embodiment cited below particularly, and cooperate appended graphicly is described in detail below:

With reference to figure 2,1-T internal storage structure of the present invention.In Fig. 2, described structure comprises memory array MAT, sensing amplifier storehouse SAB, sensing amplifier selector switch SAS, sharing type data latches SDL, row selector YS and switch S.As shown in Figure 2, in this configuration, an internal memory work unit is arrange in pairs or groups a sensing amplifier storehouse SAB and in conjunction with the configuration of each sensing amplifier selector switch SAS of one of front and back, for example MATi, SABi and two MAT_SELi of a memory array MAT.Described selector switch SAS is according to periodic signal ACCESS_MISS or ACCESS_HIT selects to use zone output to go into bus LIO respectively or use bit line as conflict processing path.In addition, two internal memory work units middle connect with bus (bus) side by side, utilize a switch S to select to use main output to go into bus MIO or bus LIO is gone in zone output.Further, finish structure in a plurality of front and back arrange in pairs or groups mode of a sharing type data latches storehouse SAB of the internal memory work unit of (subsequently connected) that is connected, as shown in Figure 2, the MAT of odevity is connected to SABi and SABn respectively from MAT (i-1) to MATn.Though with 8 memory sections (memory sectors) ratio of 1 sharing type data latches is come framework usually, this structure proportion and on-fixed, it can do optimized adjustment according to the actual state of memory configurations.So finish as shown in Figure 2 a structure of the present invention.

Structure of the present invention comprises that also part SAB is connected the concealed refresh circuit that is constituted with the internal circuit of part SDL, sees Fig. 3.In Fig. 3, described selector switch SAS is constituted with door AND and two logical locks (pass gate) PG by two placed in the middle.As shown in Figure 3, when signal MAT_SEL is 1, represent that this MAT is selected to carry out the action of memory access.At this moment, must be further determine whether that by periodic signal ACCESS_HIT and ACCESS_MISS access data has or not the problem of conflicting with new data more, and then judge that the path that is sent to corresponding data latches SDL is to export into bus LIO via long bit line LNBL/LNBLB or via the zone.Signal ACCESS_HIT is meant that described conflict betides a data access cycle, and signal ACCESS_MISS refers to that then described conflict does not betide a Data Update cycle.As shown in Figures 2 and 3, the conflict that takes place in the data access cycle can make the access data signal that amplifies through sensing amplifier deliver to corresponding data latches SDL via long bit line LNBL/LNBLB, and be input to sensing amplifier storehouse SAB when carrying out more new element upgrading data-signal, data latches SDL exports the access data signal into bus LIOL via the zone of its correspondence simultaneously, goes into the action that the data-signal access is finished in bus MIO output via main output again.On the other hand, the conflict that takes place in the Data Update cycle can make the renewal data-signal that amplifies through sensing amplifier storehouse SAB deliver to corresponding data latches SDL via long bit line LNBL/LNBLB, and be input to sensing amplifier storehouse SAB at the access data signal and amplify action and after bus MIO finishes access action, will upgrade data-signal again and send back to via long bit line LNBL/LNBLB and former sensing amplifier storehouse SAB and carry out the more action of new data among the corresponding memory group MMAT.For example, when the MAT i of amplifier storehouse SABi data-signal when store access cycle clashes, can make (enable) long bit line LNBL/LNBLB export described access data signal earlier to latch SDL i, then, when wanting data updated signal (not shown) to be sent to the renewal of amplifier storehouse SAB i do in the MAT i, latch SDLi makes (enable) its corresponding bus LIOLi and bus MIO will be stored in its interior access data signal through two buses output thus simultaneously, finishes the action of upgrading data-signal and access data signal by this simultaneously.When the MAT i of amplifier storehouse SAB i data-signal when the update cycle clashes, can make (enable) long bit line LNBL/LNBLB export described renewal data-signal earlier to latch SDL i, then, be input to that sensing amplifier storehouse SAB i amplifies action and after bus MIO finishes access action at the access data signal, the long bit line LNBL/LNBLB of activation again (enable) also sends bus MIO anergy (disable) among the corresponding memory array MAT i back to via long bit line LNBL/LNBLB and former sensing amplifier storehouse SAB i and carries out the more action of new data so that will upgrade data-signal.

With reference to figure 4, for the purpose of clear, required dependency structure is represented in the calcspar mode in the time of only will operating.In Fig. 4, described structure comprises aninstruction control unit 41, atimer 42, acolumn address latch 43, anaddress counter 44, aMAT address comparator 45, amultiplexer 46, a column address decoder 47, arow address decoder 48 and a memory array block 49.As shown in Figure 4, when a collision event took place, the MAT address EMAT that describedcolumn address latch 43 receives outer array addresses and exports place, described outer array address was to described MAT address comparator 45.Described comparer 45 utilizes aninstruction control unit 41 and makes comparisons from the MAT address MATA of describedaddress counter 44 outputs according to describedtimer 42, come output signal ACCESS_HIT and ACCESS_MISS, betide the foundation in which kind of cycle to judge conflict.At this moment,column address latch 43 andaddress counter 44 are imported an internal column address IRA and a column address RRA respectively to the multitask device, select and will carry out hidden-type data renewal or access facility by described memory array block 49 (structure as shown in Figure 2) through the address of describedrow address decoder 48 and 47 decodings of described column address decoder via multiplexer control.

The step of carrying out such as following: with reference to figure 5, Fig. 5 is the operating process under Fig. 4 structure.In Fig. 5, the method for operating of described structure comprises the following steps: relatively to take place the address of access and more new demand conflict whether in same memory array (S1); If described conflict is to occur in the same memory array, then determine present mode of operation (S2); If in the store access cycle pattern, then simultaneously through sensing amplifier renewal data-signal and through a sharing type data latches access desired data signal (S3); If in the update cycle pattern, then storing earlier needs the data updated signal in described sharing type data latches, and utilizes the technology of stealing will upgrade data-signal after finishing the data access action and deposit back (S4) in the former memory array.

As shown in Figure 5, when present data-signal meets with renewal with the access conflict problem, must judge whether earlier that described conflict ties up to generation (S1) in the same memory array, if, the affiliated work period (S2) of time point that must further determine present data collision to take place.Just, must decide ensuing processing mode, comprise via long bit line LNBL/LNBLB being sent to corresponding data latches SDL by signal ACCESS_HIT and ACCESS_MISS.Signal ACCESS_HIT means that described conflict betides a data access cycle, and signal ACCESS_MISS refers to that then described conflict does not betide a Data Update cycle.Cooperate simultaneously Fig. 2,3 and Fig. 4 for referencial use, the conflict that takes place in the data access cycle can make the access data signal that amplifies through sensing amplifier storehouse SAB deliver to corresponding data latches SDL via long bit line LNBL/LNBLB, and being input to sensing amplifier storehouse SAB when carrying out more new element upgrading data-signal, data latches SAL exports the access data signal into bus LIOL and main output via the zone of its correspondence simultaneously and goes into the action (S3) that the data-signal access is finished in bus MIO output.On the other hand, the conflict that takes place in the Data Update cycle can make the renewal data-signal that amplifies through sensing amplifier storehouse SAB deliver to corresponding data latches SAL via long bit line LNBL/LNBLB, and the access data signal be input to sensing amplifier storehouse SAB amplify the action and after bus MIO finishes access action, to upgrade data-signal again sends back among the corresponding memory array MAT via long bit line LNBL/LNBLB and former sensing amplifier storehouse SAB and stores, wherein, deposit acts may for described time and utilize handle the switching time of periodic signal, this mode is known as the technology of stealing (cycle-stealingtechnique) (S4).

Though the present invention with a preferred embodiment openly as above; so it is not to be used to limit the present invention, and any those of ordinary skills are in without departing from the spirit or scope of the invention; change and retouching when doing, so protection scope of the present invention is as the criterion with claim.

Claims (13)

1. 1-T internal storage structure with concealed updating memory function comprises:

A plurality of memory arrays are used for the storage data signal;

A plurality of sensing amplifiers storehouse is used for amplifying respectively and the data-signal of temporary pairing memory array;

One selector switch, be used for according to one-period indicator signal send the data-signal that in described sensing amplifier, amplifies via a bus; And

One sharing type data latches receives and stores the data-signal of sending from described selector switch.

2. 1-T internal storage structure as claimed in claim 1 is characterized in that, described cycle indicator signal is-store access cycle signal or a Data Update periodic signal one of them.

3. 1-T internal storage structure as claimed in claim 1 is characterized in that, described bus is that a long bit line is right.

4. 1-T internal storage structure with concealed updating memory function comprises:

One column address latch, memory array (MAT) address that is used to receive the column address data signal of outside input and exports place, described outer array address;

One present address timer is used to export the clock signal of a control present address;

One present address counter is used for exporting according to described clock signal memory array (MAT) address at described present column address place;

One address comparator is used for memory array (MAT) address at place, more described outer array address and memory array (MAT) address at described present column address place;

One instruction control unit is used for exporting a working period signal according to the comparative result of described address comparator;

One multiplexer is used for receiving respectively the column address from described column address latch and address counter;

One column address decoder is used to decipher the column address from described multiplexer;

One memory array is used for exporting corresponding data-signal according to the column address of described decoding;

One sensing amplifier is used for amplifying and temporary described outputting data signals;

One selector switch is used for sending the data-signal that amplifies via a bus according to described working period signal in described sensing amplifier; And

One sharing type data latches receives and stores the data-signal of sending from described selector switch.

5. 1-T internal storage structure as claimed in claim 4 is characterized in that, described working period signal is a update cycle signal.

6. 1-T internal storage structure as claimed in claim 4 is characterized in that, described working period signal is a store access cycle signal.

7. 1-T internal storage structure as claimed in claim 4 is characterized in that, described bus is that a long bit line is right.

8. the method for operating with 1-T internal storage structure of concealed updating memory function comprises the following steps:

Whether the address that access and more new demand conflict relatively take place is in same memory array;

If described conflict is to occur in the same memory array, then determine present work period pattern;

If in the data access cyclic pattern, then simultaneously through sensing amplifier renewal data-signal and through a sharing type data latches access desired data signal; And

If in the Data Update cyclic pattern, then storing earlier needs the data updated signal in described sharing type data latches, and utilizes the technology of stealing will upgrade data-signal to return and deposit to former memory array finishing described data access action back.

9. method of operating as claimed in claim 8, it is characterized in that, in the step of described store access cycle pattern, also comprise using a bus to be sent to described sharing type data latches the described access data signal and using corresponding zone to export to go into bus and make access action into bus and main output.

10. method of operating as claimed in claim 9 is characterized in that, described bus uses a long bit line right.

11. method of operating as claimed in claim 8 is characterized in that, in the step of described update cycle pattern, described renewal data-signal uses a bus to be sent to the sharing type data latches.

12. method of operating as claimed in claim 11 is characterized in that, described bus uses a long bit line right.

13. method of operating as claimed in claim 8 is characterized in that, the described technology of stealing uses the switch operating cycle of Data Update periodic signal to return the action of deposit data.

Images