CN1431708A - Wafer type diffusion type packaging structure and manufacturing method thereof - Google Patents

Abstract

A wafer type diffusion type package structure is prepared as cutting crystal grain, screening to adhere crystal grain to glass base, sticking I/O joint of metal pad on crystal grain to be special material and mode, implanting I/O joint ball at position, diffusing contact point to edge of crystal grain or periphery of crystal grain in diffusion mode to increase number of I/O ball, increasing more I/O contact points and reducing signal interference caused by too close distance of contact points and solder bridging problem caused by too close solder joint. The packaging process is suitable for 8-inch and 12-inch wafers, and can include dies and capacitors and multi-die or various passive devices.

Description

Wafer formed diffusion type capsulation structure and manufacture method thereof

Technical field

The present invention relates to semiconductor packaging, particularly relevant for wafer formed diffusion type capsulation structure and manufacture method thereof

Background technology

As everyone knows, after the downsizing along with the electronic building brick size, many new challenges appear on the manufacture process of integrated circuit.In addition, because computer and mechanics of communication is flourish, what follow needs is the electronic building brick of more variety classeses and application.For example, all need many memory component and dissimilar semiconductor subassemblies by the computer interface of voice operating or the interface of other communication, therefore, the trend of integrated circuit still can be towards high integration development.Fast development along with semiconductor technology, electronics produces brilliant under the fast trend of compact and multi-functional speed, and the semi-conductive I/O number of IC is not only more and more, and density is also more and more higher, also make the number of pins of package assembling also increase, and the requirement of signal transmission speed is also more and more faster thereupon.Semiconductor chip individually is encapsulated within the packaging body of plastic cement or ceramic material usually.The structure of packaging body must be able to be protected chip and the heat that is produced in the chip operation process is shed, the usefulness when traditional encapsulation is used as the chip functions test.

Early stage encapsulation technology is utilized input and the output of the pin of peripheral arrangement mode as signal mainly based on the encapsulation technology of lead frame.And under the demand of high density input and output, the encapsulation of lead frame has not met described demand at present.At present, under described demand, encapsulation also need reduce volume, and meeting present trend, and ball arranged encapsulation technology (ball grid array is also followed in the encapsulation of high density I/O; BGA encapsulation) development of technology and haveing breakthrough, therefore, the encapsulation of IC semiconductor carrying trends towards utilizing ball arranged encapsulation technology (BGA).The pin that it is characterized by I/O is spherical, and the characteristics of BGA structure dress are that the pin of negative I/O is spherical, than the elongate pins of leaded package assembly apart from weak point, and be difficult for impaired distortion, the electrical transmission range of its package assembling is short, speed is fast, can meet at present and the demand of following digital system speed.For example, in United States Patent (USP) U.S.PatentNo.5629835, by the structure of a kind of BGA of proposition such as Mahulikar, denomination of invention is " METAL BALL GRID ARRAY PACKAGE WITH IMPROVED THERMALCONDUCTIVITY ".And for example United States Patent (USP) U.S.PatentNo.5239198 discloses a kind of packing forms, and this encapsulation comprises a substrate that is assembled on the printed circuit board (PCB), and substrate utilizes the FR4 material to form, and has the surface that a conducting wire is formed at substrate on this substrate.

In addition, the semiconductor packages of many different kenels has been arranged at present, no matter be the encapsulation of any kenel, being encapsulated as of the overwhelming majority is cut into after the individuality in advance, encapsulates and tests.And United States Patent (USP) has a kind of wafer form encapsulation of exposure, consult, and US5323051, denomination of invention is " Semiconductor wafer nevel package ".This patent encapsulated before cutting crystal grain in advance, utilized glass to be used as a bonding material, made assembly be encapsulated in the hole.One perforation that hides is as the channel of electrically connect.Therefore, wafer form is encapsulated as a kind of trend of semiconductor packages.Technology in addition is formed in the surface of semiconductor crystal wafer with most grain shaped, and glass utilizes adhering substance to be attached on the surface of wafer.Then, the side that is provided with crystal grain will be ground, and to reduce its thickness, is called grinding back surface (back grinding) usually.Then, wafer is etched in order to separate the adhering substance of IC and expose portion.

In addition, in the encapsulation technology field in the past, I/O aluminium pad partly is the surface that is connected to crystal grain, because chip area is limited, I/O aluminium pad will limit its aluminium pad number under this limited area.Moreover, apart from too small, will cause coupling between signal or the interference between signal between the I/O aluminium pad.

Summary of the invention

The purpose of this invention is to provide a kind of wafer formed diffusion type capsulation structure and manufacture method thereof, principal character is to replace the position that traditional grain surface I/O plants ball, in the diffused mode, with the past outdiffusion of contact point, implant the ball of planting to promote bigger scope as I/O, to increase the number that I/O plants ball, that is the more I/O of increase, or at crystal grain under the trend of downsizing, the minimum spacing that keeps I/O reaches the purpose that prevents too approaching signal interference that is caused and the too approaching solder bridge that is caused of scolding tin joint.

The object of the present invention is achieved like this: a kind of wafer formed diffusion type capsulation structure is characterized in that; It comprises crystal grain and is disposed on the insulating base, and it is formed thereon that wafer comprises most aluminium pads; Bcb layer is coated this grain surface, and has most first openings and expose this majority aluminium pad; Scolding tin is filled in this first opening; First epoxy resin is coated on this crystal grain, insulating base and the bcb layer; Copper conductor is disposed at this first epoxy resin and is connected with this scolding tin; Second epoxy resin is coated on this copper conductor, and has this copper conductor of second opening emerges part; The tin ball is disposed on this second epoxy resin, and inserts this second opening and be connected with this copper conductor.

Also comprising copper seed layer is formed on this first scolding tin.Described copper seed layer is titanium/copper layer.Described copper seed layer is nickel/copper layer.More comprising resistance barrier or adhesion coating is formed on this aluminium pad.This resistance barrier or adhesion coating comprise nickel/aluminium lamination.The interface of this tin ball and this copper conductor comprises nickel.More comprise the side of a capacitance arrangement in this crystal grain.More comprise the side that another crystal grain is disposed at this crystal grain.

The present invention also provides a kind of manufacture method of wafer formed diffusion type capsulation structure, it is characterized in that: it comprises the steps:

(1) provides and have most crystal grain wafer formed thereon;

(2) test most crystal grain on this wafer, and the qualified crystal grain of mark;

(3) this crystal grain of spin coating BCB dielectric protection layer;

(4) remove this bcb layer partly, form first opening, to expose the metallic aluminium pad on this crystal grain;

(5) cut this wafer to separate this majority crystal grain;

(6) through screening, rearrange configuration by the action of drawing and place and be adhered on the insulator foot by the crystal grain after the quality control;

(7) fill first epoxy resin on the aluminium pad of this insulator foot, crystal grain, BCB and first opening comprehensively;

(8) etching removes this first epoxy resin of this aluminium pad top, forms second opening;

(9) solidify this first epoxy resin;

(10) the sputter barrier layer is on this aluminium pad;

(11), use scolding tin on this barrier layer, and fill up this second opening with fabrography;

(12) form copper seed layer on this scolding tin and first epoxy resin;

(13) utilize a photoresistance to electroplate the copper conductor of certain area on this scolding tin and barrier layer;

(14) formationization nickel or change gold are on this copper conductor;

(15) remove photoresist layer;

(16) be coated with second epoxy resin on this copper conductor comprehensively;

(17) solidify this second epoxy resin;

(18) remove this second epoxy resin of this copper conductor top, and form the 3rd opening;

(19) implant solder ball in the 3rd opening;

(20) cut this insulating base, in order to separate the individual package monomer.

Before forming described copper conductor, more comprise sputter one copper seed layer in this scolding tin and this is above first epoxy resin.This adhesion crystal grain more is included in and is solidified this sticker in the stove in the process of this base.The thickness of this BCB insulating barrier is 5-25 μ.This first epoxy resin of etching forms the process of this second opening, is to be undertaken by etching of photoresistance type or chemical agent.Form after described second opening, more comprise with RIE electricity slurry and clean grain surface.The material of this barrier layer comprises nickel/copper or changes nickel dam.After finishing above-mentioned fabrography, comprise with the infrared ray backflow and solidify this scolding tin.This copper seed layer is titanium/copper.The step of solidifying this second epoxy resin is for utilizing ultraviolet irradiation or heat treated.This be implanted in the 3rd opening solder ball adopt fabrography or plant the playing skill art.More comprise the side of capacitance arrangement, side by side on this glass base in this crystal grain.More comprise side that another crystal grain is disposed at this crystal grain side by side on this glass base, form polycrystalline grain encapsulating structure, this another crystal grain is including but not limited to CPU, DRAM or SRAM assembly.This insulator foot is glass, pottery or silicon wafer.

Describe in detail below in conjunction with preferred embodiment and accompanying drawing.

Description of drawings

Fig. 1 is that the single crystal grain of wafer-level packaging of the present invention is put the schematic diagram in glass base.

The crystal grain that Fig. 2 has electric capacity for wafer-level packaging of the present invention is put the schematic diagram in glass base.

Fig. 3 has the schematic diagram that forms one deck BCB protective layer on the surface of crystal grain of metal gasket for the present invention.

Fig. 4 removes the schematic diagram of part BCB protective layer for the present invention.

Fig. 5 glues the schematic diagram that places base for crystal grain process of the present invention absorption and placement back.

Fig. 6 fills the schematic diagram of first epoxy resin comprehensively for the present invention.

Fig. 7 removes the schematic diagram of first epoxy resin of aluminium pad top for the present invention.

Fig. 8 fills up the schematic diagram of this second opening with fabrography with scolding tin for the present invention.

Fig. 9 is the schematic diagram of the present invention by the copper conductor of calibration, exposure and the certain area of plating that develops.

Figure 10 is coated with the schematic diagram of second epoxy resin comprehensively for the present invention.

Figure 11 removes part second epoxy resin above the copper conductor for the present invention and forms the schematic diagram of the 3rd opening.

Figure 12 is for implanting the schematic diagram of solder ball.

Figure 13 is the schematic diagram of cutting crystal grain and intercrystalline line of cut and glass pedestal.

Figure 14 is the relevant position schematic diagram of each barrier layer on the crystal grain.

Figure 15 is the generalized section of the diffusion-type wafer encapsulated moulding of single crystal grain.

Figure 16 is implanted on the glass pedestal moulding generalized section with the diffusion-type wafer encapsulation of single crystal grain for electric capacity.

Figure 17 is the generalized section of diffusion-type wafer encapsulation in the encapsulation process of polycrystalline grain.

Embodiment

The method that the present invention discloses a kind of wafer form encapsulation (WLP) and makes the wafer form encapsulation, explanation is only done in described preferred embodiment, is not in order to restriction the present invention.

At first consult shown in Figure 1, to screen by the crystal grain after the quality control through test and the wafer that cut process, choose crystal grain (die) 1a of test passes, by drawing and apparatus for placing, it is rearranged be disposed at a new glass base 1, this base 1 can be glass, pottery or silicon wafer, and via sticker eachcrystal grain 1a is adhered on the base 1, about 10 μ of this sticker thickness, the process of solidifying sticker is to utilize the spin coater action of adhering.Crystal grain 1a lays out in glass base 1, and the distance betweencrystal grain 1a strengthens, and its objective is hope in follow-up encapsulation process, has sufficient space and can hold diffused circle solder ball array.This diffused encapsulation technology can promote the I/O number, or dwindles under the situation incrystal grain 1a size, still keeps its desired pitch, disturbs to prevent the signal between I/O.It is big or small and decide that the big small size of encapsulation depends on that successive process is finished spacing between the diffused circle solder ball array of back.

In another embodiment, also can comprise the side thatelectric capacity 1b is disposed atcrystal grain 1a on this glass pedestal 1, to promote filter effect, as shown in Figure 2.

The following stated encapsulation process is to begin its encapsulation process from the single crystal grain with metal gasket (metal pad):

As shown in Figure 3, wafer 2 fronts (or first surface) that will encapsulate have the metal gasket as input and output, aluminium pad (I/O pad or aluminum pad) 4 for example, thismetal gasket 4 is to use as intraconnections, utilize light shield through calibration, exposure and developing process, withmetal gasket 4 be formed at wafer 2 above.

Then, passing through rotary coating machine spin coating one deckBCB insulating barrier 8 on the wafer 2 in wafer 2 and above thealuminium pad 4, with protection wafer 2, the thickness ofBCB 8 is approximately 5-10 μ.

Then, as shown in Figure 4,, remove theBCB 8 of part through light shield calibration, exposure and developing process, formfirst opening 9,, it should be noted that to expose themetallic aluminium pad 4 of below, also be exposed on this Cutting Road, and, do not undermine BCB when being beneficial to cut greater than the width of its Cutting Road.Afterwards, with plating mode formationization nickel or changegold 11 onaluminium pad 4.

Through cutting, represent as Fig. 5, with amajority crystal grain 2a (wafer cut already form crystal grain) herein via screening and quality inspection qualified after,crystal grain 2a is put aboveglass base 6 with the machinery of placing function via having absorption, and bysticker 7 be adhered on theglass base 6 to, then in stove, solidified.

Then, as shown in Figure 6, on thealuminium pad 4 ofglass base 6,crystal grain 2a,BCB 8 and opening, fill one deck first epoxy resin (EPOXY) 10 comprehensively comprehensively.

Then, as shown in Figure 7,, removefirst epoxy resin 10 ofaluminium pad 4 tops, formsecond opening 13, and expose thealuminium pad 4 of below through photoresistance type etching or chemical agent.Then, solidified in stove, the thickness of thisfirst epoxy resin 10 is approximately (the thickness here refers to the thickness on the grain surface) between the 10-25 μ.

Then, the remaining epoxy resin of solid is with RIE electricity slurrycleaning crystal grain 2a surface.Then represent as for above-mentioned remaining epoxy resin with 10 '.Above-mentioned nickel/gold or changenickel dam 11 are as the barrier layer or the function of adhesion coating.

Then, as shown in Figure 8, utilize scoldingtin 12 to fill up thissecond opening 13 insecond opening 13 below nickel/copper or changenickel dam 11 with fabrography.Then, reflux to solidify this scoldingtin 12 with infrared ray, then, comprehensive ground sputter one deck titanium/copper 19 is above remainingepoxy resin 10 and scoldingtin 12, with as copper seed layer.

Then, as shown in Figure 9, with photoresistance (not shown) definition copper conductor pattern, utilize plating mode to form copper conductor above titanium/copper 19, one end is aimed at the inner (inner side edge of crystal grain) of the secondopening scolding tin 12, and the other end with horizontal direction towards outdiffusion (inner side edge of crystal grain).Clear and definite says, that is to say the position ofcopper conductor 14, one end is to trim withaluminium pad 4, the other end draws lead to direction towards outdiffusion with level, and the contact area of itself and lower floor'sepoxy resin 10 and scoldingtin 12 is big than the opening ofaluminium pad 4, its purpose mainly be used for increasing I/O plant the ball region area, then, oncopper conductor 14, form a stratification nickel dam or changegold layer 17,, remove photoresistance again to plant the adhesion coating of ball as follow-up scolding tin.And remove the upper part titanium/copper 19 that is exposed to remaining epoxy 10 '.

Then, as shown in figure 10, be coated with one deck secondepoxy resin 16 abovecopper conductor 14,nickel dam 17 and lower floor'sepoxy resin 10 comprehensively, and with step of curing, utilize ultraviolet irradiation or heat treated,, prevent thatcopper conductor 14 is oxidized with the second above-mentioned epoxy resin that hardens.

Then, as shown in figure 11, removecopper conductor 14 and part secondepoxy resin 16 above thenickel dam 17, and form the3rd opening 15, the position of the3rd opening 15 is atcopper conductor 14 and above thenickel dam 17, and be positioned at the outside (away from one side of aluminium pad 4) ofcopper conductor 14 as far as possible, be beneficial to make diffused (fan out) I/O structure.

As shown in figure 12, then at the3rd opening 15 places, above nickel (Ni)layer 17, by fabrography or plant the playing skill art andimplant solder ball 18, by among the figure obviously as seen, scolding tin asks 18 through the position after the encapsulation process design, and not directly overmetal gasket 4, but level reaches on the side ofMetal Ball 4 to side.

Then, as shown in figure 13, reflux through infrared ray again and toast epoxy resin, be sent in the wafer and carry out the wafer form test in the wafer form testing apparatus, for example last test and cutting process, and cutting crystal grain and intercrystalline line of cut 20 andglass pedestal 6 are to separate other packaging body.

Processing procedure of the present invention is simple than conventional art, before not cutting apart, test with wafer form, and after test, can cut and be divided into other crystal grain along Cutting Road, be placed on the glass substrate to draw apparatus for placing, finish diffusion-type wafer encapsulation (wafer level fan out packaging).

As shown in figure 14, for nickel/gold or changenickel dam 11, titanium/copper or nickel/gold 19,nickel dam 17 each adhesion coating and barrier layers, at each position view of intraconnections.

Shown in Figure 15, be the generalized section of the diffusion-type wafer encapsulated moulding of single crystal grain, the present invention also can include crystal grain electric capacity 2b in encapsulation process.

Shown in Figure 16, for electric capacity 2b is implanted on the glass pedestal generalized section with the diffusion-type wafer encapsulation of single crystal grain.

In another embodiment; the present invention also can integrate polycrystalline grain or multiple passive component and receive people's encapsulation process; shown in Figure 17; be in the encapsulation process of polycrystalline grain; the generalized section of diffusion-type wafer encapsulation; the different crystal grain of 2a, 2c representative among the figure, this kind packaged type can be integrated encapsulation with polycrystalline grain and multiple passive component, forms system's formula encapsulation (ysstem in package).

Principal character of the present invention is based on the wafer form encapsulation, and uses diffused (fan out) mode that the position that grain surface I/O plants ball is extended laterally, and its advantage can increase the number that I/O plants ball; Can reduce because the too approaching signal interference problem that is caused of contact point distance.

Major advantage of the present invention is as follows:

1, as shown in Figure 1, the cost of wafer form encapsulation of the present invention is low than conventional art, wafer process screening by testing and cutting again, will be by the crystal grain after the quality control, the crystal grain of choosing, rearrange in a new glass base by drawing, can reduce cost of manufacture, finish the diffused encapsulation with the action of placing.

2, because size is dwindled principle, crystal grain also dwindles thereupon, and in order to make intercrystalline distance still keep desirable distance (being coupled as principle not have influence on the signal transmission), be to encapsulate in the present invention with diffusion-type wafer, with the outdiffusion of I/O alignment, and move line to crystal grain outer zone, with the number that increases the scolding tin ball and keep desirable intercrystalline distance.

3, the present invention can be applied to 8 cun encapsulation processs with 12 cun wafers.

4, the present invention can integrate crystal grain and electric capacity in same encapsulation monomer.

5, the present invention can be integrated in same monomer with polycrystalline grain or multiple passive component, for example central processing unit, DRAM, and SRAM etc. are in the encapsulation process of encapsulation base plate.

6, the present invention can be used as buffering area with the scolding tin in the epoxy resin, in successive process, reduces between the different layers because the unequal power distribution problem that difference caused that material is used increases its reliability.

7, base of the present invention is a glass, and its material is identical with the crystal grain ground, owing to all contain the silicon material in the material, both have same thermal expansion coefficient (TCE), can not produce the unequal power distribution phenomenon.

8, base of the present invention can use glass, lime stone and silicon wafer, to improve its reliability.

9, packaging machinery of the present invention all is to encapsulate with existing machinery equipment, can save the expense of additionally buying more.

10, the present invention can increase the number of scolding tin ball, wherein some scolding tin ball is used as sample dummy output input end (dummy ball), though this dummy ball does not have the function that signal transmits, but can be made for buffering area, to weaken the stress between unlike material, the phenomenon of crystal grain be full of cracks takes place when reducing encapsulation.

The present invention with preferred embodiment explanation as above and is familiar with this field skill person, and in not breaking away from spiritual scope of the present invention, institute does a little change and retouches, and all belongs within protection scope of the present invention.

Claims (25)

Translated fromChinese

1、一种晶圆型态扩散型封装结构，其特征是；它包含晶粒配置于绝缘基座之上，晶圆包含多数个铝垫形成于其上；BCB层涂布于该晶粒表面，并具有多数第一开口暴露该多数铝垫；焊锡填充于该第一开口；第一环氧树脂涂布于该晶粒、绝缘基座及BCB层之上；铜导线配置于该第一环氧树脂并与该焊锡连接；第二环氧树脂涂布于该铜导线之上，并具有第二开口暴露部分的该铜导线；锡球配置于该第二环氧树脂之上，并填入该第二开口与该铜导线连接。1. A wafer-type diffused packaging structure, characterized in that it includes crystal grains disposed on an insulating base, and the wafer includes a plurality of aluminum pads formed thereon; BCB layer is coated on the surface of the crystal grains , and have a plurality of first openings exposing the plurality of aluminum pads; solder is filled in the first openings; a first epoxy resin is coated on the die, insulating base and BCB layer; copper wires are arranged in the first ring Oxygen resin and connected with the solder; the second epoxy resin is coated on the copper wire, and has the second opening exposed part of the copper wire; solder balls are arranged on the second epoxy resin and filled The second opening is connected with the copper wire.2、根据权利要求1所述的晶圆型态扩散型封装结构，其特征是：还包含铜种子层形成于该第一焊锡之上。2. The wafer-type diffusion package structure according to claim 1, further comprising a copper seed layer formed on the first solder.3、根据权利要求2所述的晶圆型态扩散型封装结构，其特征是：所述的铜种子层为钛/铜层。3. The wafer-type diffusion package structure according to claim 2, wherein the copper seed layer is a titanium/copper layer.4、根据权利要求2所述的晶圆型态扩散型封装结构，其特征是：所述的铜种子层为镍/铜层。4. The wafer-type diffusion package structure according to claim 2, wherein the copper seed layer is a nickel/copper layer.5、根据权利要求1所述的晶圆型态扩散型封装结构，其特征是：更包含阻障或粘着层形成于该铝垫之上。5. The wafer type diffusion package structure according to claim 1, further comprising a barrier or an adhesive layer formed on the aluminum pad.6、根据权利要求5所述的晶圆型态扩散型封装结构，其特征是：该阻障或粘着层包含镍/铝层。6. The wafer-type diffusion package structure according to claim 5, wherein the barrier or adhesive layer comprises a nickel/aluminum layer.7、根据权利要求1所述的晶圆型态扩散型封装结构，其特征是：该锡球与该铜导线的接口包含镍。7. The wafer type diffusion package structure according to claim 1, wherein the interface between the solder ball and the copper wire contains nickel.8、根据权利要求1所述的晶圆型态扩散型封装结构，其特征是：更包含一电容配置于该晶粒之侧。8. The wafer type diffusion package structure according to claim 1, further comprising a capacitor disposed on the side of the die.9、根据权利要求1所述的晶圆型态扩散型封装结构，其特征是：更包含另一晶粒配置于该晶粒之侧。9. The wafer type diffusion package structure according to claim 1, further comprising another die disposed on the side of the die.10、一种权利要求1-9其中之一所述的晶圆型态扩散型封装结构的制造方法，其特征是：它包括如下步骤：10. A method for manufacturing the wafer-type diffused packaging structure according to any one of claims 1-9, characterized in that it comprises the following steps:(1)提供具有多数晶粒形成于其上的晶圆；(1) providing a wafer having a plurality of dies formed thereon;(2)测试该晶圆上的多数晶粒，并标记合格的晶粒；(2) testing most of the dies on the wafer, and marking qualified dies;(3)旋涂BCB绝缘层保护该晶粒；(3) Spin coating the BCB insulating layer to protect the crystal grain;(4)去除部分的该BCB层，形成第一开口，以曝露出该晶粒上的金属铝垫；(4) removing part of the BCB layer to form a first opening to expose the metal aluminum pad on the crystal grain;(5)切割该晶圆以分离该多数晶粒；(5) dicing the wafer to separate the plurality of dies;(6)经筛选通过品质管制后的晶粒，通过吸取与放置的动作重新排列配置粘着于一绝缘底座之上；(6) After screening and passing the quality control, the crystal grains are rearranged and adhered to an insulating base through the actions of suction and placement;(7)全面性地填充第一环氧树脂于该绝缘底座、晶粒、BCB及第一开口的铝垫上；(7) filling the first epoxy resin comprehensively on the aluminum pad of the insulating base, the crystal grain, the BCB and the first opening;(8)蚀刻移除该铝垫上方的该第一环氧树脂，形成第二开口；(8) etching and removing the first epoxy resin above the aluminum pad to form a second opening;(9)固化该第一环氧树脂；(9) curing the first epoxy resin;(10)溅镀阻障层于该铝垫之上；(10) sputtering a barrier layer on the aluminum pad;(11)以网印技术，用焊锡在该阻障层上，并填满该第二开口；(11) using screen printing technology to solder on the barrier layer and fill the second opening;(12)形成铜种子层于该焊锡及第一环氧树脂之上；(12) forming a copper seed layer on the solder and the first epoxy resin;(13)利用一光阻电镀一定面积的铜导线于该焊锡及阻障层之上；(13) Utilize a photoresist to electroplate a certain area of copper wire on the solder and the barrier layer;(14)形成化镍或化金于该铜导线之上；(14) forming nickel or gold on the copper wire;(15)去除光阻层；(15) remove photoresist layer;(16)全面性地涂布第二环氧树脂于该铜导线之上；(16) Coating the second epoxy resin on the copper wire comprehensively;(17)固化该第二环氧树脂；(17) curing the second epoxy resin;(18)去除该铜导线上部分该第二环氧树脂，并形成第三开口；(18) removing part of the second epoxy resin on the copper wire, and forming a third opening;(19)植入焊锡球于该第三开口；(19) Implanting solder balls into the third opening;(20)切割该绝缘基座，用以分离个别封装单体。(20) Cutting the insulating base to separate individual packaging cells.11、根据权利要求10所述的晶圆型态扩散型封装结构的制造方法，其特征是：在形成所述铜导线之前，更包含溅镀一铜种子层于该焊锡与该第一环氧树脂上面。11. The method for manufacturing a wafer-type diffusion package structure according to claim 10, further comprising sputtering a copper seed layer on the solder and the first epoxy before forming the copper wires. resin top.12、根据权利要求10所述的晶圆型态扩散型封装结构的制造方法，其特征是：该粘着晶粒于该底座的过程，更包含在炉内予以固化该粘着剂。12. The manufacturing method of the wafer-type diffusion package structure according to claim 10, wherein the process of adhering the die to the base further includes curing the adhesive in a furnace.13、根据权利要求10所述的晶圆型态扩散型封装结构的制造方法，其特征是：该BCB绝缘层的厚度为5-25μ。13. The method for manufacturing a wafer-type diffused packaging structure according to claim 10, characterized in that: the thickness of the BCB insulating layer is 5-25μ.14、根据权利要求10所述的晶圆型态扩散型封装结构的制造方法，其特征是：蚀刻该第一环氧树脂形成该第二开口的过程，是通过光阻型蚀刻或化学药剂进行。14. The manufacturing method of the wafer-type diffused packaging structure according to claim 10, characterized in that: the process of etching the first epoxy resin to form the second opening is carried out by photoresist etching or chemicals .15、根据权利要求14所述的晶圆型态扩散型封装结构的制造方法，其特征是：形成所述第二开口之后，更包含以RIE电浆清洗晶粒表面。15. The method for manufacturing the wafer-type diffusion package structure according to claim 14, further comprising cleaning the surface of the die with RIE plasma after forming the second opening.16、根据权利要求10所述的晶圆型态扩散型封装结构的制造方法，其特征是：该阻障层的材料为镍/铜或化镍层。16. The method for manufacturing a wafer-type diffusion package structure according to claim 10, wherein the material of the barrier layer is nickel/copper or a nickel layer.17、根据权利要求10所述的晶圆型态扩散型封装结构的制造方法，其特征是：完成上述网印技术后，以红外线回流固化该焊锡。17. The method for manufacturing a wafer-type diffusion package structure according to claim 10, characterized in that: after the above-mentioned screen printing technology is completed, the solder is reflowed and solidified by infrared rays.18、根据权利要求11所述的晶圆型态扩散型封装结构的制造方法，其特征是：该铜种子层为钛/铜。18. The method for manufacturing a wafer-type diffusion package structure according to claim 11, wherein the copper seed layer is titanium/copper.19、根据权利要求10所述的晶圆型态扩散型封装结构的制造方法，其特征是：固化该第二环氧树脂的步骤为利用紫外线照射或加热处理。19. The method for manufacturing a wafer-type diffusion package structure according to claim 10, wherein the step of curing the second epoxy resin is by ultraviolet irradiation or heat treatment.20、根据权利要求10所述的晶圆型态扩散型封装结构的制造方法，其特征是：该植入于该第三开口的的焊锡球采用网印技术或植球技术。20. The manufacturing method of the wafer-type diffusion package structure according to claim 10, wherein the solder balls implanted in the third opening adopt screen printing technology or ball planting technology.21、根据权利要求10所述的晶圆型态扩散型封装结构的制造方法，其特征是：更包含电容配置于该晶粒之侧，并排于该玻璃底座上。21. The method for manufacturing a wafer-type diffusion package structure according to claim 10, further comprising capacitors disposed on the side of the die and arranged on the glass base.22、根据权利要求10所述的晶圆型态扩散型封装结构的制造方法，其特征是：更包含另一晶粒配置于该晶粒之侧并排于该玻璃底座上，形成多晶粒封装结构，该另一晶粒包含CPU、DRAM或SRAM组件。22. The method for manufacturing a wafer-type diffusion package structure according to claim 10, further comprising: another chip is disposed on the side of the chip and arranged on the glass base to form a multi-chip package structure, the other die contains CPU, DRAM or SRAM components.23、根据权利要求10所述的晶圆型态扩散型封装结构的制造方法，其特征是：该绝缘底座为玻璃。23. The method for manufacturing a wafer-type diffusion package structure according to claim 10, wherein the insulating base is made of glass.24、根据权利要求11所述的晶圆型态扩散型封装结构的制造方法，其特征是：该绝缘底座为陶瓷。24. The method for manufacturing a wafer-type diffusion package structure according to claim 11, wherein the insulating base is made of ceramics.25、根据权利要求10所述的晶圆型态扩散型封装结构的制造方法，其特征是：该绝缘底座为硅晶。25. The method for manufacturing a wafer-type diffused packaging structure according to claim 10, wherein the insulating base is silicon crystal.

Images