CN1431704A - Solving method for transient analysis of power source network based on equivalent circuit - Google Patents

Abstract

Translated fromChinese

基于等效电路的集成电路电源网络瞬态分析求解的方法属于VLSI物理设计中布局布线设计领域，其特征在于：它是一种利用计算机针对专用集成电路(ASIC)的电源线/地线网络大量含有链状拓扑结构的特点，把链路中间节点的RLC电路的参数R、L、C和电流源等效到这条链路两端节点上，再对于仅由所有链路两端节点构成的等效电路，列出线性方程组，利用现有的方法快速求解出此时刻等效电路的所有链路各端点的电压值，再据此求出所有链路中被合并节点此时刻的电压值的方法。它具有快速，节省内存的优点，可扩大能够处理的芯片的规模，而且精确度也满足要求。

The method for the transient analysis and solution of the integrated circuit power supply network based on the equivalent circuit belongs to the field of layout and wiring design in the physical design of VLSI, and is characterized in that: it is a large number of power lines/ground wire networks that utilize computers for application-specific integrated circuits (ASICs). Contains the characteristics of chain topology structure, the parameters R, L, C and current source of the RLC circuit of the middle node of the link are equivalent to the nodes at both ends of the link, and then for the node composed of all the nodes at both ends of the link Equivalent circuit, list linear equations, use existing methods to quickly solve the voltage values at each end point of all links in the equivalent circuit at this moment, and then calculate the voltage value of the merged nodes in all links at this moment Methods. It is fast, saves memory, scales up the size of the chips it can handle, and is accurate enough.

Description

Method based on the ic power network transients analysis and solution of equivalent electric circuit

Technical field

Method based on the ic power network transients analysis and solution of equivalent electric circuit belongs to VLSI physical Design field, especially RLC power line in the layout routing field/earth cord network transient analysis solution technique category.

Background technology

In the chip physical Design, the wiring of power line/ground wire belongs to the wiring portion of special gauze, designing improperly, power line/earth cord network can cause a series of serious problems, can not get the damage of the excessive caused supply network of current density of a certain branch road in the caused logic error of enough supply power voltages, the supply network etc. as semiconductor device, therefore in the wiring stage, the wiring of power line/ground wire has limit priority.

Along with the manufacturing process of integrated circuit enters into sub-micro (VDSM) by present deep-submicron (DSM), the design scale of integrated circuit is also by ultra-large (VLSI), and very extensive (ULSI) is to G extensive (GSI) development.Because chip power-consumption sharply increases and chip power supply voltage constantly reduces, and makes supply network that increasing operating current must be provided.Simultaneously along with being increased sharply of working frequency of chip, make parasitic capacitance, inductance to the increase day by day of supply network influence, power line/earth cord network analysis has been converted to complicated transient analysis from better simply dc analysis.All these make the safe power supply problem of chip become one of topmost thorny problem in the chip design manufacture process, also are that restriction chip performance and scale continue one of main bottleneck that improves, and therefore are subjected to the unprecedented attention of academic and industrial quarters.

Because the improving constantly of production technology, constantly the dwindling of semiconductor device, the density of line becomes increasing, makes increasing to the demand of interconnection resource.Simultaneously because supply network need provide increasing operating current, thus supply network for the supply power voltage that guarantees each unit greater than minimum normal working voltage, also must widen the width of power line/ground wire, strengthened demand to interconnection resource.Like this, design one and occupy the least possible safe power supply network of interconnection resource, just become wires design stage important target.After the power line of circuit/earth cord network design is finished, for the supply power voltage that guarantees each unit greater than minimum normal working voltage, also must carry out analysis verification to whole design, promptly power line/earth cord network is carried out transient analysis and finds the solution.Therefore the transient analysis solver of efficient, an accurate power line/earth cord network is the basis of supply network design optimization in the chip, also is the verification tool of power supply gauze design correctness, and it can shorten the design cycle of chip simultaneously.Background knowledge and technology that following portions introduction is mainly relevant.

At the ASIC circuit based on the standard cell design, its power-line network as shown in Figure 1 and Figure 2.Circuit is the standard cell power supply by the power supply loop wire with the power rail that connects thereon, for the supply power voltage that guarantees each unit greater than minimum normal working voltage, generally also to increase some power supplies and strengthen buses.

Power line/ground wire roughly becomes the fully connected topology of a grid (Mesh), and following Fig. 3 is one and considers resistance (R), inductance (L), the rlc circuit analytical model of the power-line network of electric capacity (C) influence.

Wherein utilize in current source (PWL) analog chip that segmentation represents modular unit (cell) to go up the time dependent current value that receives.Power-line network just to these unit power supplies, guarantees that each unit can operate as normal.The purpose of power supply gauze sunykatuib analysis be exactly solve all unit modules each the time magnitude of voltage that engraves, the basis is provided for the verification of correctness of power-line network and optimization.

Because the electric current that receives of unit module changes the continuous variation that causes unit module voltage in time continuously, so the electric power network analysis and solution is a transient analysis problem.For the ease of in time domain, carrying out analysis and solution, generally transient problem must be converted into the quasi-static analysis problem, an enough little time step promptly is set, the transient simulation in the one-period is converted to enough a plurality of quasistatic direct currents finds the solution problem.

It is an On Solving System of Linear Equations problem that the quasistatic direct current is found the solution in the question essence.At first according to the topological structure and kirchhoff (Kirchhoff) law of circuit network, set up circuit equation for each node, the equations simultaneousness with all obtains system of linear equations.Power-line network is by electric capacity, inductance, and resistance, current source and voltage source are formed, and character sparse, symmetrical, positive definite that the coefficient matrix of linear equations of power-line network has can utilize more existing highly effective algorithms directly to find the solution.

To sum up, the power-line network transient analysis solution procedure of integrated circuit is as follows: the step-length of (1) selected transient analysis and the total step number of definite required simulation, (2) on each simulation steps, earlier according to topology of networks and Kirchhoff's law, set up the system of linear equations of circuit, utilize the derivation algorithm of equation group to solve each magnitude of voltage of each node constantly again.

Along with the increase day by day of integrated circuit integrated level, the raising gradually of technology, the transient analysis of power-line network are found the solution also to become and are become more and more important and complexity.Recently academia has done a lot of important breakthrough research work that have in this respect, and multi-grid method (multi grid), stratification (hierarchical method), pre-excellent conjugation tonsure method (PreconditionConjugate Gradient-PCG), the hierarchical model depression of order (hierarchical model order reduction) are wherein arranged.Though these new methods have very much progress for the analysis of the electric power network of large-scale circuit, but they do not have fully to investigate the characteristic of the electric power network structure of chip, do not make full use of the regularity of supply network structure, therefore mostly have the shortcoming that computational speed is slow, committed memory is many.For this reason, at ASIC circuit based on the standard cell design, consider the regularity characteristics of its electric power network, our structure and design realized accurately, efficiently based on the ic power network transients analysis and solution device of equivalent electric circuit, under the prerequisite of not losing accuracy and save memory, increased substantially the speed of analysis and solution, enlarged the chip-scale of analysis and solution,, obtained best up to now result for handling large-scale chip.

Summary of the invention

The objective of the invention is to design a kind of ic power network transients analysis and solution device, under the situation of not losing accuracy, increase substantially the speed of analysis and solution, the chip-scale that expansion can be found the solution based on equivalent electric circuit.The basis of invention is the ordered structure of power line/earth cord network, wherein a large amount of RLC chain structure circuit that exist shown in figure (4):

The main thought of invention is: (1) at the characteristics of the power-line network chain topological structure (as shown in Figure 4) of ASIC circuit, with the electrical parameter equivalence of node in the chain to two end nodes of this chain.(2) for the equivalent electric circuit that only constitutes by two end nodes of all chains, since very little according to the listed system of linear equations scale of this equivalent circuit, existing derivation algorithm can be adopted, calculate the magnitude of voltage of this each end points of equivalent electric circuit constantly fast.(3) according to this two ends node voltage of all chains constantly, solve all chains by this magnitude of voltage constantly of merge node, to reach the purpose of sunykatuib analysis.Because in whole process, finding the solution system of linear equations is a step the most consuming time and the consumption internal memory, thus reduce the process that the scale of equation group can shorten whole analysis and solution significantly, and the expense of compression memory significantly.

In the present invention, we will be only with the node definition of two other node connections be intermediate point (Middle Node), such as N₂, N₃N_iAnd N_nCorresponding with it, with node definition more than two other node connections be joint (Cross Node), as N₁And N_N+1Node.The core content of invention is exactly for the such long-chain of each bar, and the Cross Node that all Middle Node is merged to two ends gets on, and making circuit reduction is the equivalent electric circuit of only being made up of Cross Node.After the circuit equation group of finding the solution equivalent electric circuit again obtains this voltage constantly of each Cross Node, further recover to find the solution this magnitude of voltage constantly of all Middle Node.

1. based on the method for the ic power network transients analysis and solution of equivalent electric circuit, contain the method that power line/network of wires is carried out transient analysis based on dc analysis, its characteristics are: it is a kind of characteristics of utilizing computer to contain the chain topological structure in a large number at the power line/earth cord network of application-specific integrated circuit (ASIC) (ASIC), the parameters R of the rlc circuit of link intermediate node, L, C and current source equivalence are to this both link ends node, again for the equivalent electric circuit that only constitutes by two end nodes of all links, list system of linear equations, utilize existing method rapid solving to go out this magnitude of voltage of all each end points of link of equivalent electric circuit constantly, obtain in view of the above again in all links by this magnitude of voltage constantly of merge node not only fast but also the method for saving calculator memory.

2. the method for the ic power network transients analysis and solution based on equivalent electric circuit according toclaim 1, its characteristics are that it contains following steps successively:

(1) computer reads in the message file of circuit, comprises the relational structure between the node in the file; The time dependent current waveform (utilizing PWL to represent) that receives of the supply module unit that the resistance value between the node, inductance value, inductance initial voltage and current value, capacitance, electric capacity initial voltage and current value and each node are connected, in computer, set up the information of circuit in view of the above, and all intermediate points of mark (Middle Node) and joint (Cross Node);

(2) according to the work period of circuit and the periodicity of needs simulation, computer reads in corresponding time step h and total simulation step number M respectively;

(3) electric capacity, the inductance in the discretization ifq circuit obtains the circuit of being made up of resistance, current source:

(3.1) capacitor C in the discretization circuit and resistance L,

The time step of given simulation is utilized trapezoidal difference formula, and K+1 moment electric capacity disperses and turns to an equivalent resistance

With an equivalentcurrent source$\frac{2C}{h}{V}_{c,k}+I_{c,k}$Model in parallel,$I_{c,k+1}=\frac{2C}{h}{V}_{c,k+1}-(\frac{2C}{h}{V}_{c,k}+I_{c,k})---\left(1\right),$V_{C, k}, I_{C, k}, V_{C, k+1}, I_{C, k+1}Represent the voltage and current on K and the K+1 moment electric capacity respectively, its direction is consistent; The time step of given simulation is utilized trapezoidal difference formula, and K+1 moment inductance disperses and turns to an equivalent resistance

With an equivalentcurrent source$\frac{h}{}$$\frac{}{2L}{V}_{L,k}+I_{L,k}$Model in parallel,$I_{L,k+1}=\frac{\mathrm{<figure-callout\; label="h"\; filenames="A0310477000213.png,A0310477000221.png"\; state="\{\{state\}\}">h</figure-callout>}}{2L}{V}_{L,k+1}+(\frac{\mathrm{<figure-callout\; label="h"\; filenames="A0310477000213.png,A0310477000221.png"\; state="\{\{state\}\}">h</figure-callout>}}{2L}{V}_{L,k}+I_{L,k})---\left(2\right),$

V_{L, k}, I_{L, k}, V_{L, k+1}, I_{L, k+1}Represent the voltage and current on k and the k+1 moment inductance respectively, its direction is consistent;

(3.2), set up the discretization model of ifq circuit according to the discretization process in (3.1);

(4) merge all intermediate nodes (Middle Node), set up the equivalent electric circuit of forming by the node that crosses (Cross Node):

(4.1) utilize promise to pause (Norton) law of equivalence merging current source with the simplification circuit,

For a link that contains N+1 node, bevertex ticks 1 to N+1 from left to right, (the resistance R between 1＜i＜N) of adjacent node i and i+1 on the link_iThe series circuit of forming with K+1 moment discretization inductance is reduced to by equivalent resistance

With equivalent current source el_{I, k+1}The parallel circuits of forming:$R_i^{*}={2L}_i/h+R_i---\left(3\right),$${\mathrm{el}}_{i,k+1}=(\frac{\mathrm{<figure-callout\; label="h"\; filenames="A0310477000213.png,A0310477000221.png"\; state="\{\{state\}\}">h</figure-callout>}}{{2L}_i}{V}_{L,i,k}+E_{i,k})\&CenterDot;\frac{2L_i/\mathrm{<figure-callout\; label="h"\; filenames="A0310477000213.png,A0310477000221.png"\; state="\{\{state\}\}">h</figure-callout>}}{{2L}_i/h+R_i}---\left(4\right),$

R_i, L_iBe respectively resistance and inductance value between node i and node i+1;

V_{L, i, k}, E_{I, k}Be respectively K L constantly_iOn electric current and magnitude of voltage, direction by the i+1 node to the i node;

El_{I, k+1}Be behind the equivalent-simplification with

Equivalent current source in parallel;

(4.2) current source over the ground on the merge node i,

Constantly for node i, modular unit received electric current e at K+1_{I, k+1}With the discretization capacitor C_iThe effect that obtains

Circuit is merged into by current source ec_{I, k+1}With resistance r_iThe circuit that composes in parallel:${\mathrm{ec}}_{i,k+1}=e_{i,k+1}-(\frac{2C_i}{h}{V}_{i,k}+I_{i,k})---\left(5\right),$$r_i=\frac{\mathrm{<figure-callout\; label="h"\; filenames="A0310477000221.png"\; state="\{\{state\}\}">h</figure-callout>}}{2C_i}---\left(6\right)$

C_iBe respectively node i associated capacitance value over the ground;

V_{I, k}, I_{I, k}Be respectively K constantly magnitude of voltage on the node i and the current value by electric capacity, direction over the ground;

Ec_{I, k+1}The equivalent electric that expression constantly self is received electric current and obtained by the corresponding capacitance discretization by i node K+1

Total current after stream merges calculates according to formula (5), and the sense of current over the ground;

(4.3) Y type circuit is to the equivalent transformation of pi-network:

Be two end points by three adjacent successively nodes and the Y type conversion of circuits formed of ground (GND) with form pi-network;

General, three nodes establishing the Y circuit are x, y, z (ground connection), and intermediate node is o, and the structure of Y type circuit is:

Between end points x, o: by resistance R_xWith current source I_x(direction is that o is to x) composes in parallel,

Between end points y, o: by resistance R_yWith current source I_y(direction is that o is to y) composes in parallel,

Between end points z, o: by resistance R_zWith current source I_z(direction is that o is to z) composes in parallel,

The structure of the pi-network that equivalence posterior nodal point x, y and z form is:

Between node x, the y by equivalent resistance R_XyWith equivalent current source I_XyCompose in parallel, wherein:$R_{\mathrm{xy}}=\frac{R_x{R}_y+R_x{R}_z+R_y{R}_z}{R_z},I_{\mathrm{xy}}=\frac{R_x{I}_x-R_y{I}_y}{R_{\mathrm{xy}}}---\left(7.1\right),$

Between node x, the z by equivalent resistance R_XzWith equivalent current source I_XzCompose in parallel, wherein:$R_{\mathrm{xz}}=\frac{R_x{R}_y+R_x{R}_z+R_y{R}_z}{R_y},I_{\mathrm{xz}}=\frac{R_z{I}_z-R_x{I}_x}{R_{\mathrm{xy}}}---\left(7.2\right),$

Between node y, the z by equivalent resistance R_YzWith equivalent current source I_YzCompose in parallel, wherein:$R_{\mathrm{yz}}=\frac{R_x{R}_y+R_x{R}_z+R_y{R}_z}{R_x},I_{\mathrm{xz}}=\frac{R_z{I}_z-R_y{I}_y}{R_{\mathrm{yz}}}---\left(7.3\right),$

Therefore, the size of current of inflow node x is:$E_x=\frac{V_y-V_x}{R_{\mathrm{xy}}}-\frac{V_x}{R_{\mathrm{xz}}}+\left(\frac{R_x{I}_x-R_y{I}_y}{R_{\mathrm{xy}}}\right)-\left(\frac{R_z{I}_z-R_x{I}_x}{R_{\mathrm{xz}}}\right)---\left(8\right),$

The size of current that flows into node y is:$E_y=\frac{V_x-V_y}{R_{\mathrm{xy}}}-\frac{V_y}{R_{\mathrm{yz}}}-\left(\frac{R_x{I}_x-R_y{I}_y}{R_{\mathrm{xy}}}\right)-\left(\frac{R_z{I}_z-R_y{I}_y}{R_{\mathrm{yz}}}\right)---\left(9\right),$(4.4) equivalent transformation of parallel circuits:

Parallel circuits between two nodes is done to merge the simplification conversion:$r_{\mathrm{total}}=1/(1/r_{\mathrm{left}}+1/r_{\mathrm{right}})---\left(10\right),$

i_total＝i_left+i_right?????????????——(11)，

r_Left, r_Right, i_Left, i_Right, represent the size of two resistance and current source respectively;

r_Total, i_TotalThe all-in resistance after expression merges respectively and the size in total current source;

(4.5) merge Middle Node, simplify obtaining final equivalent electric circuit:

Recycle top principle and step, the intermediate node (Middle Node) that merges every link, obtain the π type equivalent electric circuit of every link, for a link (being labeled as 1 to N+1 from left to right) that contains N+1 node, final π type equivalent circuit structure is as follows:

End points 1 is between N+1: equivalent resistance

And equivalent current source(direction N+1 to 1) parallel connection;

End points 1 is between GND: equivalent resistanceAnd equivalent current source(direction 1 to GND) parallel connection;

End points N+1 is between GND: equivalent resistance

And equivalent current source

(direction N+1 is to GND) parallel connection;

Circuit reduction is the equivalent electric circuit of the simplification of node (Cross Node) composition that only crosses the most at last;

(5) set up the nodal voltage equation group of the equivalent electric circuit that obtains by step (4.5) according to kirchhoff (Kirchhoff) law$G\&CenterDot;\stackrel{\&RightArrow;}{V}=\stackrel{\&RightArrow;}{I}$Thereby, obtain only relevant sparse coefficient matrix G with circuit structure and resistance;

(6) beginningization simulation makes step counter K=0, obtains the initial voltage value (this value should equal the initial voltage value of each node associated capacitance) of each node by the PWL oscillogram of each node, makes up thus

(7) if K＞M, then end simulation;

Otherwise execution following steps:

(8) the PWL waveform extracting K+1 step by each node constantly each node supply module unit receive electric current,

Calculate the K+1 current vector on equation group the right constantlyBring the system of linear equations that obtains by step (5) into:$G\&CenterDot;{\stackrel{\&RightArrow;}{V}}_{k+1}={\stackrel{\&RightArrow;}{I}}_{k+1}$

This step is received the PWL waveform of electric current according to the supply module unit of each node, extracts this their current value size constantly, utilizes then

Merge the size that obtains equivalent current by electric capacity, inductance discretization then through equivalent transformation according to formula (1) (2) (4) (5) (7) (11), finally obtain each this equivalence constantly of node that crosses and receive electric current, constitute vector

(9) with existing method solving equation group$G\&CenterDot;{\stackrel{\&RightArrow;}{V}}_{k+1}={\stackrel{\&RightArrow;}{I}}_{k+1},$Obtain cross the constantly magnitude of voltage vector of node ofK+1

(10) recover to find the solution this magnitude of voltage constantly of each intermediate node:${\mathrm{<figure-callout\; label="E"\; filenames="A0310477000213.png,A0310477000221.png"\; state="\{\{state\}\}">E</figure-callout>}}_{1,k+1}=\frac{V_{n+1,k+1}-{\mathrm{<figure-callout\; label="V"\; filenames="A0310477000213.png,A0310477000221.png"\; state="\{\{state\}\}">V</figure-callout>}}_{1,k+1}}{{\mathrm{<figure-callout\; label="R"\; filenames="A0310477000213.png,A0310477000221.png"\; state="\{\{state\}\}">R</figure-callout>}}_{1,n+1}^{\mathrm{equiv}}}+I_{1,n+1,k+1}^{\mathrm{equiv}}-{\mathrm{<figure-callout\; label="I"\; filenames="A0310477000213.png,A0310477000221.png"\; state="\{\{state\}\}">I</figure-callout>}}_{1,k+1}^{\mathrm{equiv}}-\frac{{\mathrm{<figure-callout\; label="V"\; filenames="A0310477000213.png,A0310477000221.png"\; state="\{\{state\}\}">V</figure-callout>}}_{1,k+1}}{{\mathrm{<figure-callout\; label="R"\; filenames="A0310477000213.png,A0310477000221.png"\; state="\{\{state\}\}">R</figure-callout>}}_1^{\mathrm{equiv}}},$

V_{1, k+1}, V_{N+1, k+1}Be the magnitude of voltage of the K+1 moment two joints,

Then by node i from 2 to N, obtain the K+1 magnitude of voltage constantly of these all intermediate nodes of link:$V_{i,k+1}=V_{i-1,k+1}+R_{i-1}^{*}(E_{i-1,k+1}-{\mathrm{el}}_{i-1,k+1}),$$E_{i,k+1}=E_{i-1,k+1}+\frac{V_{i,k+1}}{r_i}+{\mathrm{ec}}_{i,k+1},$

V_{I, k+1}Expression i node is at the K+1 voltage in step, i ∈ [1, n+1];

Resistance between expression i node and node i+1,$R_i^{*}={2L}_i/h+R_i;$

r_iThe equivalent resistance that expression is obtained by electric capacity i discretization, r_i=h/2C_i

El_{I, k+1}The equivalent current that expression obtains after by inductance i discretization, the current value that obtains through resulting electric current discretization behind the Norton equivalent transformation is tried to achieve by formula (4) again, direction by node i+1 to node i;

Ec_{I, k+1}Expression constantly self receive electric current by i node K+1 and merge by the equivalent current that the corresponding capacitance discretization obtains after total current, calculate according to formula (6), the sense of current by node i to ground;

E_{I, k+1}Expression K+1 step flows into the current value of i node, direction by node i+1 to node i;

(11) magnitude of voltage of K+1 all nodes is constantly preserved in output, puts K=K+1, forwards step (7) to, carries out next step simulation process.

Not only speed is fast under the situation of precision satisfying to experiment showed, method proposed by the invention, thereby and the internal memory that can save computer enlarge and can find the solution the scale of chip.

Description of drawings:

Fig. 1: the power line pessimistic concurrency control of integrated circuit,

The 1-supply rings,

Bus is strengthened in the 2-power supply,

The 3-power rail,

4-standard module unit (cell).

Fig. 2: based on the ASIC circuit supply network diagram of standard cell design,

The 1-power rail,

The 2-power supply is strengthened bus,

The 3-ground wire is strengthened bus,

The 4-standard cell,

5-ground wire rail,

6-power supply loop wire,

7-ground wire loop wire.

Fig. 3: the RLC analytical model of power-line network.

Fig. 4: common RLC chain circuit in the power-line network.

Fig. 5: the discretization model of electric capacity, inductance,

1-K+1 is the discretization model of electric capacity constantly,

2-K+1 is the discretization model of inductance constantly.

Fig. 6: the model before the RLC link discretization.

Fig. 7: the model after the RLC link discretization.

Fig. 8: Nuo Dun (Norton) law of equivalence,

Before the 1-conversion,

After the 2-conversion.

Fig. 9: merge current source,

Before 1-merges,

After 2-merges.

Figure 10: utilize the link after the Norton law is simplified.

Figure 11: Y type circuit is to the equivalent transformation of pi-network,

Before the 1-conversion,

After the 2-conversion.

Figure 12: the equivalent transformation of parallel circuits,

Before the 1-conversion,

After the 2-conversion.

Figure 13: begin to do the equivalent transformation of Y type circuit to pi-network from an end of link.

Figure 14: the equivalent transformation of making parallel circuits.

Figure 15: continue to do the equivalent transformation of Y type circuit to pi-network.

Figure 16: a link is simplified the final equivalent electric circuit in back.

Figure 17: h receives current value constantly according to PWL waveform extracting (K+1).

Figure 18: 8 * 8 test example,^*Expression Cross Node, Expression Middle Node, outer thick line is represented the power supply power supply rail, the internal layer fine rule is represented the gauze of powering.

Figure 19: a link illustration in the test example.

Figure 20: the discretization model of illustration.

Figure 21: the method simplification circuit that utilizes promise to pause (Norton) law and merge current source.

Figure 22: link is simplified the final equivalent electric circuit in back.

Figure 23: the final equivalent model of 8 * 8 test examples.

Figure 24: program flow chart of the present invention.

Now the present invention is described in detail according to step once in conjunction with figure (4):

1. read in the circuit information file, set up the ifq circuit structure

This is an input process, and the description document of ifq circuit is read in, and comprises the relational structure between the node in the file; The time dependent size of current of receiving of the supply module unit that the resistance value between the node, inductance value, capacitance and each node connect.In computer, set up the information of circuit in view of the above, and all intermediate points of mark (Middle Node) and joint (Cross Node).

2. set the time step h of simulation, the total step number N of simulation

This step is set the parameter of simulation, time step h and total step number M.The setting of time step h will be according to the circuit working cycle; The work week issue of needs simulation is depended in the setting of total step number.

3. discretization electric capacity, inductance obtain by resistance, current source, the circuit that voltage source is formed

Because the existence of electric capacity, inductance need utilize time step and difference formula to carry out the discretization process.Introduce the discretization process of electric capacity, inductance below.

3.1 electric capacity, the discretization of inductance

The time step of given simulation, according to the trapezoid formula of backward difference:

Electric capacity:$I_{c,k+1}=\frac{2c}{h}{V}_{c,k+1}-(\frac{2c}{h}{V}_{c,k}+I_{c,k})---\left(1\right)$

Inductance:$I_{L,k+1}=\frac{\mathrm{<figure-callout\; label="h"\; filenames="A0310477000213.png,A0310477000221.png"\; state="\{\{state\}\}">h</figure-callout>}}{2L}{V}_{L,k+1}+(\frac{\mathrm{<figure-callout\; label="h"\; filenames="A0310477000213.png,A0310477000221.png"\; state="\{\{state\}\}">h</figure-callout>}}{2L}{V}_{L,k}+I_{L,k})---\left(2\right)$

Electric capacity, inductance can be by the discrete equivalent models that turns to resistance and current source parallel connection.As shown in Figure 5

V_{C, k}, I_{C, k}, V_{C, k+1}, I_{C, k+1}Represent k and the k+1 voltage and current on the electric capacity constantly respectively, among its direction such as Fig. 5 symbol and

Arrow mark.

V_{L, k}, I_{L, k}, V_{L, k+1}, I_{L, k+1}Represent k and the k+1 voltage and current on the inductance constantly respectively, among its direction such as Fig. 5 symbol and

Arrow mark.

C and L represent the value of electric capacity and inductance respectively, the simulated time step-length that the h representative is selected.

Like this, ifq circuit is the equivalent electric circuit of being made up of resistance, current source, voltage source by discretization.

3.2 the discretization model of electrical chain in the circuit

Be as drag wherein, see Fig. 6 as the RLC chain transformaiton among Fig. 4

4. merge all Middle Node, set up the equivalent electric circuit of forming by Cross Node

This is core of the present invention, exactly all Middle Node is merged to the Cross at two ends

Node, the equivalent electric circuit that obtains simplifying.Give detailed introduction below.

4.1 the method for utilizing promise to pause (Norton) law of equivalence and merging current source is simplified circuit

On the basis of Fig. 5, utilize the Norton law, with of the conversion of the do of the local circuit in the electrical chain as Fig. 8.$R_i^{*}={2L}_i/h+R_i---\left(3\right)$${\mathrm{el}}_{i,k+1}=(\frac{\mathrm{<figure-callout\; label="h"\; filenames="A0310477000213.png,A0310477000221.png"\; state="\{\{state\}\}">h</figure-callout>}}{{2L}_i}{V}_{L,i,k}+E_{i,k})\&CenterDot;\frac{2L_i/\mathrm{<figure-callout\; label="h"\; filenames="A0310477000213.png,A0310477000221.png"\; state="\{\{state\}\}">h</figure-callout>}}{{2L}_i/h+R_i}---\left(4\right)$

4.2 the merging current source, as shown in Figure 9.${\mathrm{ec}}_{i,k+1}=e_{i,k+1}-(\frac{2C_i}{h}{V}_{i,k}+I_{i,k})---\left(5\right)$$r_i=\frac{\mathrm{<figure-callout\; label="h"\; filenames="A0310477000221.png"\; state="\{\{state\}\}">h</figure-callout>}}{2C_i}---\left(6\right)$

Through above-mentioned two steps, obtain circuit model as Figure 10.

The meaning of letter is as follows among Figure 10:

V_{I, k+1}Expression i node is at the k+1 voltage in step, i ∈ [1, n+1]

Resistance between expression i node and node i+1,$R_i^{*}=2L_i/h+R_i$

r_iThe equivalent resistance that expression is obtained by electric capacity i discretization, r_i=h/2C_i

El_{I, k+1}The equivalent current that expression obtains after by inductance i discretization, the current value through obtaining behind the Norton equivalent transformation is tried to achieve by formula (4) again, and direction is shown in Figure 10 arrow.

Ec_{I, k+1}Expression constantly self receive electric current by i node k+1 and merge by the equivalent current that the corresponding capacitance discretization obtains after total current, calculate according to formula (5), the sense of current is shown in Figure 10 arrow.

E_{I, k+1}The expression k+1 step flows into the current value of i node, and direction is shown in arrow among Figure 10.

4.3 Y type circuit is to the equivalent transformation of pi-network

General, for a Y type circuit, we can have conversion shown in Figure 11 wherein:$E_a=\frac{V_b-V_a}{R_{\mathrm{ab}}}-\frac{V_a}{R_{\mathrm{ac}}}+(\frac{R_a{I}_a}{R_{\mathrm{ab}}}-\frac{R_b{I}_b}{R_{\mathrm{ab}}})-(\frac{R_c{I}_c}{R_{\mathrm{ac}}}-\frac{R_a{I}_a}{R_{\mathrm{ac}}})---\left(8\right)$$E_b=\frac{V_a-V_b}{R_{\mathrm{ab}}}-\frac{V_b}{R_{\mathrm{bc}}}-(\frac{R_a{I}_a}{R_{\mathrm{ab}}}-\frac{R_b{I}_b}{R_{\mathrm{ab}}})-(\frac{R_c{I}_c}{R_{\mathrm{bc}}}-\frac{R_b{I}_b}{R_{\mathrm{bc}}})---\left(9\right)$

4.4 the equivalent transformation of parallel circuits is seen Figure 12$r_{\mathrm{total}}=1/(1/r_{l\mathrm{eft}}+1/r_{\mathrm{right}})---\left(10\right)$

i_total＝i_left+i_right?????????????????????——(11)

4.5 merge Middle Node, simplify obtaining final equivalent electric circuit

Recycle top conversion, a final electrical chain can be reduced to equivalent electric circuit shown in Figure 16.Describe its process (saving the mark of formula in the diagram) below in detail.

From chain, a Y type circuit part is transformed into pi-network, the part shown in circle frame among Figure 13.

Merge the parallel circuits part then, the part shown in roundlet frame among Figure 14.

After obtaining circuit, continue to do the equivalent transformation of Y type circuit to pi-network as Figure 15.

Repeat above step, up to the equivalent electric circuit that link is reduced to final following Figure 16.

Intermediate node (Middle Node) is all merged like this, and circuit is reduced to the equivalent electric circuit of only being made up of joint (Cross Node).

5. obtain the sparse matrix G of the circuit equation group of equivalent electric circuit

From formula (1) (2) (3) (6) (7) (10) (11) we as can be seen, by electric capacity and inductance discretization equivalent resistance only and electric capacity, the step-length of inductance and setting is relevant.Because these three parameters can not change in the dynamic analog analysis, so the value of all resistance can not change in the circuit after the discretization.

The circuit equation group shape of setting up according to kirchhoff as$G\&CenterDot;\stackrel{\&RightArrow;}{V}=\stackrel{\&RightArrow;}{I}$, wherein G is a sparse matrix, only lead with electricity (inverse of resistance) relevant with the structure of circuit, so a demand gets once and gets final product.

6. step counter K=0 is put in initialization simulation.Obtain the initial voltage value (this value should equal the initial voltage value of each node associated capacitance) of each node by the PWL oscillogram of each node, make up thus

7. if K＞M, then end simulation;

Otherwise execution following steps.

8. extract the electric current that receives of each unit of the K+1 step moment, and by calculating current vector

According to each unit receive electric current PWL waveform, utilize then

Merge the size that obtains equivalent current by electric capacity, inductance discretization then through equivalent transformation according to step (4) and formula (1) (2) (4) (5) (7) (11), final calculating is obtained each this equivalence constantly of node that crosses and is received electric current, obtains the K+1 current vector on equation group the right constantly

Bring the system of linear equations that obtains by step (5) into$G\&CenterDot;{\stackrel{\&RightArrow;}{V}}_{k+1}={\stackrel{\&RightArrow;}{I}}_{k+1}.$

Because the electric current that receives of unit changes in time, it is current time that the extraction K+1 step big or small process of receiving electric current constantly can be utilized (K+1) h, according to the corresponding PWL parameter in each unit, obtain it and receive current value accordingly then,

Detailed process as shown in figure 17.

9. the group of solving an equation obtains the K+1 step magnitude of voltage of all Cross Node constantly

Find the solution coefficient matrix and have system of linear equations sparse, symmetrical, positive definite character, the algorithm of a lot of existing efficient maturations is arranged at present.We adopt is a kind of conjugation tonsure method ICCG (Incomplete Cholesky Conjugate Gradient) that decomposes pre-excellent matrix based on incomplete Qiao Laisiji in the pre-excellent conjugation tonsure method (PCG, Precondition Conjugate Gradient).Find the solution finish after, obtain this magnitude of voltage of each Cross Node constantly, utilize vector

Expression.

10. recover to find the solution this magnitude of voltage constantly of each Middle Node

After obtaining this step of all Cross Node voltage constantly, recover to find the solution this step of two Middle Node between Cross Node magnitude of voltage constantly one by one according to following formula and process, reach purpose to all node sunykatuib analyses.Utilize following processes and formula to realize:${\mathrm{<figure-callout\; label="E"\; filenames="A0310477000213.png,A0310477000221.png"\; state="\{\{state\}\}">E</figure-callout>}}_{1,k+1}=\frac{V_{n+1,k+1}-{\mathrm{<figure-callout\; label="V"\; filenames="A0310477000213.png,A0310477000221.png"\; state="\{\{state\}\}">V</figure-callout>}}_{1,k+1}}{{\mathrm{<figure-callout\; label="R"\; filenames="A0310477000213.png,A0310477000221.png"\; state="\{\{state\}\}">R</figure-callout>}}_{1,n+1}^{\mathrm{equiv}}}+I_{1,n+1,k+1}^{\mathrm{equiv}}-{\mathrm{<figure-callout\; label="I"\; filenames="A0310477000213.png,A0310477000221.png"\; state="\{\{state\}\}">I</figure-callout>}}_{1,k+1}^{\mathrm{equiv}}-\frac{{\mathrm{<figure-callout\; label="V"\; filenames="A0310477000213.png,A0310477000221.png"\; state="\{\{state\}\}">V</figure-callout>}}_{1,k+1}}{{\mathrm{<figure-callout\; label="R"\; filenames="A0310477000213.png,A0310477000221.png"\; state="\{\{state\}\}">R</figure-callout>}}_1^{\mathrm{equiv}}};---\left(12\right)$

By j from 2 to N:$V_{j,k+1}=V_{j-1,k+1}+R_{j-1}^{*}(E_{j-1,k+1}-{\mathrm{el}}_{j-1,k+1});---\left(13\right)$$E_{j,k+1}=E_{j-1,k+1}+\frac{V_{j,k+1}}{r_j}+{\mathrm{ec}}_{j,k+1};---\left(14\right)$

So far, recovery calculates intermediate node (Middle Node) magnitude of voltage this moment between two nodes that cross (Cross Node).

11. the K+1 node voltage value in step is preserved in output, this step sunykatuib analysis finishes.Put K=K+1, carry out next step simulation.

Embodiment

We adopt one to generate ourselves, but do not lose example explanation the specific embodiment of the present invention of general proxy property, carry out according to top flow chart.

This example vertical view (18) of 8 * 8, each point among the figure (is labeled as^*Perhaps) working cell in the indication circuit (cell), just we want the node of analysis mode, and they have the electric current of receiving and associated capacitance over the ground.On each bar line resistance and inductance are arranged, shown in following partial enlarged drawing.In this example, we utilize a supply rings of outside to represent power supply, and it can logic is seen as a node.According to the definition on top, obviously be labeled as the Middle Node that () is, be labeled as (^*) the Cross Node that is.Be the part in the middle of two Cross Node points in the circle frame among the figure, its side circuit is shown in figure (19), and following explanation will illustrate that mainly other parts by that analogy round this section local circuit.

1. read in the circuit information file, comprise in the file: the relational structure between the node; The time dependent current waveform (utilizing PWL to represent) that receives of the supply module unit that the resistance value between the node, inductance value, inductance initial voltage and current value, capacitance, electric capacity initial voltage and current value and each node are connected.In computer, set up the information of circuit in view of the above, and all intermediate points of mark (Middle Node) and joint (Cross Node).

2. set the time step h=T/120 of simulation, T is the work period of circuit.The total step number M=240 of simulation is equivalent to simulate two cycles

3. according to 3.1 and 3.2 process discrete circuit.Link in the illustration is transformed to (20) model as figure.

4. merge all intermediate nodes (Middle Node), set up the equivalent electric circuit of forming by the node that crosses (Cross Node)

The method of utilizing promise in 4.1 and 4.2 the process to pause (Norton) law of equivalence and merging current source is simplified circuit, obtains the circuit model as figure (21)

Utilize 4.3,4.4 and 4.5 processes to simplify link, form final equivalent electric circuit, shown in figure (22).

To all links, make above process.Merge all Middle Node, obtain the equivalent electric circuit of only forming by Cross Node.Original 65 points are reduced to 17 points, significantly dwindle circuit scale, thereby improve the speed of finding the solution and reduce memory requirements.Shown in figure (23).

5. obtain the sparse matrix G of the circuit equation group of equivalent electric circuit, according to the circuit structure of figure (21) and resistance value wherein, the sparse matrix G of equationof structure group.

6. beginningization simulation makes step counter K=0.Obtain the initial voltage value (this value should equal the initial voltage value of each node associated capacitance) of each node by the PWL oscillogram of each node, make up thus

7. if K＞M, end simulation then,

Otherwise execution following steps.

8. extract the electric current that receives of each unit of the K+1 step moment, and obtain current vector

According to time parameter (K+1) h, extract the current value that receives in this moment of each supply node, then according to the process and the formula (1) (2) (4) (5) (7) (11) of (4.3), (4.4) and (4.5), calculate the equivalent associated current value of each Cross Node, merging obtains current vector thenSet up the circuit system of linear equations$G\&CenterDot;{\stackrel{\&RightArrow;}{V}}_{k+1}={\stackrel{\&RightArrow;}{I}}_{k+1}$

9. utilize ICCG method solving equation group, obtain the magnitude of voltage of all nodes that cross (Cross Node) among K+1 moment Figure 22

10. recover to find the solution this magnitude of voltage constantly of each Middle Node

After obtaining this voltage constantly of all Cross Node, recover to find the solution this magnitude of voltage constantly of all Middle Node, reach the purpose of analyzing all nodes.

11. output is preserved this moment node voltage to output file.The simulation of this step finishes, and K=K+1 begins next step simulation.

Because the analysis and solution of power-line network and earth cord network is similarly, so the present invention only provides the analysis and solution method of power-line network.The present invention is equally applicable to the analysis and solution of earth cord network.

This method is at CPU450M, simulation test run on the Sun Solaris V880 work station of internal memory 2G, and all codes utilize the C language compilation, and compiler is GNU gcc 2.95.1 version.

The present invention is satisfying under the prerequisite of precision, not only fast but also utilize internal memory little, is applicable to the more test of monster chip.

Claims (2)

Translated fromChinese

1.基于等效电路的集成电路电源网络瞬态分析求解的方法，含有基于直流分析的对电源线/电线网络进行瞬态分析的方法，其特点在于：它是一种利用计算机针对专用集成电路(ASIC)的电源线/地线网络大量含有链状拓扑结构的特点，把链路中间节点的RLC电路的参数R、L、C和电流源等效到这条链路两端节点上，再对于仅由所有链路的两端节点构成的等效电路，列出线性方程组，利用现有的方法快速求解出此时刻等效电路的所有链路各端点的电压值，再据此求出所有链路中被合并节点此时刻的电压值的既快速又节约计算机内存的方法。1. The method for transient analysis and solution of integrated circuit power supply network based on equivalent circuit, including the method for transient analysis of power line/wire network based on DC analysis, and its characteristic is that it is a method for using a computer to target specific integrated circuits The (ASIC) power line/ground network has a large number of chain topology features, and the parameters R, L, C and current source of the RLC circuit at the middle node of the link are equivalent to the nodes at both ends of the link, and then For an equivalent circuit consisting only of nodes at both ends of all links, list the linear equations, use existing methods to quickly solve the voltage values at each end of all links of the equivalent circuit at this moment, and then calculate A fast and computer-memory-saving method of merging the voltage values of nodes at this moment in all links.2.根据权利要求1所述的基于等效电路的集成电路电源网络瞬态分析求解的方法，其特点在于，它依次含有以下步骤：2. the method for the transient analysis solution of the integrated circuit power supply network based on equivalent circuit according to claim 1, is characterized in that, it contains following steps successively:(1)计算机读入电路的信息文件，文件中包括节点之间的关联结构；节点之间的电阻值、电感值、电感初始电压和电流值、电容值、电容初始电压和电流值以及各个节点连接的供电模块单元的随时间变化的吸纳电流波形(利用PWL表示)，据此在计算机内建立电路的信息，并且标记所有中间点(Middle Node)和交汇点(Cross Node)；(1) The computer reads the information file of the circuit, which includes the associated structure between nodes; the resistance value, inductance value, initial voltage and current value of the inductor, capacitance value, initial voltage and current value of the capacitor, and each node The time-varying sink current waveform (indicated by PWL) of the connected power supply module unit, based on which the information of the circuit is established in the computer, and all intermediate points (Middle Node) and intersection points (Cross Node) are marked;(2)根据电路的工作周期和需要模拟的周期数，计算机分别读入相应的时间步长h和总模拟步数M；(2) According to the working cycle of the circuit and the number of cycles to be simulated, the computer reads in the corresponding time step h and the total number of simulation steps M;(3)离散化原始电路中的电容、电感，得到由电阻、电流源组成的电路：(3) Discretize the capacitance and inductance in the original circuit to obtain a circuit composed of resistance and current source:(3.1)离散化电路中的电容C和电阻L，(3.1) Capacitance C and resistance L in the discretization circuit,给定模拟的时间步长，利用梯形差分公式，K+1时刻电容离散化为一个等效电阻和一个等效电流源$\frac{2C}{h}{V}_{c,k}+I_{c,k}$并联的模型，$I_{c,k+1}=\frac{2C}{h}{V}_{c,k+1}-(\frac{2C}{h}{V}_{c,k}+I_{c,k})---\left(1\right),$Given the time step of the simulation, using the trapezoidal difference formula, the capacitance at time K+1 is discretized into an equivalent resistance and an equivalent current source$\frac{2C}{h}{V}_{c,k}+I_{c,k}$ Parallel models,$I_{c,k+1}=\frac{2C}{h}{V}_{c,k+1}-(\frac{2C}{h}{V}_{c,k}+I_{c,k})---\left(1\right),$V_c，k，I_c，k，V_c，k+1，I_c，k+1分别代表K和K+1时刻电容上的电压和电流，其方向保持一致；V_{c , k} , I_{c , k} , V_{c , k+1} , I_{c , k+1} respectively represent the voltage and current on the capacitor at K and K+1, and their directions are consistent;给定模拟的时间步长，利用梯形差分公式，K+1时刻电感离散化为一个等效电阻和一个等效电流源$\frac{h}{2L}{V}_{L,k}+I_{L,k}$并联的模型，$I_{L,k+1}=\frac{h}{2L}{V}_{L,k+1}+(\frac{h}{2L}{V}_{L,k}+I_{L,k})---\left(2\right),$Given the time step of the simulation, using the trapezoidal difference formula, the inductance is discretized into an equivalent resistance at time K+1 and an equivalent current source$\frac{h}{2L}{V}_{L,k}+I_{L,k}$ Parallel models,$I_{L,k+1}=\frac{h}{2L}{V}_{L,k+1}+(\frac{h}{2L}{V}_{L,k}+I_{L,k})---\left(2\right),$V_L，k，I_L，k，V_L，k+1，I_L，k+1分别代表k和k+1时刻电感上的电压和电流，其方向保持一致；V_{L, k} , I_{L, k} , V_{L, k+1} , I_{L, k+1} represent the voltage and current on the inductor at k and k+1 respectively, and their directions are consistent;(3.2)根据(3.1)中的离散化过程，建立原始电路的离散化模型；(3.2) According to the discretization process in (3.1), the discretization model of the original circuit is established;(4)合并所有的中间节点(Middle Node)，建立由交汇节点(Cross Node)组成的等效电路：(4) Merge all the middle nodes (Middle Node), and establish an equivalent circuit composed of cross nodes (Cross Node):(4.1)利用诺顿(Norton)等效定律合并电流源以简化电路，(4.1) Utilize Norton's (Norton's) equivalent law to incorporate the current source to simplify the circuit,对于一条含有N+1个节点的链路，从左到右把节点标记为1到N+1，把链路上相邻节点i和i+1(1＜i＜N)之间的电阻R_i和K+1时刻离散化电感组成的串联电路简化为由等效电阻和等效电流源el_i，k+1组成的并联电路：$R_i^{*}={2L}_i/h+R_i---\left(3\right),$${\mathrm{el}}_{i,k+1}=(\frac{h}{{2L}_i}{V}_{L,i,k}+E_{i,k})\&CenterDot;\frac{2L_i/h}{{2L}_i/h+R_i}---\left(4\right),$For a link containing N+1 nodes, mark the nodes as 1 to N+1 from left to right, and mark the resistance R between adjacent nodes i and i+1 (1<i<N) on the link The series circuit composed of discretized inductance at time_i and K+1 is simplified to an equivalent resistance And the parallel circuit composed of equivalent current source el_{i, k+1} :$R_i^{*}={2L}_i/h+R_i---\left(3\right),$${\mathrm{el}}_{i,k+1}=(\frac{h}{{2L}_i}{V}_{L,i,k}+{\mathrm{E.}}_{i,k})\&CenterDot;\frac{2L_i/h}{{2L}_i/h+R_i}---\left(4\right),$R_i、L_i分别为节点i和节点i+1之间的电阻和电感值；R_i and L_i are the resistance and inductance values between node i and node i+1 respectively;V_L，i，k，E_i，k分别为K时刻L_i上的电流和电压值，方向由i+1节点到i节点；V_{L, i, k} , E_{i, k} are the current and voltage values on L_i at time K respectively, and the direction is from node i+1 to node i;el_i，k+1是等效简化后的与并联的等效电流源；el_{i, k+1} is the equivalent simplified AND parallel equivalent current sources;(4.2)合并节点i上的对地电流源，(4.2) Merge the ground-to-ground current source on node i,在K+1时刻对于节点i，把模块单元的吸纳电流e_i，k+1和离散化电容C_i得到的效For node i at time K+1, the effect obtained by combining the absorbing current e_{i of the module unit, k+1} and the discretized capacitance C_i电路合并成由电流源ec_i，k+1和电阻r_i并联组成的电路：${\mathrm{ec}}_{i,k+1}=e_{i,k+1}-(\frac{2C_i}{h}{V}_{i,k}+I_{i,k})---\left(5\right),$$r_i=\frac{h}{2C_i}---\left(6\right)$The circuits are combined into a circuit consisting of a current source ec_i,k+1 and a resistance_ri connected in parallel:${\mathrm{ec}}_{i,k+1}=e_{i,k+1}-(\frac{2C_i}{h}{V}_{i,k}+I_{i,k})---\left(5\right),$$r_i=\frac{h}{2C_i}---\left(6\right)$C_i分别为节点i对地的关联电容值；C_i are the associated capacitance values of node i to ground;V_i，k，I_i，k分别为K时刻节点i上的电压值和通过电容的电流值，方向对地；V_{i, k} , I_{i, k} are the voltage value on node i and the current value passing through the capacitor at time K respectively, and the direction is to the ground;ec_i，k+1表示由i节点K+1时刻自身吸纳电流和由相应电容离散化得到的等效电ec_{i, k+1} represents the equivalent electric current absorbed by the i node at K+1 moment and the discretization of the corresponding capacitance流合并后的总电流，按照公式(5)计算得到，电流方向对地；The total current after the combined flow is calculated according to the formula (5), and the current direction is to the ground;(4.3)Y型电路向π型电路的等效变换：(4.3) Equivalent transformation from Y-type circuit to π-type circuit:把由三个依次相邻的节点与地(GND)组成的Y型电路等效变换为两个端点与地组成的的π型电路；The Y-type circuit composed of three consecutive adjacent nodes and the ground (GND) is equivalently converted into a π-type circuit composed of two terminals and the ground;一般的，设Y电路的三个节点为x、y、z(接地)，中间节点为o，Y型电路的结构为：In general, let the three nodes of the Y circuit be x, y, z (grounded), the middle node is o, and the structure of the Y circuit is:端点x、o间：由电阻R_x和电流源I_x(方向为o到x)并联组成，Between terminals x and o: composed of resistance R_x and current source I_x (direction from o to x) connected in parallel,端点y、o间：由电阻R_y和电流源I_y(方向为o到y)并联组成，Between terminals y and o: composed of resistance R_y and current source I_y (direction from o to y) connected in parallel,端点z、o间：由电阻R_z和电流源I_z(方向为o到z)并联组成，Between terminals z and o: It is composed of resistance R_z and current source I_z (direction is from o to z) connected in parallel,等效后节点x、y和z组成的π型电路的结构为：The structure of the π-type circuit composed of nodes x, y and z after equivalent is:节点x、y之间由等效电阻R_xy和等效电流源I_xy并联组成，其中：$R_{\mathrm{xy}}=\frac{R_x{R}_y+R_x{R}_z+R_y{R}_z}{R_z},I_{\mathrm{xy}}=\frac{R_x{I}_x-R_y{I}_y}{R_{\mathrm{xy}}}---\left(7.1\right),$The connection between nodes x and y is composed of equivalent resistance R_xy and equivalent current source I_xy in parallel, where:$R_{\mathrm{xy}}=\frac{R_x{R}_{\mathrm{the\; y}}+R_x{R}_z+R_{\mathrm{the\; y}}{R}_z}{R_z},I_{\mathrm{xy}}=\frac{R_x{I}_x-R_{\mathrm{the\; y}}{I}_{\mathrm{the\; y}}}{R_{\mathrm{xy}}}---\left(7.1\right),$节点x、z之间由等效电阻R_xz和等效电流源I_xz并联组成，其中：$R_{\mathrm{xz}}=\frac{R_x{R}_y+R_x{R}_z+R_y{R}_z}{R_y},I_{\mathrm{xz}}=\frac{R_z{I}_z-R_x{I}_x}{R_{\mathrm{xy}}}---\left(7.2\right),$Between nodes x and z is composed of parallel connection of equivalent resistance R_xz and equivalent current source I_xz , where:$R_{\mathrm{xz}}=\frac{R_x{R}_{\mathrm{the\; y}}+R_x{R}_z+R_{\mathrm{the\; y}}{R}_z}{R_{\mathrm{the\; y}}},I_{\mathrm{xz}}=\frac{R_z{I}_z-R_x{I}_x}{R_{\mathrm{xy}}}---\left(7.2\right),$节点y、z之间由等效电阻R_yz和等效电流源I_yz并联组成，其中：$R_{\mathrm{yz}}=\frac{R_x{R}_y+R_x{R}_z+R_y{R}_z}{R_x},I_{\mathrm{xz}}=\frac{R_z{I}_z-R_y{I}_y}{R_{\mathrm{yz}}}---\left(7.3\right),$The connection between nodes y and z is composed of equivalent resistance R_yz and equivalent current source I_yz in parallel, where:$R_{\mathrm{yz}}=\frac{R_x{R}_{\mathrm{the\; y}}+R_x{R}_z+R_{\mathrm{the\; y}}{R}_z}{R_x},I_{\mathrm{xz}}=\frac{R_z{I}_z-R_{\mathrm{the\; y}}{I}_{\mathrm{the\; y}}}{R_{\mathrm{yz}}}---\left(7.3\right),$因此，流入节点x的电流大小为：$E_x=\frac{V_y-V_x}{R_{\mathrm{xy}}}-\frac{V_x}{R_{\mathrm{xz}}}+\left(\frac{R_x{I}_x-R_y{I}_y}{R_{\mathrm{xy}}}\right)-\left(\frac{R_z{I}_z-R_x{I}_x}{R_{\mathrm{xz}}}\right)---\left(8\right),$Therefore, the magnitude of the current flowing into node x is:${\mathrm{E.}}_x=\frac{V_{\mathrm{the\; y}}-V_x}{R_{\mathrm{xy}}}-\frac{V_x}{R_{\mathrm{xz}}}+\left(\frac{R_x{I}_x-R_{\mathrm{the\; y}}{I}_{\mathrm{the\; y}}}{R_{\mathrm{xy}}}\right)-\left(\frac{R_z{I}_z-R_x{I}_x}{R_{\mathrm{xz}}}\right)---\left(8\right),$流入节点y的电流大小为：$E_y=\frac{V_x-V_y}{R_{\mathrm{xy}}}-\frac{V_y}{R_{\mathrm{yz}}}-\left(\frac{R_x{I}_x-R_y{I}_y}{R_{\mathrm{xy}}}\right)-\left(\frac{R_z{I}_z-R_y{I}_y}{R_{\mathrm{yz}}}\right)---\left(9\right),$The magnitude of the current flowing into node y is:${\mathrm{E.}}_{\mathrm{the\; y}}=\frac{V_x-V_{\mathrm{the\; y}}}{R_{\mathrm{xy}}}-\frac{V_{\mathrm{the\; y}}}{R_{\mathrm{yz}}}-\left(\frac{R_x{I}_x-R_{\mathrm{the\; y}}{I}_{\mathrm{the\; y}}}{R_{\mathrm{xy}}}\right)-\left(\frac{R_z{I}_z-R_{\mathrm{the\; y}}{I}_{\mathrm{the\; y}}}{R_{\mathrm{yz}}}\right)---\left(9\right),$(4.4)并联电路的等效变换：(4.4) Equivalent transformation of parallel circuit:对两个节点之间的并联电路作合并简化变换：$r_{\mathrm{total}}=1/(1/r_{\mathrm{left}}+1/r_{\mathrm{right}})---\left(10\right),$Merge simplification for a parallel circuit between two nodes:$r_{\mathrm{total}}=1/(1/r_{\mathrm{left}}+1/r_{\mathrm{right}})---\left(10\right),$i_total＝i_left+i_right               ——(11)，i_total = i_left + i_right - (11),r_left，r_right，i_left，i_right，分别表示两个电阻和电流源的大小；r_left , r_right , i_left , i_right represent the size of the two resistors and the current source respectively;r_total，i_total分别表示合并后的总电阻和总电流源的大小；r_total , i_total represent the size of the combined total resistance and total current source respectively;(4.5)合并Middle Node，简化得到最终的等效电路：(4.5) Merge Middle Node and simplify to obtain the final equivalent circuit:反复利用上面的原理和步骤，合并每条链路的中间节点(Middle Node)，得到每条链路的π型等效电路，对于一条含有N+1个节点的链路(从左向右标记为1到N+1)，最终的π型等效电路结构如下：Repeatedly use the above principles and steps to merge the middle nodes (Middle Node) of each link to obtain the π-type equivalent circuit of each link. For a link containing N+1 nodes (marked from left to right is 1 to N+1), the final π-type equivalent circuit structure is as follows:端点1，N+1间：等效电阻和等效电流源(方向N+1到1)并联；Between terminal 1 and N+1: equivalent resistance and an equivalent current source (direction N+1 to 1) in parallel;端点1，GND间：等效电阻和等效电流源(方向1到GND)并联；Between terminal 1 and GND: equivalent resistance and an equivalent current source (direction 1 to GND) in parallel;端点N+1，GND间：等效电阻

和等效电流源

(方向N+1到GND)并联；Between terminal N+1 and GND: equivalent resistance

and an equivalent current source

(direction N+1 to GND) in parallel;最终将电路简化为只有交汇结点(Cross Node)组成的简化的等效电路；Finally, the circuit is simplified to a simplified equivalent circuit composed of only Cross Nodes;(5)据基尔霍夫(Kirchhoff)定律建立由步骤(4.5)得到的等效电路的节点电压方程组$G\&CenterDot;\stackrel{\&RightArrow;}{V}=\stackrel{\&RightArrow;}{I}$，从而得到只与电路结构和电阻有关的稀疏系数矩阵G；(5) Establish the node voltage equations of the equivalent circuit obtained in step (4.5) according to Kirchhoff's law$G\&Center\; Dot;\stackrel{\&Right\; Arrow;}{V}=\stackrel{\&Right\; Arrow;}{I}$ , so as to obtain the sparse coefficient matrix G that is only related to the circuit structure and resistance;(6)始化模拟，令步骤计数器K＝0，由每一个节点的PWL波形图得到各个节点的初始电压值(此值应该等于各个节点关联电容的初始电压值)，由此构建(6) Initialize the simulation, make the step counter K=0, obtain the initial voltage value of each node from the PWL waveform diagram of each node (this value should be equal to the initial voltage value of the associated capacitance of each node), thus construct(7)若K＞M，则结束模拟；(7) If K>M, then end the simulation;否则执行以下步骤：Otherwise perform the following steps:(8)通过每一个节点的PWL波形提取K+1步骤时刻各个节点供电模块单元的吸纳电流，计算得到K+1时刻方程组右边的电流向量

带入由步骤(5)得到的线性方程组：$G\&CenterDot;{\stackrel{\&RightArrow;}{V}}_{k+1}={\stackrel{\&RightArrow;}{I}}_{k+1}$(8) Extract the absorbing current of each node power supply module unit at K+1 step time through the PWL waveform of each node, and calculate the current vector on the right side of the equation group at K+1 time

Bring in the system of linear equations obtained by step (5):$G\&CenterDot;{\stackrel{\&Right\; Arrow;}{V}}_{k+1}={\stackrel{\&Right\; Arrow;}{I}}_{k+1}$此步骤根据每一个节点的供电模块单元吸纳电流的PWL波形，提取此时刻它们的电流值大小，然后利用根据公式(1)(2)(4)(5)(7)(11)合并由电容、电感离散化然后经过等效变换得到等效电流的大小，最终求出每一个交汇节点此时刻的等效吸纳电流，构成向量In this step, according to the PWL waveform of the current absorbed by the power supply module unit of each node, extract their current value at this moment, and then use According to the formula (1)(2)(4)(5)(7)(11) combined with the discretization of capacitance and inductance and then through equivalent transformation to obtain the size of the equivalent current, and finally calculate the equivalent current of each intersection node at this moment The effect of absorbing current constitutes a vector(9)用现有方法求解方程组$G\&CenterDot;{\stackrel{\&RightArrow;}{V}}_{k+1}={\stackrel{\&RightArrow;}{I}}_{k+1},$得到K+1时刻交汇节点的电压值向量(9) Solving equations with existing methods$G\&Center\; Dot;{\stackrel{\&Right\; Arrow;}{V}}_{k+1}={\stackrel{\&Right\; Arrow;}{I}}_{k+1},$ Get the voltage value vector of the junction node at K+1 time(10)恢复求解每一个中间节点此时刻的电压值：$E_{1,k+1}=\frac{V_{n+1,k+1}-V_{1,k+1}}{R_{1,n+1}^{\mathrm{equiv}}}+I_{1,n+1,k+1}^{\mathrm{equiv}}-I_{1,k+1}^{\mathrm{equiv}}-\frac{V_{1,k+1}}{R_1^{\mathrm{equiv}}},$(10) Resume solving the voltage value of each intermediate node at this moment:${\mathrm{E.}}_{1,k+1}=\frac{V_{\mathrm{no}+1,k+1}-V_{1,k+1}}{R_{1,\mathrm{no}+1}^{\mathrm{Equiv}}}+I_{1,\mathrm{no}+1,k+1}^{\mathrm{Equiv}}-I_{1,k+1}^{\mathrm{Equiv}}-\frac{V_{1,k+1}}{R_1^{\mathrm{Equiv}}},$V_1，k+1，V_n+1，k+1为K+1时刻两个交汇点的电压值，V_{1, k+1} , V_{n+1, k+1} are the voltage values of the two junctions at K+1 time,然后由节点i从2到N，求出此链路所有中间节点的K+1时刻的电压值：$V_{i,k+1}=V_{i-1,k+1}+R_{i-1}^{*}(E_{i-1,k+1}-{\mathrm{el}}_{i-1,k+1}),$$E_{i,k+1}=E_{i-1,k+1}+\frac{V_{i,k+1}}{r_i}+{\mathrm{ec}}_{i,k+1},$Then from node i from 2 to N, calculate the voltage value of all intermediate nodes of this link at K+1 time:$V_{i,k+1}=V_{i-1,k+1}+R_{i-1}^{*}({\mathrm{E.}}_{i-1,k+1}-{\mathrm{el}}_{i-1,k+1}),$${\mathrm{E.}}_{i,k+1}={\mathrm{E.}}_{i-1,k+1}+\frac{V_{i,k+1}}{r_i}+{\mathrm{ec}}_{i,k+1},$V_i，k+1表示i节点在K+1步的电压，i∈[1，n+1]；V_{i, k+1} represents the voltage of node i at step K+1, i∈[1,n+1];表示i节点与节点i+1之间的电阻，$R_i^{*}={2L}_i/h+R_i;$Indicates the resistance between node i and node i+1,$R_i^{*}={2L}_i/h+R_i;$r_i表示由电容i离散化得到的等效电阻，r_i＝h/2C_i；r_i represents the equivalent resistance obtained from the discretization of capacitance i, r_i =h/2C_i ;el_i，k+1表示由电感i离散化后得到的等效电流，再经过Norton等效变换后所得到的电流离散化得到的电流值，由公式(4)求得，方向由节点i+1到节点i；el_{i, k+1} represents the equivalent current obtained by the discretization of the inductance i, and then the current value obtained by the discretization of the current obtained after the Norton equivalent transformation, which is obtained by the formula (4), and the direction is determined by the node i+ 1 to node i;ec_i，k+1表示由i节点K+1时刻自身吸纳电流和由相应电容离散化得到的等效电流合并后的总电流，按照公式(6)计算得到，电流方向由节点i到地；ec_{i, k+1} represents the total current combined by the current absorbed by itself at node i K+1 and the equivalent current obtained from the discretization of the corresponding capacitance, calculated according to formula (6), and the current direction is from node i to ground;E_i，k+1表示K+1步流入i节点的电流值，方向由节点i+1到节点i；E_{i, k+1} represents the current value flowing into node i in K+1 steps, and the direction is from node i+1 to node i;(11)输出保存K+1时刻的所有节点的电压值，置K＝K+1，转到步骤(7)，进行下一步模拟过程。(11) Output and save the voltage values of all nodes at time K+1, set K=K+1, go to step (7), and proceed to the next simulation process.

Images