CN1355561A - Manufacturing method of thin film transistor flat panel display - Google Patents

Abstract

A method for manufacturing a thin film transistor flat panel display comprises forming a first metal layer on the surface of a glass substrate, and performing a first photolithography and etching process to form a gate electrode and a pad electrode. An insulating layer, a semiconductor layer and a doped silicon conducting layer are sequentially formed on the glass substrate, and a second yellow light and etching manufacturing process is carried out to define an active area and a connecting pad opening. And forming a transparent conductive layer and a second metal layer on the glass substrate, performing a third photolithography and etching process, and forming a source and a drain in the transistor region. Forming a protective layer on the glass substrate, performing a fourth photolithography and etching process, and performing an oxidation reaction.

Description

The manufacture method of film transistor plane indicator

The present invention relates to a kind of manufacture method of film transistor plane indicator, particularly relate to four yellow-light etching process of a kind of use (photo-etching-process, the manufacture method of Thin Film Transistor-LCD PEP).

Thin Film Transistor-LCD ((Thin Film Transistor Liquid Crystal Display, hereinafter to be referred as TFT-LCD) mainly be the thin-film transistor that utilizes into rectangular arrangement, cooperate electronic components such as suitable electric capacity, connection gasket to drive liquid crystal pixel, enrich beautiful figure with generation.The electronic component of TFT-LCD has consisted essentially of a transparency carrier (transparent substrate), has scan line (scan line) and holding wire (signal line), a filter (color filter) and the liquid crystal material between transparency carrier and filter of thin-film transistor that an array formula arranges, pixel electrode (pixel electrode), orthogonal staggered (orthogonal) on it.

Please refer to Fig. 1 to Fig. 5, Fig. 1 to Fig. 5 is the existing method schematic diagram of making a TFT-LCD electronic component.As shown in Figure 1, existing TFT-LCD is produced on thetransparency carrier 10, andtransparency carrier 10 is one by high purifying silicon dioxide (high-purified SiO₂) transparent glass substrate that constituted, be provided with a transistor (transistor) district A and a connection gasket (pad) district B on its surface at least, to be used for formingtransistor 20 and connection gasket 30 respectively.

Existing method forms afirst metal layer 11 prior totransparency carrier 10 surfaces, and carry out one first yellow-light etching process (PEP), form agate electrode 12 withtransparency carrier 10 surfaces, and form apad electrode 14 ontransparency carrier 10 surfaces of connection gasket district B respectively at transistor area A.

As shown in Figure 2, then carry out a chemical vapour deposition (CVD) manufacture craft (chemical vapordeposition process, CVD), the insulating barrier (isolation layer) 16 that forms by silicon nitride (siliconnitride) attransparency carrier 10 surperficial uniform depositions one, thickness is about 4000 dusts (angstrom), and form one in regular turn by amorphous silicon (amorphous silicon, a-Si)semiconductor layer 18 of Gou Chenging and doped silicon (doped silicon)conductive layer 22 oninsulating barrier 16 surfaces.

As shown in Figure 3, carry out one second yellow-light etching process, in transistor area A, form the pattern of doped siliconconductive layer 22 andsemiconductor layer 18, to limit an active area 23.In connection gasket district B, carry out one the 3rd yellow-light etching process then, removepad electrode 14 tops doped siliconconductive layer 22,semiconductor layer 18, withinsulating barrier 16, to form theopening 24 of connection gasket district B,pad electrode 14 is exposed in theopening 24.

As shown in Figure 4, carry out another CVD manufacture craft to deposit atransparency conducting layer 25 and onesecond metal level 26 intransparency carrier 10 surfaces in regular turn comprehensively.(indiumtin oxide ITO) forms, as pixel electrode (pixel electrode)transparency conducting layer 25 by tin indium oxide.Then carry out one the 4th yellow-light etching process, to form the passage 27 onsensible semiconductor layer 18 surfaces togate electrode 12 tops in transistor area A.Passage 27 is separated into two districts withsecond metal level 26,transparency conducting layer 25 with doped siliconconductive layer 22, to form an one source pole 26a and a drain electrode 26b respectively.

As shown in Figure 5, intransistor 20 and connection gasket 30 surperficial uniform deposition one protective layers (passivation layer) 28,protective layer 28 can be inserted in the passage 27 at last.Then, carry out one the 5th yellow-light etching process, remove thesubstrate 10 topprotective layers 28 andsecond metal level 26, transistor area Atransparency conducting layer 25 is in addition come out, and finish the making of electronic component in the Thin Film Transistor-LCD.

Existing method uses five road yellow-light etching process to limit grid and the pattern that fills up electrode, active area, connection gasket district opening, source electrode and drain electrode and pixel electrode in regular turn respectively, the manufacturing process of whole Thin Film Transistor-LCD is still quite tediously long and complicated, and the image quality of display is not very good yet, remains further to be improved.

The object of the present invention is to provide a kind of Thin Film Transistor-LCD manufacture craft of simplifying, and can improve the manufacture method of display image quality.

The object of the present invention is achieved like this, a kind of manufacture method of film transistor plane indicator promptly is provided, this display is produced on the substrate (substrate), this substrate includes at least one transistor (transistor) district and at least one connection gasket (pad) district, be used for forming a transistor and a connection gasket respectively, this manufacture method includes the following step: (1) forms a first metal layer on this substrate surface; (2) (photo-etching-process PEP) limits the pattern (pattern) of this first metal layer, to form a gate electrode and a pad electrode respectively in this transistor area and this connection gasket district to carry out one first yellow-light etching process; (3) on this substrate, form an insulating barrier, semi-conductor layer and a doped silicon (doped silicon) conductive layer in regular turn; (4) carry out the pattern that one second yellow-light etching process limits this doped silicon conductive layer, this semiconductor layer and this insulating barrier, in this connection gasket district, limit an open area, remove outside (a) this transistor area simultaneously and (b) this connection gasket district outer with this open area in this insulating barrier, this semiconductor layer, and this doped silicon conductive layer, come out with this connection gasket district exposure of substrates in addition beyond so making this transistor area, and form an opening in this connection gasket district, make this pad electrodes exposed in this opening; (5) on this substrate, form a transparency conducting layer and one second metal level in regular turn, and this transparency conducting layer and this second metal level are inserted in this opening; (6) carry out the pattern that one the 3rd yellow-light etching process limits this second metal level, in this transistor area, limit a channel region earlier, remove this second metal level in this channel region, be shade with this second metal level afterwards, remove this transparency conducting layer and this doped silicon conductive layer of this channel region, this semiconductor layer is exposed in this passage; (7) on this substrate, form a protective layer (passivation layer), and make it cover this passage fully; And (8) carry out one the 4th yellow-light etching process; limit the pattern of this protective layer and this second metal level; remove (a) this transistor area outer with (b) this connection gasket district outside reach this protective layer and this second metal level in this opening, so make this transparency conducting layer be exposed in this opening, this transistor area is outer, and this connection gasket district outside the zone.

Carry out a heat treatment (thermal process) step at last, make the protective layer soft heat and cover transistor area and the connection gasket district in the sidewall of second metal level.Utilize a heat treatment to protect second metal level at last, make it be unlikely the pollution liquid crystal, therefore can reach and reduce manufacturing process steps number of times and the purpose of improving image quality.

Below in conjunction with accompanying drawing, describe embodiments of the invention in detail, wherein:

Fig. 1 to Fig. 5 is the manufacture method schematic diagram of the electronic component of existing film transistor plane indicator;

Fig. 6 to Figure 12 is the manufacture method schematic diagram of the electronic component of film transistor plane indicator of the present invention.

Please refer to Fig. 6 to Figure 12, Fig. 6 to Figure 12 is the manufacture method schematic diagram of film transistor plane indicator of the present invention.As shown in Figure 6, film transistor plane indicator is produced on thetransparency carrier 40,transparency carrier 40 is a transparent glass substrate that is made of high purifying silicon dioxide, and its surface is provided with a transistor area C and a connection gasket district D at least, to be used for formingtransistor 50 andconnection gasket 60 respectively.

The present invention forms a first metal layer 41 ontransparency carrier 40 surfaces earlier, is generally chromium or titanium.Then carry out one first yellow-light etching process, utilize a photoresist to limit and an etching process,transparency carrier 40 surfaces respectively at transistor area C form agate electrode 42, and form apad electrode 44 ontransparency carrier 40 surfaces of connection gasket district D.

As shown in Figure 7, then carrying out a film forming manufacture craft, for example is the chemical vapor deposition (CVD) manufacture craft, atwhole transparency carrier 40 surperficial uniform deposition oneinsulating barriers 46, thickness is about 4000 dusts, and formssemi-conductor layer 48 and doped siliconconductive layer 52 in regular turn oninsulating barrier 46surfaces.Semiconductor layer 48 can be made up of amorphous silicon (a-Si) or polysilicon.

As shown in Figure 8, carry out a photoresist and limit second yellow-light etching process that makes up with an etching process, form the pattern of doped siliconconductive layer 52,semiconductor layer 48 andinsulating barrier 46, to form anactive area 53 and in connection gasket district D, to form anopening 54 at transistor area C simultaneously.In this step, on connection gasket district D, limit an open area earlier, remove outside (a) transistor area C simultaneously and (b) connection gasket district D outer with the open area ininsulating barrier 46,semiconductor layer 48, and doped siliconconductive layer 52, come out with this connection gasket district D exposure of substrates in addition beyond so making transistor area C, and,pad electrode 44 is exposed in theopening 54 in connection gasket district D formation opening 54.

As shown in Figure 9, carry out a film forming manufacture craft and deposit atransparency conducting layer 56 and onesecond metal level 58 intransparency carrier 40 surfaces in regular turn.Transparency conductinglayer 56 is made up of tin indium oxide (ITO) usually, as pixel electrode.Then carry out one the 3rd yellow-light etching process, utilize a photoresist to limit and an etching process,, removesecond metal level 58 in the channel region prior to limiting a channel region in the transistor area C in transistor area C.Afterwards, be shade withsecond metal level 58 again, remove thetransparency conducting layer 56 and doped siliconconductive layer 52 of channel region,semiconductor layer 48 is exposed in the passage 62.Passage 62 is separated into two districts withmetal level 58,transparency conducting layer 56 and doped siliconconductive layer 52, to form an onesource pole 58a and adrain electrode 58b respectively.

As shown in figure 10,, and carry out one the 4th yellow-light etching process, utilize a photoresist to limit the pattern that limits theprotective layer 64 andsecond metal level 58 with an etching process attransistor 50 and connection gasket 60 surperficial uniform deposition one protective layers 64.In this step; remove outside (a) transistor area C outer (b) and the connection gasket district D and theprotective layer 64 andsecond metal level 58 in theopening 54;transparency conducting layer 56 is exposed in theopening 54; and thetransparency conducting layer 56 that transistor area C is outer and connection gasket district D is outer also comes out, and theprotective layer 64 of opening 54 both sides andmetal level 58 width of being separated by is about 35mm.

Usually,protective layer 64 is made of silicide, can be silicon nitride or silica.At this moment, after the 4th yellow-light etching process, can carry out a high-temperature oxydation manufacture craft (thermal oxidationprocess).Shown in Fig. 11, carry out an oxidation reaction on the surface ofsecond metal level 58, make second metal level, 58 sidewall surfaces form anoxide layer 65, be used for protectingsecond metal level 58, make unlikely contact the in metal surface and influence its electrical performance with liquid crystal.

Protective layer 64 also can be made up of organic material, and with identical manufacture craft formation structure as shown in figure 10.Then; as shown in figure 12; carry out a heat treatment in whole transparency carrier at last, heating makesprotective layer 64 soft heats (reflow) and covers second metal level, 58 sidewalls, therefore also can avoid the follow-up liquid crystal that is filled on thetransparency carrier 40 to contact with second metal level 58.Use organic material to be as another benefit of protective layer, this organic material is that the mode with spin coating (spin-coat) is formed on the glass substrate, so the surface of this organic protection layer can be more smooth than non-organic protection layer.

Because the deposit thickness ofprotective layer 64 only is about 2mm, and the width of opening 54 reaches 35mm, even withprotective layer 64 heating and melting, also isunlikely opening 54 is filled up, does not therefore have the problem that increasespad electrode 44 resistance values and produce.

Compare with the manufacture method of existing Thin Film Transistor-LCD, the inventive method can provide one to simplify manufacture craft, the access times of yellow-light etching process is reduced to four times by five times, to reduce production costs.Simultaneously, the present invention utilizes heat treatment or oxidation reaction protection to live metal level, avoids it to pollute liquid crystal, therefore can promote the image quality of display, is very helpful to improving competitiveness of product.

The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.

Claims (9)

1. the manufacture method of a film transistor plane indicator, this display is produced on the substrate (substrate), this substrate includes at least one transistor (transistor) district and at least one connection gasket (pad) district, be used for forming a transistor and a connection gasket respectively, this manufacture method includes the following step:

(1) on this substrate surface, forms a first metal layer;

(2) (photo-etching-process PEP) limits the pattern (pattern) of this first metal layer, to form a gate electrode and a pad electrode respectively in this transistor area and this connection gasket district to carry out one first yellow-light etching process;

(3) on this substrate, form an insulating barrier, semi-conductor layer and a doped silicon (dopedsilicon) conductive layer in regular turn;

(4) carry out the pattern that one second yellow-light etching process limits this doped silicon conductive layer, this semiconductor layer and this insulating barrier, in this connection gasket district, limit an open area, remove outside (a) this transistor area simultaneously and (b) this connection gasket district outer with this open area in this insulating barrier, this semiconductor layer, and this doped silicon conductive layer, come out with this connection gasket district exposure of substrates in addition beyond so making this transistor area, and form an opening in this connection gasket district, make this pad electrodes exposed in this opening;

(5) on this substrate, form a transparency conducting layer and one second metal level in regular turn, and this transparency conducting layer and this second metal level are inserted in this opening;

(6) carry out the pattern that one the 3rd yellow-light etching process limits this second metal level, in this transistor area, limit a channel region earlier, remove this second metal level in this channel region, be shade with this second metal level afterwards, remove this transparency conducting layer and this doped silicon conductive layer of this channel region, this semiconductor layer is exposed in this passage;

(7) on this substrate, form a protective layer (passivation layer), and make it cover this passage fully; And

(8) carry out one the 4th yellow-light etching process; limit the pattern of this protective layer and this second metal level; remove (a) this transistor area outer with (b) this connection gasket district outside reach this protective layer and this second metal level in this opening, so make this transparency conducting layer be exposed in this opening, this transistor area is outer, and this connection gasket district outside the zone.

2. the method for claim 1; the sidewall of this second metal level is exposed in this transistor area and this connection gasket district; and this method also comprises a heat treatment step afterwards in this step (8), makes this protective layer soft heat (reflow) also cover the sidewall of second metal level in this transistor area and this connection gasket district fully.

3. method as claimed in claim 2, wherein this protective layer is formed by an organic material.

4. the method for claim 1, wherein after finishing the 4th yellow-light etching process, this method also comprises an oxidation reaction, so that this second metal level sidewall forms an oxide layer, is used for protecting this second metal level.

5. method as claimed in claim 4, wherein this protective layer is formed by an inorganic material.

6. the method for claim 1, wherein this second yellow-light etching process trims the edge of this doped silicon conductive layer, this semiconductor layer and this insulating barrier approximately so that the transparency conducting layer of subsequent deposition some can directly be deposited on this glass substrate.

7. the method for claim 1, when wherein this step (6) limits the pattern of this transparency conducting layer and this doped silicon conductive layer, in this transistor area, form an one source pole electrode and a drain electrode, and this source electrode and this drain electrode by this channel region the interval.

8. the method for claim 1, wherein this substrate also comprises a capacitive region, to be used to form an electric capacity.

9. the method for claim 1, wherein this semiconductor layer is an amorphous silicon layer or polysilicon layer.

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