CN1318172A - Method and system for updating user memory in emulator systems - Google Patents

Abstract

A device, system and method for providing access to user memory in emulator systems. The emulator system contains an emulator system memory, a user system memory and an emulator device. The emulator device operates in a mode where program execution instructions originate in the emulation memory while read and write instructions target the user memory. Logic included in emulator chip directs the read and write memory accesses to the user memory while instructions are fetched from the emulator memory.

Description

Upgrade the method and system of user memory in the emulator systems

Background technology

Technical field

The present invention relates to emulator systems and simulator, more particularly, relate to can be easily the more emulator systems and the simulator of (on-chip) and outer (off-chip) storer of sheet on the new film.

Context analyzer

Many microcontroller device configurations comprise the accumulator system of on-chip memory and the outer user's storer of sheet.In emulator systems, existence can be upgraded the needs of the content of these two types of storeies.In general, emulator systems can easily upgrade on-chip memory, but it is very complicated to upgrade chip external memory.Such as, a kind of classic method that realizes the access user memory for a copy by the emulator controll block direct access that duplicates is provided.Use the main system of emulator systems directly to control the user memory that uses emulator controll block.In another method, can in the emulator controll block that exists, dispose other web member and additional busses.No matter use the emulator controll block of duplicating still to have to increase in addition web member and another bus, all increased the cost and the complicacy of system.

In the another one legacy system, the PIC17C01 simulator of producing by the application's bailee can the access sheet on (emulator program) and sheet (user) storer outward.But simulator must be by the I/O bit is set generates store access cycle with the access chip external memory by hand.More particularly, when needs when user memory reads, main system is from the emulator program storer section of downloading and begin to carry out among PIC17C01 this program segment.Program segment is write inbound port C, D and E data latches, and write C, D and E data direction register (DDR) with as the output configuration they.Main system is changed into the MC pattern from the MP pattern, and port C, D and E are changed into the I/O port mode from the system bus pattern.DDR is provided with in advance and drives as output.Main system begins to pass program segment under the emulator program storer of carrying out this program segment in PIC17C01, and begins to carry out this program segment in PIC17C01.

Program segment is write inbound port C, D and E with the analogue system bus and read the Memory Storage Unit of expectation then.Address ram is write inbound port C and D, and port E is set to the high gating of ALE.The port C of DDR and D are written into and dispose as input, and DDR port E is set to the low gating of OE.Data read on port C and D, and with data storage in the RAM of PIC17C01.Main system is changed into the MC pattern from the MP pattern then, passes program segment down and begin to carry out this program segment in PIC17C01 to the emulator program storer.This program segment is sent to main system with the data among the RAM.

Ablation process is similar, wherein when carrying out, the program segment that passes to the program storage of emulator is down write inbound port C and D and port E with address ram and is set to the high gating of ALE, and the data that will write user program memory write DDR port C and D and DDR port E and are set to the low gating of WR.

Invention is summed up

An object of the present invention is to provide a kind of emulator systems, apparatus and method, realize simply also the outer user's storer of access sheet effectively.

Another object of the present invention provides a kind of emulator systems and device, and wherein code is carried out in the storer of emulator, and the read and write access is direct user's storer outside sheet.

Further aim of the present invention provides a kind of simulator that links to each other with custom system with emulator systems, realizes the program storage in simple and the access custom system effectively.

These and other purposes of the present invention can reach by a kind of simulator, and this simulator has the memory interface that is used for the access program storer, and program storage has at device outside first memory and second memory; And the selection circuit that links to each other with interface, be used for when device is configured to from the first memory instruction fetch, only program storage being write with the memory read access and point to second memory.

Whether this device may further include and the circuit of selecting circuit to link to each other, be used for detecting at least just reading and show to write one of access in execution list, and select circuit only table to be read and table is write access and pointed to second memory.This device also can comprise mode selection circuit, and the switchgear of wherein selecting circuit to comprise to link to each other with first and second storeies also receives signal by mode selection circuit output.

This device also can comprise instruction decoder, and this demoder is used for exporting one and at least just shows one signal writing access instruction at the access of decoding program memory read and program storage.A circuit can link to each other with such demoder, and it is configured to received signal and executive memory read access instruction and program storage are write in the access instruction one at least.

When this device comprised mode selection circuit, this circuit also can comprise the logical circuit that is connected to the output of receiving mode selection circuit; And have the instruction decoder that an output links to each other with logical circuit, wherein interface circuit links to each other with the output of logical circuit.

Mode selection circuit can comprise the device that is used to export the signal that shows this device mode of operation, and instruction decoder can comprise being used for exporting and shows the device that at least just reads or writes one signal of access at the decoding program storer.Logical circuit is connected to and is used for receiving the signal of these two device outputs and exports that signal that allows access that shows first and second storeies to selecting circuit.

Memory interface can comprise program storage bus and the program storage bus controller that links to each other with bus.Select circuit can comprise the multiplexer that links to each other with program storage bus, first memory ACCESS bus and second memory ACCESS bus, and link to each other with multiplexer and to be used for the circuit between the first and second storage access buses, selected.This circuit can comprise being used to produce and outputs to multiplexer and show when this device and be configured to when first memory extracts instruction the only device of the signal of access second memory.This device can comprise mode selection circuit, produce the circuit just show at the signal of executive memory access, be connected to and be used for first logical circuit that receiving mode is selected the output of circuit and had an input end that connects into the signal that is used to receive this circuit output.

First memory can be the emulator program storer, and second memory can be user program memory.

Emulator systems and custom system also can be connected to this device.Emulator systems can comprise first memory, and custom system can comprise second memory.First memory can comprise the emulator program storer, and second memory can comprise user program memory.

Above-mentioned purpose and other purposes also can realize by a kind of simulator, this simulator has the device that is used to receive the instruction that comes from the emulation memory that links to each other with this device, and links to each other as the device that is configured to only memory read and write command target are appointed as the user memory that links to each other with this device when this device when emulation memory extracts instruction with the device that is used to receive.This device also can comprise with the device that is used to receive and linking to each other as the device of detection of stored device read and write instruction, and link to each other with the device that is used to detect with the device of this device mode of operation that elects with the device that is used to receive.

The device that is used for the target appointment can comprise the device that is used to detect this device mode of operation, the device that is used for the device of detection of stored device read and write instruction and is used to be chosen in the output access of two detection means of use between emulation memory and the user memory.This device also can comprise and is used for the device that access is switched between emulation memory and user memory under selector control.

Above-mentioned purpose and other purposes also can realize that the method comprising the steps of: only obtain instruction from first memory by a kind of method of operational simulation device; And only that the storage access sensing is discrete with first memory and the second memory outside storage arrangement.Instruction can only be obtained from emulator memory, and can only storage access be pointed to and the discrete user program memory of emulator memory.This method also can comprise and will read and show to write a sensing program storage in the access at table at least.

This method also can comprise the mode of operation that detects this device; Whether the access of detection of stored device is carried out; And be chosen in the access of one of first and second storeies based on detecting step.The access of detection of stored device whether carrying out can comprise detection whether at least one table read and table is write access and carried out; And guide storage access to comprise at least one table read and table is write access and pointed to second memory.

This method also can comprise decoding instruction, and whether detection is using the access of decoding step execute store, and determines using in detection step accesses first and second storeies that.Also can detect the mode of operation of this device, and determine using in detection step execution access first and second storeies that.

Brief description of the drawings

By with reference to detailed description with the accompanying drawing hereinafter, feature that the present invention is more detailed and affiliated advantage thereof can easily obtain, become better understood simultaneously, wherein:

Fig. 1 is the simplified block diagram according to emulator systems of the present invention;

Fig. 2 is the block scheme according to emulator chip of the present invention;

Fig. 3 is according to the circuit diagram that is included in the emulator chip of the present invention;

Fig. 4 A to Fig. 4 C is the emulation memory mapping graph that is operated under the different mode;

Fig. 5 is according to read command tabulation figure of the present invention; With

Fig. 6 is according to write order tabulation figure of the present invention.

The elaboration of preferred embodiment

Referring now to accompanying drawing, be Fig. 1 more particularly, represented embodiment according to system of the present invention.System comprisesemulator systems 10,emulator chip 20 and custom system 30.Emulator systems 10 comprisesSimulation Control circuit 11,address latch 12 and emulator program storer 13.Main system 40 is communicated by letter withemulator systems 10 by the bus 41 that is connected betweenmain system 40 and the Simulation Control chip 11.Address fromemulator chip 12 is input to addresslatch 12, and data are transmitted betweenstorer 11 andchip 20 by bus 14.Simulation Control circuit 11 also links to each other with bus 14.Address fromlatch 12 is input to emulator program storer 13 bybus 15.

Addresslatch 12 links to each other with EALE with pin EA, EBA0, andSimulation Control 11 links to each other with several pins ofchip 20 simultaneously.Program storage 13 is also write high pin and emulator with emulator output enable pin, the emulator ofchip 20 and is write low pin and link to eachother.Bus 21 is connected betweensystem 10,chip 20 and thesystem 30.

Custom system 30 comprises user program memory 33 and address latch 32.Address fromchip 20 is fed to storer 33 bybus 31 from latch 32.The UAD pin ofchip 20 links to each other with the input of the data of storer 33, and pin UA, pin UBA0 link to each other with address latch 32 with pin UALE.User memory output enable pin, user write high pin and user and write low pin and also link to each other with program storage 33.

The capacity that should note emulator memory 13 and user memory 33 is normally inequality.Chip external memory 33 is generally bigger.

Many pins ofchip 20 also link to each other with slave unit 50.Slave unit provides partial simulation devicefunction.Emulator chip 20 is designed to the major function of the most devices of emulation, the peripheral function of these devices of slave unit emulation, andchip 20 andslave unit 50 be the whole device of operation simulation together.Chip 20 andslave unit 50 are designed to discrete, to allow just can emulation to have by the different slave unit of simple use various types of devices of different peripheral functions.Connect 51 to 53 and show being connected ofchip 20 andslave unit 50 and " target " system.The place of emulator alternate user system chips that in other words, Here it is.

In the present invention,chip 20 is placed the mode of operation of expectation.In a kind of pattern, term is a microprocessor tracing pattern (MP/W), and below will go through.Program inchip 20 is carried out and is taken place from emulator program storer 13, occurs in user program memory 33 but show to read and show write command.Main system 40 uses the Simulation Control circuit to pass program segment for 11 times to emulator program storer 13.The execution of the program segment ofmain system 40 beginnings in chip 20.When memory read 33, the program segment execution list reads instruction with memory read 33.The program segment of carrying out inchip 20 transmits data fromchip 20 tomain system 40 bycircuit 11 and bus 41.

When similar operation takes place when program storage 33 is write.Chip 20 is placed the MP/W pattern, working procedure is pointed to from emulator program storer 13 take place, and write command is read and shown to table in user program memory 33 generations.Main system 40 usesSimulation Control circuit 11 to pass to emulator program storer 13 under the program segment.The execution of the program segment ofmain system 40 beginnings in chip 20.Program segment execution list write command is with to storer 33 write datas.The data transmission that is stored within thechip 20 arrives storer 33.

More detailed Fig. 2 that is illustrated in of chip 20.Program storage interface 60 joins bypin 61 and emulator program storer 13 and user program memory 33.For instance, input EA and EAD and emulator program storer 13 join, and input UA and UAD and user program memory 33 join.The instruction that is input to device is loaded intoorder register 63 by program bus 62.Order register 63 and instructions decodings andcontrol 67 and address multiplexer 76 be connected to each other.Fig. 2 also shows theSimulation Control circuit 66 of reception from a plurality of inputs of the Simulation Control in theemulator systems 10 11.It should be noted that the pattern input of 3 bits discussed in more detail below.

What link to each other withinterface 60 is that table is read and table is write execution logic circuit 83.Circuit 83 links to each other withinterface 60 bybus.Circuit 83 also and instruction decoding 67 link to each other, but in this figure not with its diagram; And the execution of finishing the program storage read and write instruction that is called as table read and writeinstruction.Circuit 83 also comprises and is used in execution list and reads and show register TBLPTR and TABLAT in the write command.Describe the work of this circuit in detail below in conjunction with Fig. 3 and Fig. 5 and Fig. 6.

Chip 20 also comprises theclock generator 68 that is used for producing the various clock signals that are used inentire chip 20, and comprises thecircuit 69 that resembles electric timer, oscillator starting timer, power-on reset and watchdog timer unit.ALU71 with work register (WReg) 70 links to each other with various circuit bybus 82, such as timer 77,peripheral circuit 78 and data monitor 79.This chip comprises several registers, and some of them do not illustrate for simplicity.What illustrate is group selection register (BSR) 73,status register 74 and file mask register (FSR) 75.Provide adata memory interface 80, to handle by the data transmission ofpin 81 with data-carrier store (emulated data RAM).Data-carrier store is usually located in the slave unit 50.Be received fromorder register 63 and be input to data-carrier store interface 67 byaddress ram bus 81 by the address that address multiplexer 76 is presented.It should be understood that Fig. 2 is not the complete graph ofchip 20, many other circuit and interconnectors are not shown, Fig. 2 is included is used to illustrate the present invention, and does not mean that all features thatchip 20 is shown.

The read and write program storage is usually by being called the instruction realization that table is read and shown to write in microprocessor.These instructions allow transmission information between data memory space and program memory space.In the present invention, the logic in theemulator chip 20 is read table and show write order and reassigns and be to allow the access user memory.Therefore, user memory 33 access easily.This will become obvious in the following description.

The more detailed review that is included in some circuit in thechip 20 is shown in Fig. 3.Mode decodinglogical circuit 90 receives 3 bit mode signals fromSimulation Control circuit 66 as input.This 3 bit signal of mode decoding logical decode and according to the expectation mode of operation output logic " 1 " signal on suitable output line.In such cases, for example understand microcontroller pattern, microprocessor model and microprocessor tracing pattern.The memory mapped separately of these patterns is shown in Fig. 4 A to Fig. 4 C, and goes through below.It should be understood that these three kinds of patterns only as illustrating the present invention, and other mode of operation is feasible.

Fig. 4 A to Fig. 4 C has represented the emulation memory mapping under different working modes.Fig. 4 A illustrates microcontroller protection/microcontroller pattern, can only the access emulation memory.In microprocessor model (Fig. 4 B), can only the access user memory.In addition, Fig. 4 C illustrates the pattern that is called microprocessor tracing pattern, and wherein all program execution commands all are derived from emulation memory, and read and write table handling command source oneself or target are user memory.

Mapping graph shown in Fig. 4 A to Fig. 4 C is to be used for illustrating understanding of the present inventionly, and does not mean that user and emulator storer have identical capacity or be necessary for onesize.Usually the user memory outside the sheet is more many greatly than emulator program storer.

The circuit of Fig. 3 also comprises themultiplexer 100 that links to each other withcustom system bus 21 with emulator systems bus 14.Multiplexer 100 is controlled with the output of multiplexer being pointed to thelogical circuit 95 that allows ESB access or USB access by output signal on signal wire 101.Circuit 95 comprises ANDgate 91 and 93,phase inverter 94 and OR-gate 92.What be connected tomultiplexer 100 by the program storage bus is programstorage bus controller 99, is used for the read and write of control program storer.The instruction that is received from program storage is input toinstruction demoding circuit 67.

Write commandexecution logic circuit 83 is read/shown to table is that the signal wire of TBLRD and TBLWT is connected todecoding circuit 67 bylabel.Circuit 83 comprises two and is used in register TBLPTR97 and the TABLAT98 that write command was read and shown to execution list, and its use below will be described indetail.Circuit 83 is connected to programstorage bus controller 99 by program storage read/write bus.TBLRD and TBLWT signal wire are fed to OR-gate 96, and the output of OR-gate 96 is fed to the input of AND gate 91.The every other output that is fed to the appropriate circuitry of simulator with the decoding instruction of execution ofsignal wire 102 representatives.An example is the ALU that is used to carry out arithmetical operation.

To set forth the work of the circuit of Fig. 3 now.May take place three types memory cycle in the circuit of Fig. 3.They are that instruction is obtained, read and write from the TBLWT instruction list from the TBLRD instruction list.Instruction sends to instruction decoder 62.Instruction is decoded as table reads, show to write and other instructions, in Fig. 3, be schematically represented as one group of output 102.When detecting TBLRD or TBLWT, signal to instruction execution logic circuit 83.Logical circuit 83 is givencontroller 99 with the router storage access.According to the signal in the input of pattern pin, if the multiplexer control signal is a logical zero, multiplexer points to access ESB with the program storage access; If the multiplexer control signal is a logical one, then access USB is pointed in the program storage access.

The storer of access is wanted in the model selection decision.In the microcontroller pattern, always expect storage access is pointed to ESB.Therefore, the MC mode signal is sent to AND gate 86 after anti-phase, thereby the multiplexer control signal always is a logical zero.In microprocessor model, always expect storage access is pointed to USB.Therefore, the microprocessor model signal is sent to OR-gate 88, thereby the multiplexer control signal always is a logical one.

ANDgate 91 receives the microprocessor tracing signal and the signal that produces from OR-gate 96 as input.When read or write instruction byinstruction decoder 67 decoding after read or show to write on the line because the logical one signal outputs to table, so produce the logical one signal of OR-gate 96.The output of this OR-gate 96 is fed on theAND gate 91 of microprocessor tracing output as input of going back receiving mode decode logic 90.When two signals that are input to ANDgate 91 when all being high, the logical one signal causes the logical one signal from OR-gate 92 outputs fromAND gate 91 outputs.Then, because the signal on microcontroller line and the line microprocessor is defined as logical zero in microprocessor tracing pattern, so AND gate is with output logic " 1 " signal.In microprocessor tracing pattern, the target of read and write instruction is USE, and the target of the every other storage access relevant with other any instructions is ESB.Therefore, chip moves by obtain instruction fromESB system 10, and any table is read or shown write command and carries out in USB system 30.Under this pattern, allow to execute instruction from the emulator program storer simply according to simulator of the present invention, and read and write from user program memory.

More detailed table read and write operation is shown in Fig. 5 and Fig. 6.In table read command shown in Figure 5, two registers in thechip 20 have been described.The TABLAT register is for the table latch and occupy 8 bits.This register keeps the content by the address of the list index register TBLPTR that is loaded into 21 bits Memory Storage Unit pointed.Instruction can have four kinds of selections for TBLRD.Under three kinds of situations, be loaded into TABLAT by the data in the Memory Storage Unit of TABLPTR user memory 33 pointed.As the operand defined, the value among the TBLPTR is for keeping constant or increasing or decreasing after value is loaded into TABLAT.Under the situation, the value of TBLPTR increases progressively in the 4th, and will be loaded into TABLAT by the storage unit in the storer 33 pointed of the increment value among the TBLPTR.

The execution of table write command is similar.As shown in Figure 6, instruction also has four kinds of feasible selection for TBLWT.Under three kinds of situations, be loaded into TABLAT by the data in the Memory Storage Unit of TABLPTR user memory 33 pointed.As the operand defined, the value among the TBLPTR is for keeping constant or increasing or decreasing.Under the situation, the value of TBLPTR increases progressively in the 4th, and the data among the TABLAT will be loaded into by the Memory Storage Unit in the user memory 33 pointed of the increment value among the TBLPTR.

Clearly, can carry out multiple modification and change to the present invention according to above-mentioned example.Therefore should be appreciated that within the scope of the appended claims, all can implement the present invention in addition, and just do not resemble the special description of institute here.

Claims (26)

1. simulator comprises:

The memory interface that is used for the access program storer, described program storage are included in the first memory and the second memory of device outside; With

The selection circuit that links to each other with described interface is used for only program storage being write with memory read access and points to described second memory when described device is configured to from described first memory instruction fetch.

2. device as claimed in claim 1 comprises:

With the circuit that described selection circuit links to each other, at least just whether be used for detecting in execution list and read and show to write of access;

Wherein said selection circuit can only be read described table and table is write access and pointed to described second memory.

3. device as claimed in claim 1 comprises:

Mode selection circuit;

Wherein said selection circuit comprises the switchgear that links to each other with described first and second storeies and connects into the signal of reception by described mode selection circuit output.

4. device as claimed in claim 1 comprises:

Instruction decoder is used for exporting one and at least just shows one signal writing access instruction at the access of decoding program memory read and program storage;

With the circuit that described demoder links to each other, be configured to receive described signal and be configured to carry out at least the instruction of described program storage read access and described program storage is write in the access instruction one.

5. device as claimed in claim 1 comprises:

Mode selection circuit;

Be connected to the logical circuit of the output that receives described mode selection circuit;

Instruction decoder with the output that links to each other with described logical circuit;

Described interface circuit links to each other with the output of logical circuit.

6. device as claimed in claim 5, wherein:

Described mode selection circuit comprises first device that is used to export the signal that shows described device mode of operation;

Described instruction decoder comprises being used for exporting and shows second device that at least just reads or writes one signal of access at the decoding program storer; With

Described logical circuit be connected to be used for receiving by the described signal of described first and second devices output and export one show described first memory and described second memory that be to allow the signal of access to described selection circuit.

7. device as claimed in claim 1, wherein:

Described memory interface comprises:

The program storage bus and

The program storage bus controller that links to each other with described bus; And described selection circuit comprises:

The multiplexer that links to each other with described program storage bus, first memory ACCESS bus and second memory ACCESS bus and

Link to each other with described multiplexer and to be used for the circuit between the described first and second storage access buses, selected.

8. device as claimed in claim 7, wherein said circuit comprise being used to produce and output to described multiplexer and show when described device and be configured to when described first memory extracts instruction the only device of the signal of the described second memory of access.

9. device as claimed in claim 8, wherein said device comprises:

Mode selection circuit;

Generation just shows the circuit at the signal of executive memory access; With

Link to each other with the output of described mode selection circuit and have first logical circuit of the input end that connects into the described signal that is used to receive described circuit output.

10. device as claimed in claim 1, wherein:

Described first memory be the emulator program storer and

Described second memory is a user program memory.

11. device as claimed in claim 1 further comprises:

The emulator systems that links to each other with described device; With

The custom system that links to each other with described device.

12. device as claimed in claim 11, wherein:

Described emulator systems comprises described first memory; With

Described custom system comprises described second memory.

13. device as claimed in claim 12, wherein:

Described first memory comprises the emulator program storer that contains the instruction of being extracted by described device;

Described second memory comprises when described device and is configured to only described program storage be write and memory read access user program memory pointed when described first memory extracts instruction.

14. a simulator comprises:

Be used to receive the device of the instruction that comes from the emulation memory that links to each other with described device; With

Link to each other with the described device that is used to receive, extract when instructing from described emulation memory, only memory read and write command target are appointed as the device of the user memory that links to each other with described device as being configured to when described device.

15. device as claimed in claim 14 comprises:

Link to each other as the device that detects described memory read and write command with the described device that is used to receive; With

Link to each other with the described device that is used to detect with the device of the described device mode of operation that elects with the described device that is used to specify target.

16. device as claimed in claim 14, the described device that wherein is used to specify target comprises:

Be used to detect the device of described device mode of operation;

Be used to detect the device of described memory read and write command; With

Be used to use the output of two described detection means between described emulation memory and described user memory, to select the device of access.

17. device as claimed in claim 16 comprises:

Be used for the device that access is switched between described emulation memory and described user memory under described selector control.

18. the method for an operational simulation device comprises:

Only obtain instruction from first memory; With

Only storage access is pointed to second memory discrete with described first memory and outside described storage arrangement.

19. method as claimed in claim 18 comprises:

Only obtain instruction from emulator memory; With

Only described storage access is pointed to user program memory discrete with described emulator memory and outside described simulator.

20. method as claimed in claim 19 comprises:

Point to described program storage with reading and show to write in the access one at table at least.

21. method as claimed in claim 18 comprises:

Detect the mode of operation of described device;

Whether the access of detection of stored device is carried out; With

Be chosen in the access of one of described first and second storeies based on described detection step.

22. method as claimed in claim 21, wherein:

The access of detection of stored device whether carrying out comprise detection whether at least one table read and table is write access and carried out; With

Guide described storage access to comprise at least one described table read and table is write access and pointed to described second memory.

23. method as claimed in claim 22 comprises:

Only obtain instruction from emulator memory; With

Only described storage access is pointed to user program memory discrete with described emulator memory and outside described simulator.

24. method as claimed in claim 18 comprises:

The described instruction of decoding;

Detect and whether using the access of described decoding step execute store; With

Determine to use in described first and second storeies of described detection step accesses that.

25. method as claimed in claim 24 comprises:

Detect the mode of operation of described device; With

Determine to use described detection step to carry out in described first and second storeies of access that.

26. method as claimed in claim 25 comprises:

Only described storage access is pointed to user program memory discrete with described emulator memory and outside described simulator.

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