CN1307427C - Beam synthesizer and synthetic method based on linear interpolation - Google Patents

Abstract

Translated fromChinese

本发明公开一种基于线性插值的波束合成器及其合成方法，旨在提供一种低成本无暂态输出的内插式波束合成方法及其装置。本发明采取了两项措施：其一是延时存储器采用了FIFO结构，接收延时在起始延时的基础上以细延时精度为单位动态地调整；其二是把变迹加权系数分别融入到线性插值的两个系数a，b中，把插值与变迹一并完成。该方法在利用处理器对数字化后的回波信号进行合成处理的过程中，每当循环至暂态D0时，FIFO延时储存器停读一拍，线性插值器的锁存器也停工一拍。本发明方法适用于医用超声波诊断系统接收进程的数字波束合成。

The invention discloses a beam synthesizer based on linear interpolation and a synthesis method thereof, aiming to provide a low-cost interpolation beam synthesis method and a device thereof without transient output. The present invention has taken two measures: one is that the delay memory adopts a FIFO structure, and the receiving delay is dynamically adjusted in units of fine delay precision on the basis of the initial delay; the other is that the apodization weighting coefficients are respectively It is integrated into the two coefficients a and b of linear interpolation, and the interpolation and apodization are completed together. In this method, in the process of synthesizing and processing the digitized echo signal by the processor, whenever the cycle reaches the transient state D0, the FIFO delay storage stops reading for one beat, and the latch of the linear interpolator also stops working for one beat. . The method of the invention is suitable for the digital beam forming in the receiving process of the medical ultrasonic diagnosis system.

Description

Translated fromChinese

基于线性插值的波束合成器及其合成方法Beam combiner and its combining method based on linear interpolation

                       技术领域                      

涉及本发明涉及医用超声波诊断系统中数字波束合成的方法和装置，尤其涉及接收进程中的波束合成。波束合成是医用超声波诊断系统中最关键的技术，合成波束的质量对超声成象的精确性和分辨率有很大影响。The present invention relates to a method and a device for digital beam forming in a medical ultrasonic diagnostic system, in particular to beam forming in a receiving process. Beam synthesis is the most critical technology in medical ultrasonic diagnostic systems, and the quality of the synthesized beam has a great influence on the accuracy and resolution of ultrasonic imaging.

                       背景技术 Background technique

波束合成器有模拟与数字之分，数字波束合成器在精确性、稳定性和灵活性方面优于传统的模拟波束合成器，随着数字器件性能的提高和成本的减少，数字波束合成正逐渐取代模拟波束合成，本发明涉及的是数字波束合成器。The beamformer can be divided into analog and digital. The digital beamformer is superior to the traditional analog beamformer in terms of accuracy, stability and flexibility. With the improvement of the performance of digital devices and the reduction of cost, digital beamformer is gradually Instead of analog beamformers, the present invention relates to digital beamformers.

数字波束合成的关键技术是数字延时，数字延时一般是通过双口RAM实现的。各通道回波信号在A/D变换之后，按同样的地址写入各通道的双口RAM，而在读双口RAM的时候，各通道使用不同的读地址获得波束合成所需的延时。延时精度取决于A/D采样率，这个采样率要比Nyquist采样率大几倍，一般要求高于100MHz。The key technology of digital beamforming is digital delay, and digital delay is generally realized through dual-port RAM. After A/D conversion, the echo signals of each channel are written into the dual-port RAM of each channel at the same address, and when reading the dual-port RAM, each channel uses a different read address to obtain the delay required for beamforming. The delay accuracy depends on the A/D sampling rate, which is several times higher than the Nyquist sampling rate, generally higher than 100MHz.

在Proceeding of the IEEE Vol.67，No.6，pp.904-919，June 1979公开的文章中，Pridham和Mucci提出了通过内插降低A/D变换高速取样的要求。A/D采样率只需满足Nyquist要求，延时存储器在波束合成进程中提供一个粗的延时，而波束合成所需的精确延时则用插值的方法实现。在此之后，内插式波束合成的研究集中在如何降低成本方面。美国专利5345426提出了用整系数FIR滤波器实现内插的低成本方案；美国专利5544128提出了把插值滤波器放在波束形成之后的低成本方案。这些内插式波束合成方案，在动态聚焦和动态变迹应用中，无法避免插值滤波器的暂态输出，从而使波束合成的质量受到影响。In the article published in Proceeding of the IEEE Vol.67, No.6, pp.904-919, June 1979, Pridham and Mucci proposed the requirement of reducing the high-speed sampling of A/D conversion through interpolation. The A/D sampling rate only needs to meet the Nyquist requirement, and the delay memory provides a coarse delay during the beamforming process, while the precise delay required by the beamforming is realized by interpolation. After that, the research of interpolation beamforming focused on how to reduce the cost. US Patent No. 5,345,426 proposes a low-cost solution for implementing interpolation using an integer-coefficient FIR filter; US Patent No. 5,544,128 proposes a low-cost solution for placing an interpolation filter after beamforming. These interpolation beamforming schemes cannot avoid the transient output of the interpolation filter in dynamic focusing and dynamic apodization applications, thus affecting the quality of beamforming.

                         发明内容Contents of invention

本发明的目的在于克服现有技术存在的不足而提供一种低成本无暂态输出的内插式波束合成方法及其装置。The purpose of the present invention is to overcome the shortcomings of the prior art and provide a low-cost non-transient output interpolation beamforming method and device thereof.

为达到上述目的，本发明通过适当地提高A/D采样率，例如提高到两倍以上的Nyquist采样率，把插值滤波器简化到它的最简形式——线性插值器。把线性插值器放在每一个接收通道的延时存储器之后，为实现低成本无暂态输出的内插式波束合成器提供了可能。为消除插值器的暂态输出，本发明采取了两项措施：其一是延时存储器采用了FIFO结构，接收延时在起始延时的基础上以细延时精度为单位动态地调整；其二是把变迹加权系数分别融入到线性插值的两个系数a，b中，把插值与变迹一并完成。具体的波束合成方法如下：To achieve the above purpose, the present invention simplifies the interpolation filter to its simplest form—linear interpolator by appropriately increasing the A/D sampling rate, for example, increasing the Nyquist sampling rate to more than twice. Placing a linear interpolator after the delay memory of each receive channel provides the possibility to implement a low-cost interpolating beamformer with transient-free output. For eliminating the transient output of the interpolator, the present invention has taken two measures: one is that the delay memory adopts a FIFO structure, and the receiving delay is dynamically adjusted in units of fine delay precision on the basis of the initial delay; The second is to integrate the apodization weighting coefficient into the two coefficients a and b of linear interpolation respectively, and complete the interpolation and apodization together. The specific beamforming method is as follows:

i.来自目标的回波由探头的各阵元接收，每个探头阵元连接各自的信号接收处理通道；i. The echo from the target is received by each array element of the probe, and each probe array element is connected to its own signal receiving and processing channel;

ii.在每个信号接收处理通道中，来自探头阵元的信号被放大，然后以统一的速率数字化；ii. In each signal reception processing channel, the signal from the probe array element is amplified and then digitized at a uniform rate;

iii.数字化后的回波信号被送入各信号接收处理通道处理器进行处理；iii. The digitized echo signal is sent to each signal receiving and processing channel processor for processing;

在利用处理器对数字化后的回波信号进行合成处理的过程中，In the process of synthesizing and processing the digitized echo signals by the processor,

iv.由具有FIFO结构的延时存储器和线性插值器分别提供信号接收处理通道的粗延时和细延时，粗延时精度等于射频采样间隔T，细延时精度等于T除以插值相数M；iv. The coarse delay and fine delay of the signal receiving and processing channel are respectively provided by the delay memory with FIFO structure and the linear interpolator. The coarse delay accuracy is equal to the radio frequency sampling interval T, and the fine delay accuracy is equal to T divided by the number of interpolation phases M;

v.当所有信号接收处理通道的延时储存器都有数据样本写入时，动态聚焦打开各信号接收处理通道延时存储器的读使能，并输出五种状态的细延时代码S1S2S3S4，它们是：一个暂态D0＝0000，四个稳态D1＝1000、D2＝0100、D3＝0010和D4＝0001；细延时代码S1S2S3S4的每一种状态各对应一组线性插值系数a和b；v. When there are data samples written in the delay memory of all signal receiving and processing channels, the dynamic focus opens the read enable of the delay memory of each signal receiving and processing channel, and outputs five states of fine delay codes S1S2S3S4, which Be: one transient state D0=0000, four steady states D1=1000, D2=0100, D3=0010 and D4=0001; each state of the fine delay code S1S2S3S4 corresponds to a group of linear interpolation coefficients a and b;

vi.在接收聚焦延时的动态调整过程中，细延时代码S1S2S3S4按D4→D3→D2→D1→D0→D4的循环规律变化，以便对起始延时进行动态调整，达到动态聚焦的目的；vi. During the dynamic adjustment of the receiving focus delay, the fine delay code S1S2S3S4 changes according to the cycle of D4→D3→D2→D1→D0→D4, so as to dynamically adjust the initial delay and achieve the purpose of dynamic focus ;

vii.每当循环至暂态D0时，FIFO延时储存器停读一拍，线性插值器的锁存器也停工一拍；vii. Whenever looping to the transient state D0, the FIFO delay storage stops reading for one beat, and the latch of the linear interpolator also stops working for one beat;

viii.把细延时代码映射为两个插值系数，并把两插值系数分别与变迹系数相乘得到变迹插值系数，最后完成插值系数与通道加权系数的合并；viii. Map the fine delay code into two interpolation coefficients, and multiply the two interpolation coefficients by the apodization coefficients to obtain the apodization interpolation coefficients, and finally complete the merging of the interpolation coefficients and the channel weighting coefficients;

ix.各通道合并的输出信号经检测器检测后，由显示屏显示数据。ix. After the combined output signal of each channel is detected by the detector, the data will be displayed on the display.

根据上述波束合成方法，可设计出基于线性插值的波束合成器，该波束合成器包括：According to the above beamforming method, a beamformer based on linear interpolation can be designed, which includes:

用于向受测机体发射超声波并接收目标回波的各探头阵元；Each probe array element is used to transmit ultrasonic waves to the body under test and receive target echoes;

用于放大各探头阵元所输出回波的各通道放大器；Amplifiers for each channel used to amplify the echoes output by each probe array element;

用于把各通道放大器的模拟信号输出转换成数字信号的各通道A/D变换器；Each channel A/D converter for converting the analog signal output of each channel amplifier into a digital signal;

用于对各通道A/D变换器所输出数字信号进行聚焦延时、加权与串行求和处理的各通道处理器；Each channel processor is used to perform focus delay, weighting and serial sum processing on the digital signals output by each channel A/D converter;

上述各探头阵元、各通道放大器、各通道A/D变换器和各通道处理器按顺序单向连接构成多个互相独立的信号接收处理通道；还包括：The above probe array elements, channel amplifiers, A/D converters of each channel and processors of each channel are sequentially connected in one direction to form multiple independent signal receiving and processing channels; it also includes:

用于储存各通道聚焦延时数据和变迹数据的数据存储器及其读控制器和扫描控制器，所有信号接收处理通道的输出信号合成后经检测器，最后送显示器显示；其特征在于所述每一个处理器阵元包括：The data memory for storing the focus delay data and apodization data of each channel and its read controller and scan controller, the output signals of all signal receiving and processing channels are synthesized and then sent to the display for display after being synthesized; it is characterized in that Each processor element consists of:

具有FIFO结构的延时储存器，用于提供信号接收处理通道的粗延时；Delay memory with FIFO structure, used to provide rough delay of signal receiving and processing channel;

线性插值器，用于提供信号接收处理通道的细延时；A linear interpolator for providing a fine delay of the signal reception processing channel;

动态聚焦，用于向延时储存器提供读使能控制，并提供细延迟代码；Dynamic focus for providing read enable control to latency storage and providing fine latency code;

起始延时，用于控制延时储存器的写使能，达到控制起始延时的目的；The start delay is used to control the write enable of the delay storage to achieve the purpose of controlling the start delay;

插值变迹系数产生器，用于把细延迟代码映射为插值系数，并计算出变迹插值系数；an interpolation apodization coefficient generator, which is used to map the fine delay codes into interpolation coefficients, and calculate the apodization interpolation coefficients;

线性插值器的信号输入端口分别连接延时储存器、动态聚焦和插值变迹系数产生器，其信号输出端经第一加法器连接检测器。The signal input ports of the linear interpolator are respectively connected to the delay storage, the dynamic focus and the interpolation apodization coefficient generator, and the signal output ports are connected to the detector through the first adder.

与现有技术相比，本发明基于线性插值的波束合成器及其合成方法具有如下优点：在保证波束合成的质量的前提下，实现低成本无暂态输出的内插式波束合成。Compared with the prior art, the linear interpolation-based beamformer and its synthesis method of the present invention have the following advantages: on the premise of ensuring the quality of beamformation, low-cost interpolation beamformer without transient output is realized.

                      附图说明Description of drawings

本发明的数码可视复读机的附图说明如下：The accompanying drawings of the digital video repeater of the present invention are as follows:

图1是一个超声波成象装置的构成方框图；Fig. 1 is a block diagram of the composition of an ultrasonic imaging device;

图2是依据本发明原理构造的各接收通道处理器的原理方框图；Fig. 2 is the principle block diagram of each receiving channel processor constructed according to the principles of the present invention;

图3是起始延时逻辑的原理方框图；Fig. 3 is the principle block diagram of initial delay logic;

图4是动态聚焦逻辑单元的原理方框图；Fig. 4 is a schematic block diagram of a dynamic focus logic unit;

图5是插值变迹系数产生逻辑的原理方框图；Fig. 5 is a principle block diagram of interpolation apodization coefficient generation logic;

图6是数据存储器及其读控制器的原理方框图。Fig. 6 is a schematic block diagram of the data memory and its read controller.

                    具体实施方式 Detailed ways

为了更好地全面理解本发明，下面将结合本发明的一个优选实例和附图进行详细的说明。In order to understand the present invention better and comprehensively, a detailed description will be given below in conjunction with a preferred example of the present invention and accompanying drawings.

图1是一个超声波成象装置的构成方框图，该超声波成象装置使用多阵元探头，因此波束合成器包含多个信号处理通道。来自目标的回波由探头的各阵元接收，每个阵元连接到不同的接收通道。在每个接收通道中，来自探头阵元的信号被放大，然后以统一的速率数字化。为了简化描述，假设探头阵元只有四个，但它也可更大些。四个发射器10至13产生常规的驱动脉冲，激励探头阵元向受测试的机体组织发射超声波，之后，这些阵元又接收从受测试的机体组织中反射回来的超声波。在并行接收信道2至5，各阵元接收到的回波分别由放大器14至17放大，然后分别由A/D变换器20至23以统一的速率进行数字化。数字化后的回波信号进入各通道的处理器，在这里完成聚焦延时、加权与串行求和。处理器27的输出是波束合成信号，该信号由检测器6检测。为了在显示器9上显示数据，必须用数字扫描变换器7将回波数据转换为视频信号。系统所有的控制都由控制器8产生的控制信号来执行。FIG. 1 is a block diagram of an ultrasonic imaging device. The ultrasonic imaging device uses a multi-element probe, so the beamformer includes multiple signal processing channels. Echoes from the target are received by the transducer's array elements, each of which is connected to a different receive channel. In each receive channel, the signal from the probe elements is amplified and then digitized at a uniform rate. To simplify the description, it is assumed that there are only four probe elements, but it could be larger. The fourtransmitters 10 to 13 generate conventional driving pulses to excite the probe elements to transmit ultrasonic waves to the body tissue under test, and then these elements receive the ultrasonic waves reflected from the body tissue under test. Inparallel receiving channels 2 to 5, the echoes received by each array element are respectively amplified byamplifiers 14 to 17, and then digitized by A/D converters 20 to 23 at a uniform rate. The digitized echo signal enters the processor of each channel, where focusing delay, weighting and serial summation are completed. The output of theprocessor 27 is the beamforming signal, which is detected by thedetector 6 . In order to display the data on thedisplay 9, the echo data must be converted into a video signal by means of adigital scan converter 7. All control of the system is performed by control signals generated by thecontroller 8 .

本发明的关键之处在于根据发明目的，对处理器的结构进行改进。图2是依据本发明原理构造的各接收通道处理器的原理方框图；所述处理器阵元包括：The key point of the invention is to improve the structure of the processor according to the purpose of the invention. Fig. 2 is the principle block diagram of each receiving channel processor constructed according to the principles of the present invention; the array element of the processor comprises:

具有FIFO结构的延时储存器30，用于提供信号接收处理通道的粗延时；Adelay storage 30 with a FIFO structure is used to provide a rough delay of the signal receiving and processing channel;

线性插值器39，用于提供信号接收处理通道的细延时；Alinear interpolator 39, configured to provide a fine delay of the signal receiving and processing channel;

动态聚焦32，用于向延时储存器30提供读使能控制，并提供细延迟代码；Dynamic focus 32 for providing read enable control to delaystorage 30 and providing fine delay codes;

起始延时31，用于控制延时储存器30的写使能，达到控制起始延时的目的；Theinitial delay 31 is used to control the write enable of thedelay storage 30 to achieve the purpose of controlling the initial delay;

插值变迹系数产生器33，用于把细延迟代码映射为插值系数，并计算出变迹插值系数；The interpolationapodization coefficient generator 33 is used for mapping the fine delay codes into interpolation coefficients, and calculates the apodization interpolation coefficients;

线性插值器39的信号输入端口分别连接延时储存器30、动态聚焦32和插值变迹系数产生器33，其信号输出端经第一加法器38连接检测器6。The signal input port of thelinear interpolator 39 is respectively connected to thedelay storage 30 , thedynamic focus 32 and the interpolationapodization coefficient generator 33 , and its signal output port is connected to thedetector 6 via thefirst adder 38 .

所述线性插值器39包括顺序连接的第一乘法器35、第二加法器37以及第一锁存器34和第二乘法器36，第一锁存器34的输入端连接动态聚焦32，第一乘法器35和第二乘法器36的输入端连接插值变迹系数产生器33，第二乘法器36的输出端与第二加法器37连接。延时存储器30采用FIFO结构，其深度由所需的最大延时量决定，读写时钟CKO为射频采样时钟。延时存储器30与线性插值器39分别提供接收通道的粗延时与细延时，粗延时精度等于射频采样间隔T，细延时精度等于T/M，M由所需的延时精度决定，T的取值范围一般在40ns～25ns之间。在本例中M等于4。延时存储器的写使能由起始延时31提供，起始延时31根据各接收通道所需的起始粗延时控制延时存储器30的写使能，而各接收通道所需的起始细延时则由动态聚焦32给出。当所有接收通道的延时存储器都有数据样本写入的时候，动态聚焦32打开各通道延时存储器30的读使能，同时也打开第一锁存器34的时钟使能。动态聚焦32输出的细延时代码s1s2s3s4有五种可能状态：D0＝0000，D1＝1000，D2＝0100，D3＝0010，D4＝0001，与线性插值系数a和b的关系是：s1s2s3s4＝1000则a＝1，b＝0；s1s2s3s4＝0100则a＝3/4，b＝1/4；s1s2s3s4＝0010则a＝2/4，b＝2/4；s1s2s3s4＝0001则a＝1/4，b＝3/4；s1s2s3s4＝0000则a＝1/4，b＝3/4。在接收聚焦延时的动态调整过程中，细延时代码的五种可能状态按一种循环规律变化：D4变D3、D3变D2、D2变D1、D1变D0、D0变D4。假设当前细延时代码状态为D2＝0100，当接收聚焦延时需要调整时，D2变为D1，插值系数由a＝3/4、b＝1/4变为a＝1、b＝0，线性插值器的输出延时增加一个细延时单位T/M；当接收聚焦延时再需要调整时，D1变为D0，但D0状态只持续一个射频采样周期，然后变为D4稳定下来，直到下一次调整接收聚焦延时。所以称D0为暂态，而称D1至D4为稳态。D0状态与D4状态的插值系数是一样的，但在D0状态，延时FIFO停读一拍，第一锁存器34也停工一拍。插值变迹系数产生单元33的作用是把细延时代码映射为插值系数，并完成插值系数与通道加权系数的合并。第一加法器38是通道间串行求和链上的一个环节。Describedlinear interpolator 39 comprisesfirst multiplier 35,second adder 37 andfirst latch 34 andsecond multiplier 36 connected in sequence, the input end offirst latch 34 is connected withdynamic focus 32, the second The input terminals of thefirst multiplier 35 and thesecond multiplier 36 are connected to the interpolationapodization coefficient generator 33 , and the output terminal of thesecond multiplier 36 is connected with thesecond adder 37 . Thedelay memory 30 adopts a FIFO structure, and its depth is determined by the required maximum delay. The read and write clock CKO is a radio frequency sampling clock. Thedelay memory 30 and thelinear interpolator 39 respectively provide the coarse delay and the fine delay of the receiving channel, the coarse delay precision is equal to the radio frequency sampling interval T, and the fine delay precision is equal to T/M, and M is determined by the required delay precision , the value range of T is generally between 40 ns and 25 ns. M is equal to 4 in this example. The write enable of the delay memory is provided by thestart delay 31, and thestart delay 31 controls the write enable of thedelay memory 30 according to the initial coarse delay required by each receiving channel, and the required start of each receiving channel The start-to-refine delay is given by thedynamic focus 32 . When there are data samples written in the delay memories of all receiving channels, thedynamic focus 32 enables the reading of thedelay memories 30 of each channel, and also turns on the clock enable of thefirst latch 34 at the same time. The fine delay code s1s2s3s4 thatdynamic focus 32 outputs has five possible states: D0=0000, D1=1000, D2=0100, D3=0010, D4=0001, and the relation of linear interpolation coefficient a and b is: s1s2s3s4=1000 Then a=1, b=0; s1s2s3s4=0100 then a=3/4, b=1/4; s1s2s3s4=0010 then a=2/4, b=2/4; s1s2s3s4=0001 then a=1/4 , b=3/4; s1s2s3s4=0000 then a=1/4, b=3/4. During the dynamic adjustment of the receiving focus delay, the five possible states of the fine delay code change according to a cyclic law: D4 changes to D3, D3 changes to D2, D2 changes to D1, D1 changes to D0, and D0 changes to D4. Assuming that the current fine delay code status is D2=0100, when the receiving focus delay needs to be adjusted, D2 becomes D1, and the interpolation coefficient changes from a=3/4, b=1/4 to a=1, b=0, The output delay of the linear interpolator is increased by a fine delay unit T/M; when the receiving focus delay needs to be adjusted again, D1 becomes D0, but the D0 state only lasts for one RF sampling period, and then becomes D4 to stabilize until Adjust the receive focus delay next time. Therefore, D0 is called transient state, and D1 to D4 are called steady state. The interpolation coefficients of the D0 state and the D4 state are the same, but in the D0 state, the delay FIFO stops reading for one shot, and thefirst latch 34 also stops for one shot. The function of the interpolation apodizationcoefficient generation unit 33 is to map the fine delay codes into interpolation coefficients, and complete the combination of interpolation coefficients and channel weighting coefficients. Thefirst summer 38 is a link in the serial summing chain between the channels.

所述起始延时31包括起始延时计数器40、第二锁存器41、第一或门42和第一与门43；第二锁存器41的输入输出端分别连接数据存储器及其读控制器28和起始延时计数器40，第一与门43的输入输出端分别连接控制器8、起始延时计数器40和延时储存器30(图3)；起始延时计数器40是可装载计数器，它在接收期开始前装载起始粗延时数据，在接收期开始后以射频采样率计数，计满时开启延时储存器30的写使能。一个脉冲周期分成几个时段，首先是参数预置期，其次是脉冲发射期，然后是回波接收期，最后是延时FIFO的移位输出期。在参数预置期，第二锁存器41锁存本通道的起始粗延时数据；在脉冲发射期，起始粗延时数据加载计数器40；在回波接收器，计数器40开始计数，计满时打开延时FIFO的写使能，同时关闭计数器40的计数使能。Describedinitial delay 31 comprisesinitial delay counter 40,second latch 41, first ORgate 42 and first ANDgate 43; The input and output terminals ofsecond latch 41 are respectively connected data memory and itsRead controller 28 andinitial delay counter 40, the input and output end of the first ANDgate 43 connectscontroller 8,initial delay counter 40 and delay storage 30 (Fig. 3) respectively; Initial delay counter 40 It is a loadable counter, which loads the initial coarse delay data before the receiving period begins, counts at the radio frequency sampling rate after the receiving period begins, and opens the write enable of thedelay storage 30 when the count is full. A pulse cycle is divided into several periods, the first is the parameter preset period, the second is the pulse transmission period, then the echo reception period, and finally the delay FIFO shift output period. During the parameter preset period, thesecond latch 41 latches the initial coarse delay data of this channel; during the pulse transmission period, the initial coarse delay data is loaded into thecounter 40; at the echo receiver, thecounter 40 starts counting, Turn on the write enable of the delay FIFO when the count is full, and turn off the count enable of thecounter 40 at the same time.

所述动态聚焦32包括可装载循环移位寄存器50、第三锁存器51、第四锁存器52、第五锁存器53、第十锁存器55、第十一锁存器58和第十二锁存器59、第二或门54、第三或门56和第二与门57；寄存器50的data输入端经第三锁存器51连接数据存储器及其读控制器28，其en输入端经第二或门54、第五锁存器53、第四锁存器52连接数据存储器及其读控制器28，其load输入端直接连接控制器8(图4)；它在接收期开始前装载起始细延时数据，在接收进程中通过循环左移对起始延时进行动态的调整，以达到动态聚焦的目的。动态聚焦32的核心是一个5位的循环移位寄存器50。在参数预置期，第三锁存器51锁存本通道的起始细延时代码，起始细延时代码是四个稳态中的一个；在脉冲发射期，起始细延时代码加载循环移位寄存器的右四位。循环移位寄存器的右四位输出是细延时代码s1s2s3s4，它们的或输出在延时FIFO的移位输出期用来控制延时FIFO的读使能。在延时FIFO的移位输出期，第四锁存器52锁存聚焦延时动态调整数据，聚焦延时动态调整数据是1bit的数据流。在第四锁存器52锁存到一个高电平的时候，第五锁存器53把这个高电平变为一个相移脉冲，相移脉冲是宽度为射频采样周期的正脉冲，相移脉冲为第四锁存器52清零，也使循环移位寄存器左移一位。当循环移位寄存器中的1移到最左边时，会紧接一次移位，使细延时代码的D0状态只持续一个射频采样周期。Thedynamic focus 32 includes a loadable circular shift register 50, a third latch 51, a fourth latch 52, a fifth latch 53, a tenth latch 55, an eleventh latch 58 and The twelfth latch 59, the second OR gate 54, the third OR gate 56 and the second AND gate 57; the data input end of the register 50 is connected to the data memory and itsread controller 28 through the third latch 51, which The en input terminal is connected to the data memory and itsread controller 28 through the second OR gate 54, the fifth latch 53, and the fourth latch 52, and its load input terminal is directly connected to the controller 8 (Fig. 4); Load the initial fine-delay data before the start of the period, and dynamically adjust the initial delay by cyclically moving to the left during the receiving process to achieve the purpose of dynamic focus. The heart of thedynamic focus 32 is a 5-bit cyclic shift register 50 . In the parameter preset period, the third latch 51 latches the initial fine delay code of this channel, and the initial fine delay code is one of the four steady states; in the pulse transmission period, the initial fine delay code Load the right four bits of the circular shift register. The right four-bit output of the circular shift register is the fine delay code s1s2s3s4, and their OR output is used to control the read enable of the delay FIFO during the shift output period of the delay FIFO. During the shift output period of the delay FIFO, the fourth latch 52 latches the focus delay dynamic adjustment data, and the focus delay dynamic adjustment data is a 1-bit data stream. When the fourth latch 52 is latched to a high level, the fifth latch 53 turns the high level into a phase shift pulse, the phase shift pulse is a positive pulse with a width of the radio frequency sampling period, and the phase shift The pulse clears the fourth latch 52 and also shifts the rotate register left one bit. When the 1 in the circular shift register is moved to the leftmost, it will be shifted once, so that the D0 state of the fine delay code lasts only one RF sampling period.

所述插值变迹系数产生器33包括组合逻辑60、第六锁存器61、第七锁存器62、第八锁存器65和第九锁存器66、第三乘法器63和第四乘法器64；组合逻辑60把细延时代码映射为线性插值器的两个系数a和b，第六锁存器61和第七锁存器62构成两级变迹系数锁存器，在接收进程中变迹系数分时锁存到各通道第一级的变迹系数锁存器中，然后在同一时刻更新第二级锁存器的内容，变迹系数在第三乘法器63和第四乘法器64中分别与插值系数a和b相乘，最后由第八锁存器65和第九锁存器66分别输出变迹插值系数A和B，以达到动态变迹的目的(图5)。The interpolationapodization coefficient generator 33 includes acombination logic 60, asixth latch 61, aseventh latch 62, aneighth latch 65 and aninth latch 66, athird multiplier 63 and afourth Multiplier 64;Combination logic 60 is mapped to two coefficients a and b of the linear interpolator with fine delay code, and thesixth latch 61 and theseventh latch 62 constitute two-stage apodization coefficient latches, and receive In the process, the apodization coefficients are locked into the first-stage apodization coefficient latches of each channel in time-sharing, and then update the contents of the second-stage latches at the same time, and the apodization coefficients are stored in thethird multiplier 63 and the fourth multiplier. In themultiplier 64, the interpolation coefficients a and b are multiplied respectively, and finally theeighth latch 65 and theninth latch 66 respectively output the apodization interpolation coefficients A and B, so as to achieve the purpose of dynamic apodization (Fig. 5) .

所述数据存储器及其读控制器28包括延时数据存储器70和变迹数据存储器71以及两个数据读控制器；延时数据存储器70和变迹数据存储器71分别存储不同接收通道的聚焦延时数据和动态变迹数据。在延时数据存储器70中包含起始延时数据和动态调整数据，延时数据存储器70和变迹数据存储器71各有自己的读控制器。延时数据读控制器72提供给延时数据存储器70读地址，变迹数据读控制器73提供给变迹数据存储器71读地址，并给出各通道变迹数据的锁存脉冲(图6)。延时数据存储器70、变迹数据存储器71分别存储四个接收通道的聚焦延时数据和动态变迹数据。在延时数据存储器中包含起始延时数据和动态调整数据。延时数据存储器70、变迹数据存储器71各有自己的读控制器。延时数据读控制器提供给延时数据存储器70读地址，给出动态调整数据锁存脉冲CK1，还给出8个起始延时数据锁存脉冲，其中4个用来锁存四接收通道的起始粗延时数据，另4个则用来锁存四接收通道的起始细延时数据。变迹数据读控制器提供给变迹数据存储器71读地址，并给出四通道变迹数据的锁存脉冲。The data memory and itsread controller 28 include adelay data memory 70, anapodization data memory 71 and two data read controllers; thedelay data memory 70 and theapodization data memory 71 respectively store the focusing delays of different receiving channels data and dynamic apodization data. Thedelay data memory 70 contains initial delay data and dynamic adjustment data, and thedelay data memory 70 and theapodization data memory 71 each have their own read controllers. The delay data readcontroller 72 provides the read address for thedelay data memory 70, the apodization data readcontroller 73 provides the read address for theapodization data memory 71, and provides the latch pulse (Fig. 6) of the apodization data of each channel . Thedelay data memory 70 and theapodization data memory 71 respectively store focus delay data and dynamic apodization data of the four receiving channels. The initial delay data and dynamic adjustment data are included in the delay data memory. Thedelay data memory 70 and theapodization data memory 71 each have their own read controllers. The delay data read controller provides the read address for thedelay data memory 70, provides the dynamic adjustment data latch pulse CK1, and also provides 8 initial delay data latch pulses, 4 of which are used to latch the four receiving channels The initial coarse delay data, and the other four are used to latch the initial fine delay data of the four receiving channels. The apodization data read controller provides the read address for theapodization data memory 71, and provides the latch pulse of the four-channel apodization data.

Claims (10)

1, a kind of beam synthesizing method based on linear interpolation, this method comprises the steps:

I. the echo from target is received by each array element of popping one's head in, and signal that each probe array element connects separately receives treatment channel;

Ii. receive in treatment channel at each signal, be exaggerated from the signal of probe array element, then with unified speed digitizing;

Iii. the echoed signal after the digitizing is admitted to the processor that each signal receives treatment channel and handles;

It is characterized in that: the echoed signal after utilizing processor to digitizing is synthesized in the process of handling,

Iv. thick time-delay and the thin time-delay that provides signal to receive treatment channel respectively by delay memory with fifo structure and linear interpolation device, thick delay precision equals the radio frequency sampling interval T, and thin delay precision equals T divided by interpolation number of phases M;

V. all to have data sample to write fashionable for the time-delay reservoir that receives treatment channel when all signals, dynamic focusing open each signal receive the treatment channel delay memory read enable, and export the thin time-delay code S1S2S3S4 of five kinds of states, they are: a transient state D0=0000, four stable state D1=1000, D2=0100, D3=0010 and D4=0001; Each state each corresponding one group of linear interpolation coefficient a and b of thin time-delay code S1S2S3S4;

Vi. in the dynamic adjustment process of collectiong focusing time-delay, the code S1S2S3S4 that carefully delays time changes by the circulation law of D4 → D3 → D2 → D1 → D0 → D4, so that initial time-delay is dynamically adjusted, reaches the purpose of dynamic focusing;

Vii. when being circulated to transient state D0, FIFO time-delay reservoir stops reading a bat, the bat of also stopping work of the latch of linear interpolation device;

Viii. thin time-delay code is mapped as two interpolation coefficients, and interpolation coefficient and channel weighting coefficient are merged into change mark interpolation coefficient;

Ix. the output signal that merges of each passage is after device detects after testing, by the display screen video data.

2, the beam synthesizing method based on linear interpolation according to claim 1 is characterized in that: in described step e., the pass with linear interpolation coefficient a and b of the code S1S2S3S4 that carefully delays time is: S1S2S3S4=1000, then a=1, b=0; S1S2S3S4=0100, then a=3/4, b=1/4; S1S2S3S4=0010, then a=2/4, b=2/4; S1S2S3S4=0001, then a=1/4, b=3/4; S1S2S3S4=0000, then a=1/4, b=3/4.

3, the beam synthesizing method based on linear interpolation according to claim 1 is characterized in that: the span of described radio frequency sampling interval T is between 40ns～25ns, and interpolation number of phases M is generally 4.

4, a kind of beam synthesizer based on linear interpolation comprises:

Be used for the array element of respectively popping one's head in to tested body emission ultrasound wave and receiving target echo;

Be used to amplify each channel amplifier of echo that array element is exported of respectively popping one's head in;

Be used for the analog signal conversion of each channel amplifier is become each passage A/D transducer of digital signal;

Be used for each passage A/D digital signal that transducer is exported is focused on each channel processor that time-delay, weighting and serial summation are handled;

The above-mentioned array element of respectively popping one's head in, each channel amplifier, each passage A/D transducer and each channel processor be unidirectional in order connect and compose a plurality of mutually independently signal receive treatment channel; Also comprise:

Be used to store data-carrier store and Read Controller (28) and the controller (8) that each passage focuses on delay data and becomes the mark data, all signals receive the output signal of treatment channel and synthesize after detecting device (6) send display (9) to show at last; It is characterized in that described each channel processor comprises:

Time-delay reservoir (30) with fifo structure is used to provide signal to receive the thick time-delay of treatment channel;

Linear interpolation device (39) is used to provide signal to receive the thin time-delay of treatment channel;

Dynamic focusing (32) is used for providing to time-delay reservoir (30) and reads to enable control, and provides thin Delay-Code;

Initial time-delay (31) is used for writing of control time-delay reservoir (30) and enables, and reaches the purpose of the initial time-delay of control;

Interpolation trace-changing coefficient generator (33) is used for thin Delay-Code is mapped as interpolation coefficient, and calculates change mark interpolation coefficient;

The signal input port of linear interpolation device (39) connects time-delay reservoir (30), dynamic focusing (32) and interpolation trace-changing coefficient generator (33) respectively, and its signal output part is through first adder (38) connection detector (6).

5, the beam synthesizer based on linear interpolation according to claim 4, it is characterized in that: described linear interpolation device (39) comprises first multiplier (35), second adder (37) and first latch (34) and second multiplier (36) that is linked in sequence, the clock Enable Pin of first latch (34) connects dynamic focusing (32), the input end of first multiplier (35) and second multiplier (36) is connected interpolation trace-changing coefficient generator (33), and the output terminal of second multiplier (36) is connected with second adder (37).

6, the beam synthesizer based on linear interpolation according to claim 4 is characterized in that: described initial time-delay (31) comprises initial delay counter (40), second latch (41), first or door (42) and first and (43); The input/output terminal of second latch (41) connects data-carrier store and Read Controller (28) and initial delay counter (40) respectively, and first is connected controller (8), initial delay counter (40) respectively and the reservoir (30) of delaying time with the input/output terminal of door (43); Initial delay counter (40) is to load counter, and it loads initial thick delay data before the take over period begins, and begins the back with radio frequency sampling rate counting in the take over period, opens writing of time-delay reservoir (30) when meter is full and enables.

7, the beam synthesizer based on linear interpolation according to claim 4 is characterized in that: described dynamic focusing (32) but comprise loader cycle shift register (50), the 3rd latch (51), quad latch (52), the 5th latch (53), the tenth latch (55), the 11 latch (58) and the 12 latch (59), second or door (54), the 3rd or door (56) and second and (57); The data input end of register (50) connects data-carrier store and Read Controller (28) thereof through the 3rd latch (51), its en input end through second or door (54), the 5th latch (53), quad latch (52) connect data-carrier store and Read Controller (28) thereof, its load input end directly connects controller (8); It loads initial thin delay data before the take over period begins, by ring shift left initial time-delay is adjusted dynamically in receiving process, to reach the purpose of dynamic focusing.

8, the beam synthesizer based on linear interpolation according to claim 4 is characterized in that: described interpolation trace-changing coefficient generator (33) comprises combinational logic (60), the 6th latch (61), the 7th latch (62), the 8th latch (65) and the 9th latch (66), the 3rd multiplier (63) and the 4th multiplier (64); Combinational logic (60) is mapped as thin time-delay code two the coefficient a and the b of linear interpolation device, the 6th latch (61) and the 7th latch (62) constitute two-stage trace-changing coefficient latch, the trace-changing coefficient timesharing is latched in the trace-changing coefficient latch of each passage first order in receiving process, upgrade the content of second level latch then at synchronization, trace-changing coefficient multiplies each other with interpolation coefficient a and b respectively in the 3rd multiplier (63) and the 4th multiplier (64), export change mark interpolation coefficient A and B respectively by the 8th latch (65) and the 9th latch (66) at last, to reach the purpose of dynamic change mark.

9, the beam synthesizer based on linear interpolation according to claim 4 is characterized in that: described data-carrier store and Read Controller thereof (28) comprise delay data storer (70) and become mark data-carrier store (71) and two data Read Controllers; Delay data storer (70) is stored the focusing delay data of different receiving cables respectively and is dynamically become the mark data with change mark data-carrier store (71); Comprise initial delay data and dynamic adjusting data in delay data storer (70), delay data storer (70) and change mark data-carrier store (71) respectively have the Read Controller of oneself; Delay data Read Controller (72) offers delay data storer (70) and reads the address, and change mark data Read Controllers (73) offer change mark data-carrier store (71) and read the address, and provides the latch pulse that each passage becomes the mark data.

10, the beam synthesizer based on linear interpolation according to claim 5, it is characterized in that: first latch (34) of described linear interpolation device (39) has a clock and enables control end, the sample that is used for the last output of temporary time-delay reservoir (30), and its clock enables control end and time-delay reservoir (30) dress reads to enable a shared signal.

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