CN1301426C - Liquid crystal display panel with narrow frame design and manufacturing method thereof - Google Patents
Liquid crystal display panel with narrow frame design and manufacturing method thereofDownload PDFInfo
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- CN1301426C CN1301426CCNB031537529ACN03153752ACN1301426CCN 1301426 CCN1301426 CCN 1301426CCN B031537529 ACNB031537529 ACN B031537529ACN 03153752 ACN03153752 ACN 03153752ACN 1301426 CCN1301426 CCN 1301426C
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Abstract
Translated fromChinese
Description
Technical field
The present invention relates to a kind of display panels, particularly about a kind of display panels border width that dwindles, with display panels of the narrow frame design that improves indication range and preparation method thereof.
Background technology
(liquid crystal display is to turn to by driving liquid crystal molecule LCD) to display panels, and the penetrability that changes liquid crystal layer is to reach the purpose of demonstration.Turn in order to drive liquid crystal molecule, liquid crystal layer be manufactured with an electrode layer up and down respectively, drive the required driving voltage of liquid crystal molecule to provide.Wherein, lower electrode layer is the metallic conduction electrode of a tool low work function (Low Work Function), as electron emission layer, the lower electrode layer material can be that lithium (Li), magnesium (Mg), calcium (Ca), aluminium (Al), silver (Ag), indium (In) wait and alloy, and how meter its thickness generally be about 100～400.And upper electrode layer is a transparency conducting layer, with as the hole emission layer.The most normal transparent conductive material that uses is indium tin oxide (ITO) at present.
Please refer to Fig. 1, show a typical display panels 1, comprise that a color panel 10 and a thin-filmtransistor display panel 30, one liquid crystal layers 20 are that clamping is between color panel 10 and thin-film transistor display panel 30.Upper surface at thin-filmtransistor display panel 30 is manufactured with a thin film transistor (TFT) array, and wherein, each thin film transistor (TFT) is to be connected with a pixel electrode, and the lower surface at color panel 10 is manufactured with community electrode.By the potential difference (PD) between common electrode and pixel electrode, liquid crystal molecule turns in the liquid crystal layer 20 to drive.
Please refer to Fig. 2 A, this figure is the vertical view of a typical thin film transistor display panel 30.The upper surface of this thin-filmtransistor display panel 30 can be divided into arectangular display area 310 and a frame zone 320.Rectangular display area 310 is the middle positions that are positioned at this thin-filmtransistor display panel 30, andframe region 320 is surrounded this rectangular display area 310.Please refer to Fig. 2 B and Fig. 2 C, Fig. 2 B is corresponding to the position D among Fig. 2 A, and Fig. 2 C is the diagrammatic cross-section corresponding to Fig. 2 B a-a ' line of cut.One thin film transistor (TFT), 330 arrays are to be made on the rectangular display area 310.The gate of same row thin film transistor (TFT) 330 is to link to each other with agate line 340, be to link to each other with asignal wire 350 with the source electrode of delegation's thin film transistor (TFT) 330, and the drain electrode of each thin film transistor (TFT) 330 is connected with apixel electrode 60 respectively.In addition, a plurality ofplain conductors 322 are to be made on theframe region 320, and eachplain conductor 322 is connected to an above-mentionedgate line 340 respectively.By this, agate drive circuit 360 can be by the sequential that scans ofplain conductor 322 control sluicepolar curves 340.
Generally speaking, in order to simplify processing procedure, the gate of each thin film transistor (TFT) 330,gate line 340 andplain conductor 322 are to be made in one deck metal level.Yet, be subjected to the restriction of the size of contaminate particulate in the resolution of micro-photographing process and the processing environment, must havecertain intervals 322 of each plain conductors, to avoid producing short circuit.Therefore, on thin-film transistor display panel, must reserveenough frame region 320 holding above-mentionedplain conductor 322, and cause the size ofviewing area 310 to be restricted, can't further strengthen.
In view of this, the present invention proposes the display panels that a kind of new narrow frame designs, and with the width of reduction frame region, and uses and improves in the display panels, the ratio that the viewing area is shared.
Summary of the invention
The present invention proposes a kind ofly can to reach display panels of the narrow frame design of dwindling size of display panels and preparation method thereof by the width that reduces frame region.
The technical scheme that realizes the display panels that narrow frame of the present invention designs is as follows:
A kind of display panels of narrow frame design comprises at least:
One glass substrate, the upper surface of this glass substrate can be divided into a viewing area and a frame zone, a plurality of pixel components are that array distribution is on this viewing area, and each this pixel components includes a thin film transistor (TFT) controlling the demonstration of this pixel components, and this frame region is to surround this viewing area;
A plurality of first leads are made on this frame region, in order to control the switch of those thin film transistor (TFT)s of a part;
One dielectric layer is made on this frame region, and covers this first lead; And
A plurality of second leads are made on this dielectric layer, in order to control the switch of remaining this thin film transistor (TFT).
The display panels of described narrow frame design, it is characterized in that: the gate of this first lead and this thin film transistor (TFT) is to be positioned at one deck metal level, and the source electrode of this second lead and this thin film transistor (TFT) and drain electrode are to be positioned at one deck metal level.
The display panels of described narrow frame design, it is characterized in that: those first leads and those second leads are the edges along this viewing area, are made at certain intervals on this frame region.
The display panels of described narrow frame design, it is characterized in that: this dielectric layer is a silicon nitride layer.
The present invention also provides a kind of method for making of two-d display panel, and this two-d display panel includes the demonstration that a plurality of thin film transistor (TFT)s are controlled each pixel, and this method for making comprises the following steps: at least
Make a plurality of gate lines and a plurality of first lead on a glass substrate, and those first leads are to connect those gate lines of a part;
Make a dielectric layer on this glass substrate, and cover those gate lines and those first leads; And
Make a plurality of source electrodes, a plurality of drain electrode and a plurality of second lead on this dielectric layer, and those second leads are to connect remaining those gate line.
The method for making of the display panels of described narrow frame design, it is characterized in that: the step of making this gate line and this first lead comprises:
Make a first metal layer on this glass substrate; And
This first metal layer of etching is forming those gate lines and those first leads, and those first leads are to connect those gate lines of a part.
The method for making of the display panels of described narrow frame design, it is characterized in that: the step of making this second lead comprises:
Make one second metal level on this dielectric layer;
This second metal level of etching is to form those source electrodes, those drain electrodes and those second leads;
Make a protective seam on this dielectric layer, and cover those source electrodes, those drain electrodes and those second leads;
This protective seam of etching forms a plurality of windows to expose those second leads and remaining those gate line; And
Make a plurality of syndetons on this protective seam, and insert among those windows, make those second leads connect remaining those gate line respectively.
The method for making of the display panels of described narrow frame design, it is characterized in that: this glass substrate can be divided into a viewing area and a frame zone, this gate line is to be made on this viewing area, this first lead and this second wire producing are on this frame region, and this frame region is to surround this viewing area.
The method for making of the display panels of described narrow frame design, it is characterized in that: those first leads and those second leads are the edges along this viewing area, are made at certain intervals on this frame region.
The method for making of the display panels of described narrow frame design, it is characterized in that: this dielectric layer is to make with silicon nitride material.
The disclosed two-d display panel of the present invention comprises a glass substrate, a plurality of first lead, a dielectric layer and a plurality of second lead at least.Can divide into a viewing area and a frame zone at the glass substrate upper surface, a plurality of pixel components are that array distribution is on the viewing area, frame region is to surround the viewing area, and each pixel components includes the demonstration of a thin film transistor (TFT) with the control pixel components.
First lead is to be made on the frame region, and in order to controlling the switch of a part of above-mentioned thin film transistor (TFT), and dielectric layer is to be made on the frame region, and cover above-mentioned first lead, simultaneously, second lead is to be made on the dielectric layer, in order to control the switch of all the other above-mentioned thin film transistor (TFT)s.
The invention has the advantages that:
Compared to the frame design of traditional display panels, design of the present invention has following characteristic:
When needed gate line quantity is n, in traditional frame design, must production quantity be the plain conductor of n, and frame design of the present invention, utilization is made in first lead and second lead of different metal layer, the function that replaces original plain conductor, therefore, the quantity of required first lead and second lead is n/2.In addition, under the situation of same process condition,, must keep a preset distance to prevent to produce short circuit between each plain conductor, between each first lead and between each second lead.Therefore, by frame of the present invention design, can reduce border width to original half.
In display panels of the present invention,, increased the shared ratio of indication range size and viewing area of display panels because the reduction of the width of frame is relative.
Can will be further understood by following specific embodiment and detailed description in conjunction with the accompanying drawings about the advantages and spirit of the present invention.
Description of drawings
Fig. 1 is the synoptic diagram of a known display panels.
Fig. 2 A, B and C are the synoptic diagram of a known thin-film transistor display panel.
Fig. 3 A to D is the synoptic diagram of thin-film transistor display panel one preferred embodiment of the present invention.
Fig. 4 A to D is the synoptic diagram that thin-film transistor display panel of the present invention is made flow process one preferred embodiment.
Embodiment
Shown below, be display panels one preferred embodiment of the present invention.Please refer to Fig. 1, a display panels 1 comprises that a color panel 10 and a thin-filmtransistor display panel 30, one liquid crystal layers 20 are that clamping is between color panel 10 and thin-film transistor display panel 30.Upper surface at thin-filmtransistor display panel 30 is manufactured with a thin film transistor (TFT) array, and each thin film transistor (TFT) is to be connected with a pixel electrode, and the lower surface at color panel 10 is manufactured with community electrode.By the potential difference (PD) between common electrode and pixel electrode, drive liquid crystal layer 20 interior liquid crystal molecules and turn to.
Please refer to Fig. 3 A, the upper surface of thin-filmtransistor display panel 30 can be divided into arectangular display area 310 and a frame zone 320.Wherein,rectangular display area 310 is positioned at the middle position of thin-filmtransistor display panel 30, andframe region 320 is surrounded this rectangular display area 310.Please refer to Fig. 3 B, is corresponding to the position E among Fig. 3 A.One thin film transistor (TFT) array is to be made on the rectangular display area 310.The gate of same row thin film transistor (TFT) 330 is to link to each other with agate line 340, be to link to each other with asignal wire 350 with the source electrode of delegation's thin film transistor (TFT) 330, and the drain electrode of each thin film transistor (TFT) is connected with apixel electrode 60 respectively.
Please refer to Fig. 3 B and Fig. 3 C, wherein, Fig. 3 C is the diagrammatic cross-section corresponding to Fig. 3 B b-b ' line of cut.A plurality offirst leads 324 are the edges along above-mentioned rectangular display area, be made on theframe region 320, and adielectric layer 326 are to be made on theframe region 320, cover above-mentioned first lead 324.In addition, a plurality ofsecond leads 328 are the edges along rectangular display area, are made on thedielectric layer 326, and aprotective seam 341 is to be made onsecond lead 328 and the dielectric layer 326.Above-mentionedfirst lead 324 is thegate lines 340 that are connected with a part, and above-mentionedsecond lead 328 is to connect remaining gate line 340.By this, agate drive circuit 360 can be by the sequential that scans of above-mentionedfirst lead 324 and second lead, 328 control sluicepolar curves 340.
It should be noted thatsecond lead 328 andgate line 340 are to be made in different metal levels.Please refer to Fig. 3 D, is corresponding to Fig. 3 B c-c ' line of cut.Must the two be linked to each other by a syndeton betweensecond lead 328 andgate line 340, this syndeton comprisesfirst connector 372,conductive connecting line 374 and second connector 376.Above-mentionedfirst connector 372 is to run throughdielectric layer 326 andprotective seam 341, andsecond connector 376 is to run through protective seam 341.Conductive connecting line 374 is the upper surfaces that are made indielectric layer 341, and by above-mentionedfirst connector 372 andsecond connector 376, connects thegate line 340 andsecond lead 328 respectively.With regard to a preferred embodiment, thisconductive connecting line 374 is to be made in same conductive layer withpixel electrode 60, and general often makes with indium tin oxide.Otherwise,, promptly do not have this problem and exist becausefirst lead 324 is to be made in one deck metal level withgate line 340.
Please refer to Fig. 4 A to Fig. 4 D, show a preferred embodiment of thin-filmtransistor display panel 30 making flow processs of the present invention.At first, shown in Fig. 4 A, deposit a metal level on a glass baseplate, and a plurality ofgates 331 of a plurality offirst leads 324, a plurality ofgate line 340 and thin film transistor (TFT) array are made in etching.Thegate 331 of same row is to be connected with agate line 340, and thegate line 340 of a part is to be connected to those first leads 324.Subsequently, make adielectric layer 326 on glass baseplate, cover above-mentionedfirst lead 324,gate line 340 and gate 331.Please refer to Fig. 4 B, then deposit a metal level ondielectric layer 326, and this metal level of etching, multiple source, thedrain electrode second leads 328, a plurality ofsignal wire 350 and thin film transistor (TFT) 330 arrays made.And eachsecond lead 328 isgate lines 340 that correspondence one is not connected withfirst lead 324.
Subsequently; please refer to Fig. 4 C, make aprotective seam 341 on glass baseplate, cover above-mentionedsecond lead 328,signal wire 350 and source-drain electrode protective seam 341, makeopening second lead 328 and corresponding gate line 340.At last; please refer to Fig. 4 D; make an indium tin oxide layer onprotective seam 341; and insert in above-mentionedopening pixel electrodes 60 and a plurality of syndetons; and each syndeton has onefirst connector 372, aconductive connecting line 374 and onesecond connector 376, uses to connectsecond lead 328 andcorresponding gate line 340.
Under the situation of preferred embodiment,first lead 324 andsecond lead 328 all are parallel to the marginal distribution ofrectangular display area 310, simultaneously,dielectric layer 326 can select for use silicon nitride as deposition materials, to reach the good isolation effect atfirst lead first lead 324 andsecond lead 328, influence the normal demonstration in the rectangular display area 310.The interval at the most inboardfirst lead 324 andrectangular display area 310 edges is the intervals greater than adjacent 2 first leads 324, and the interval at the most inboardsecond lead 328 andrectangular display area 310 edges is the intervals greater than adjacent 2 second leads 328.Simultaneously, be subjected to the influence of peripheral environment for the signal transmission of avoidingfirst lead 324 andsecond lead 328, the interval of outermostfirst lead 324 andframe region 320 outer rims, it is interval greater than adjacent 2 first leads 324, and, the interval of outermostsecond lead 328 andframe region 320 outer rims is the intervals greater than adjacent 2 second leads 328.
Please refer to Fig. 3 A,first lead 324 andsecond lead 328 are the long limits, left side that are made in frame region 320.Yet if demand in other design is arranged, above-mentionedfirst lead 324 andsecond lead 328 can also be made in the long limit, right side offrame region 320 and minor face up and down.In addition, above-mentionedfirst lead 324 is not limited only to be connectedgate line 340 withsecond lead 328, and other circuit that is made on the thin-filmtransistor display panel 30 can also carry out the signal transmission byfirst lead 324 andsecond lead 328.
The above is to utilize preferred embodiment to describe the present invention in detail, but not limit the scope of the invention, and know this type of skill personage and all can understand, suitably do slightly change and adjustment, will not lose main idea of the present invention place, also not break away from the spirit and scope of the present invention.
Claims (10)
1, a kind of display panels of narrow frame design comprises at least:
One glass substrate, the upper surface of this glass substrate can be divided into a viewing area and a frame zone, a plurality of pixel components are that array distribution is on this viewing area, and each this pixel components includes a thin film transistor (TFT) controlling the demonstration of this pixel components, and this frame region is to surround this viewing area; It is characterized in that:
A plurality of first leads are made on this frame region, and connect the gate line of a part of thin film transistor (TFT), to control the switch of this part thin film transistor (TFT);
One dielectric layer is made on this frame region, and covers this first lead; And
A plurality of second leads are made on this dielectric layer, and connect the gate line of remainder thin film transistor (TFT), with the switch of control remainder thin film transistor (TFT).
2, the display panels of narrow frame design according to claim 1, it is characterized in that: the gate of this first lead and this thin film transistor (TFT) is to be positioned at one deck metal level, and the source electrode of this second lead and this thin film transistor (TFT) and drain electrode are to be positioned at one deck metal level.
3, the display panels of narrow frame design according to claim 1, it is characterized in that: those first leads and those second leads are the edges along this viewing area, are made at certain intervals on this frame region.
4, the display panels of narrow frame design according to claim 1, it is characterized in that: this dielectric layer is a silicon nitride layer.
5, a kind of method for making of two-d display panel, this two-d display panel includes the demonstration that a plurality of thin film transistor (TFT)s are controlled each pixel, and this method for making comprises the following steps: at least
Make a plurality of gate lines and a plurality of first lead on a glass substrate, and those first leads are to connect those gate lines of a part;
Make a dielectric layer on this glass substrate, and cover those gate lines and those first leads; And
Make a plurality of source electrodes, a plurality of drain electrode and a plurality of second lead on this dielectric layer, and those second leads are to connect remaining those gate line.
6, the method for making of the display panels of narrow frame design according to claim 5, it is characterized in that: the step of making this gate line and this first lead comprises:
Make a first metal layer on this glass substrate; And
This first metal layer of etching is forming those gate lines and those first leads, and those first leads are to connect those gate lines of a part.
7, the method for making of the display panels of narrow frame design according to claim 5, it is characterized in that: the step of making this second lead comprises:
Make one second metal level on this dielectric layer;
This second metal level of etching is to form those source electrodes, those drain electrodes and those second leads;
Make a protective seam on this dielectric layer, and cover those source electrodes, those drain electrodes and those second leads;
This protective seam of etching forms a plurality of windows to expose those second leads and remaining those gate line; And
Make a plurality of syndetons on this protective seam, and insert among those windows, make those second leads connect remaining those gate line respectively.
8, the method for making of the display panels of narrow frame design according to claim 5, it is characterized in that: this glass substrate can be divided into a viewing area and a frame zone, this gate line is to be made on this viewing area, this first lead and this second wire producing are on this frame region, and this frame region is to surround this viewing area.
9, the method for making of the display panels of narrow frame design according to claim 5, it is characterized in that: those first leads and those second leads are the edges along this viewing area, are made at certain intervals on this frame region.
10, the method for making of the display panels of narrow frame design according to claim 5, it is characterized in that: this dielectric layer is to make with silicon nitride material.
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| CNB031537529ACN1301426C (en) | 2003-08-19 | 2003-08-19 | Liquid crystal display panel with narrow frame design and manufacturing method thereof |
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| CNB031537529ACN1301426C (en) | 2003-08-19 | 2003-08-19 | Liquid crystal display panel with narrow frame design and manufacturing method thereof |
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| CN1301426Ctrue CN1301426C (en) | 2007-02-21 |
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| CN101515589B (en)* | 2007-06-15 | 2011-05-04 | 友达光电股份有限公司 | Pixel structure, display panel, optoelectronic device and method for forming same |
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| CN101487962B (en)* | 2009-01-20 | 2012-07-04 | 友达光电股份有限公司 | Display equipment with narrow frame structure and its driving method |
| CN101582422B (en)* | 2009-06-01 | 2012-05-23 | 友达光电股份有限公司 | Display device |
| CN101587266B (en)* | 2009-06-29 | 2011-01-26 | 友达光电股份有限公司 | display device |
| US9190421B2 (en)* | 2011-08-18 | 2015-11-17 | Lg Display Co., Ltd. | Display device and fabrication method thereof |
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| KR101981531B1 (en)* | 2012-10-19 | 2019-05-23 | 엘지디스플레이 주식회사 | Touch screen panel |
| KR102007831B1 (en)* | 2012-12-14 | 2019-08-06 | 엘지디스플레이 주식회사 | Narrow bezel type array substrate for liquid crystal display device |
| KR101400112B1 (en)* | 2012-12-18 | 2014-05-27 | 엘지디스플레이 주식회사 | Liquid crystal display device having dual link structure and fabricating method thereof |
| CN103941500B (en)* | 2013-12-11 | 2017-10-24 | 上海天马微电子有限公司 | Display panel and display device |
| TWI676848B (en)* | 2018-04-25 | 2019-11-11 | 友達光電股份有限公司 | Display panel |
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| CN1584712A (en) | 2005-02-23 |
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